Advanced Nanoscale MOSFET Architectures E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Fachliteratur
• Sprache: Englisch

Seitenzahl: 507

Veröffentlichungsjahr: 2024

Beschreibung

Comprehensive reference on the fundamental principles and basic physics dictating metal-oxide-semiconductor field-effect transistor (MOSFET) operation Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal-oxide-semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs. Additional topics covered include: * High-k gate dielectrics and metal gate electrodes for multi-gate MOSFETs, covering gate stack processing and metal gate modification * Strain engineering in 3D complementary metal-oxide semiconductors (CMOS) and its scaling impact, and strain engineering in silicon-germanium (SiGe) FinFET and its challenges and future perspectives * TCAD simulation of multi-gate MOSFET, covering model calibration and device performance for analog and RF applications * Description of the design of an analog amplifier circuit using digital CMOS technology of SCL for ultra-low power VLSI applications Advanced Nanoscale MOSFET Architectures helps readers understand device physics and design of new structures and material compositions, making it an important resource for the researchers and professionals who are carrying out research in the field, along with students in related programs of study.

Leseprobe

Table of Contents

Cover

Table of Contents

Title Page

Copyright

About the Editors

List of Contributors

Preface

Acknowledgments

1 Emerging MOSFET Technologies

1.1 Introduction: Transistor Action

1.2 MOSFET Scaling

1.3 Challenges in Scaling the MOSFET

1.4 Emerging MOSFET Architectures

1.5 Organization of this Book

References

2 MOSFET: Device Physics and Operation

2.1 Introduction to MOSFET

2.2 Advantages of MOSFET

2.3 Applications of MOSFETs

2.4 Types of MOSFETs

2.5 Band Diagram of MOSFET

2.6 MOSFET Regions of Operation

2.7 Scaling of MOSFET

2.8 Short‐channel Effects

2.9 Body Bias Effect

2.10 Advancement of MOSFET Structures

References

3 High‐

κ

Dielectrics in Next Generation VLSI/Mixed Signal Circuits

3.1 Introduction to Gate Dielectrics

3.2 High‐

κ

Dielectrics in Metal–Oxide–Semiconductor Capacitors

3.3 High‐

κ

Dielectrics in Metal Insulator Metal (MIM) Capacitors

3.4 MOSFETs Scaling and the Need of High‐

κ

3.5 High‐

κ

Dielectrics in Next Generation Transistors

References

4 Consequential Effects of Trap Charges on Dielectric Defects for MU‐G FET

4.1 Introduction

4.2 TID Effects Overview

4.3 Application Area of Device for TID Effect Analysis

4.4 Near the Earth: Trapped Radiation

4.5 Ionizing Radiation Effect in Silicon Dioxide (SiO

2

)

4.6 TID Effects in CMOS

4.7 TID Effects in Bipolar Devices

4.8 Understanding and Modeling a‐SiO

2

Physics

4.9 Hydrogen (H

2

) Reaction with Trapped Charges at Insulator

4.10 Pre‐Existing Trap Density and their Respective Location

4.11 Use of High‐K Dielectric in MU‐G FET

4.12 Properties of Trap in the High‐K with Interfacial Layer

4.13 Trap Extraction Techniques

4.14 Conclusion

References

5 Strain Engineering for Highly Scaled MOSFETs

5.1 Introduction

5.2 Simulation Approach

5.3 Case Study

5.4 Conclusions

References

6 TCAD Analysis of Linearity Performance on Modified Ferroelectric Layer in FET Device with Spacer

6.1 Introduction

6.2 Simulation and Structure of Device

6.3 Results and Analysis

6.4 Conclusion

Acknowledgment

References

7 Electrically Doped Nano Devices: A First Principle Paradigm

7.1 Introduction

7.2 Electrical Doping

7.3 First Principle

7.4 Molecular Simulation

7.5 Conclusion

References

8 Tunnel FET: Principles and Operations

8.1 Introduction to Quantum Mechanics and Principles of Tunneling

8.2 Tunnel Field‐Effect Transistor

8.3 Challenges of Tunnel Field‐Effect Transistor

8.4 Techniques for Improving Electrical Performance of Tunnel Field‐Effect Transistor

8.5 Conclusion

References

9 GaN Devices for Optoelectronics Applications

9.1 Introduction

9.2 Properties of GaN‐Based Material

9.3 GaN LEDs

9.4 GaN Lasers

9.5 GaN HEMTs for Optoelectronics

9.6 GaN Sensors

References

10 First Principles Theoretical Design on Graphene‐Based Field‐Effect Transistors

10.1 Introduction

10.2 Graphene

10.3 Graphene/‐BN Hybrid Structure

10.4 Conclusions

Acknowledgments

References

11 Performance Analysis of Nanosheet Transistors for Analog ICs

11.1 Introduction

11.2 Evolution of Nanosheet Transistors

11.3 TCAD Modeling of Nanosheet Transistor

11.4 Transistor's Analog Performance Parameters

11.5 Challenges and Perspectives of Modern Analog Design

References

12 Low‐Power Analog Amplifier Design using MOS Transistor in the Weak Inversion Mode

12.1 Introduction

12.2 Review of the Theory of Weak Inversion Mode Operation of MOS Transistor

12.3 Design Steps for Transistor Sizing Using the IC

12.4 Design Examples

12.5 Summary

References

13 Ultra‐conductive Junctionless Tunnel Field‐effect Transistor‐based Biosensor with Negative Capacitance

13.1 Introduction

13.2 Importance of SS and

I

ON

/

I

OFF

in Biosensing

13.3 Importance of Dopingless Source and Drain in High Conductivity

13.4 Relation of Negative Capacitance with Non‐hysteresis and Effect on Biosensing

13.5 Variation of Source Material on Biosensing

13.6 Importance of Dual Gate and Ferroelectricity on Biosensing

13.7 Effect of Dual Material Gate on Biosensing

References

14 Conclusion and Future Perspectives

14.1 Applications

14.2 Some Recent Developments

14.3 Future Perspectives

14.4 Conclusion

References

Index

End User License Agreement

List of Tables

Chapter 2

Table 2.1 Parameters of MOSFET before and after scaling.

Chapter 4

Table 4.1 Trap charge property near the interface region.

Chapter 5

Table 5.1 Geometrical details of the virtually fabricated FinFET as shown i...

Table 5.2 Device details of SNSFETs used in the simulation.

Chapter 6

Table 6.1 The Parameter of the proposed device (NCFET (spacer)).

Table 6.2 Constraint of analog and digital implementation for NCFETs and NC...

Chapter 9

Table 9.1 A material parameter of compound semiconductors with Si at 300 K....

Table 9.2 Comparison of bandgap and Varshni parameters for different compou...

Table 9.3 Different colors of LEDs for different semiconductor materials.

Chapter 10

Table 10.1 Interlayer distances and formation energies of two‐layer and fou...

Chapter 11

Table 11.1 NST Device Dimensions and Physical Parameters for TCAD Calibrati...

Chapter 12

Table 12.1 Tabulated study of various performance parameters of the CS stag...

Table 12.2 Table summarizing the dimensions of the transistors in the propo...

Table 12.3 Tabulated report of the derived and simulated results of importa...

Table 12.4 Table of simulation results of the OTA circuit.

Chapter 13

Table 13.1 Device simulations parameters (Replacing the conventional insula...

List of Illustrations

Chapter 1

Figure 1.1 Schematic diagram of the Conventional Bulk MOSFET Structure.

Figure 1.2 Schematic diagram of tunnel FET.

Figure 1.3 Schematic 3D view and a cross‐sectional view of a cylindrical FET...

Figure 1.4 Schematic diagram of a gate‐all‐around nanosheet FET [36]/MDPI/CC...

Figure 1.5 (a) Schematic diagram of the DFR‐negative capacitance FET, (b) eq...

Figure 1.6 A sketch of the graphene FET [39]/MDPI/CC by 4.0.

Chapter 2

Figure 2.1 Structure of a basic MOSFET.

Figure 2.2 Classification of MOSFET.

Figure 2.3 Symbol of (a) depletion mode of P‐type and (b) N‐type MOSFET (c) ...

Figure 2.4 MOS capacitor structure.

Figure 2.5 Energy band diagram of the Metal–Oxide–Semiconductor system.

Figure 2.6 Energy band diagram of combined MOS system.

Figure 2.7 Energy band diagram in accumulation region.

Figure 2.8 Energy band diagram in the depletion region.

Figure 2.9 Energy band diagram in inversion region.

Figure 2.10 Drain voltage vs. drain current characteristics of N‐ and P‐Chan...

Figure 2.11 Gate metal last fabrication process. (a) High‐

j

dielectric and p...

Figure 2.12 Analysis of DIBL.

Figure 2.13 Transfer curves of device for

V

...

Figure 2.14 The concept of GIDL.

Figure 2.15 Body bias effect for a PMOS transistor.

Figure 2.16 DG MOSFET's primary structure.

Figure 2.17 JL MOSFET with S and D extensions.

Figure 2.18 N‐type junction less double gate MOSFET structure.

Figure 2.19 Construction of DSBO‐SOI MOSFET.

Figure 2.20 JLDG structure.

Figure 2.21 Junction Less MOSFET – Underlapping at the D end of the channel....

Figure 2.22 Structure of Si‐supported MOSFET.

Figure 2.23 Black Phosphorous‐based Junction Less Recessed Channel (BP JL‐RC...

Figure 2.24 The structure of DMSG MOSFET.

Figure 2.25 GC‐DMGJLT arrangement.

Figure 2.26 JL MOSFET for identifying biomolecules.

Figure 2.27 A pocket n‐MOSFET arrangement.

Figure 2.28 Structure of EJ‐SOI MOSFET.

Figure 2.29 AGJL MOSFET structure.

Figure 2.30 Recessed channel MOSFET.

Figure 2.31 N‐type JLDG MOSFET structure.

Figure 2.32 DMG with recessed S and D UTB silicon on insulator MOSFET.

Chapter 3

Figure 3.1 Gate leakage current density vs. SiO

2

physical thickness.

Chapter 4

Figure 4.1 Ionizing dosage in SiO

2

‐on‐Si structures is depicted graphically ...

Figure 4.2 Trapped proton belt at Earth atmosphere [5]/NASA/Public Domain.

Figure 4.3 Trapped electron belt at Earth atmosphere [5]/NASA/Public Domain....

Figure 4.4 South Atlantic trapped region [5]/NASA/Public Domain.

Figure 4.5 South Atlantic and electron distribution on Earth [5]/NASA/Public...

Figure 4.6 Photon‐matter interaction type as a function of atomic number (

Z

)...

Figure 4.7 (a) Illustration showing the effect of fixed oxide trapped charge...

Figure 4.8 An illustration of how surface SRH (SSRH) recombination is induce...

Figure 4.9 2D representation of the GLPNP test structure. Adapted from [12]....

Figure 4.10 Gate sweep responses of the GLPNP base current before and after ...

Figure 4.11 Band diagram showing the interactions between shallow and deep t...

Figure 4.12 Representation of

V

Oδ

., which formed after the removal of a...

Figure 4.13 Trap charges at different interfaces in stack gate oxide structu...

Chapter 5

Figure 5.1 Stress distribution (von Mises,

xx

‐ and

yy

‐direction) in Si‐fin a...

Figure 5.2 Two‐dimensional contour (XZ planes) plot of total current density...

Figure 5.3 The 2D and 1D electron concentration profile of the EB–BQP model ...

Figure 5.4 The mobility profile of (a) electron and (b) hole of the BQP mode...

Figure 5.5 Output characteristics (

I

d

 − 

V

d

) comparison for different models ...

Figure 5.6 3D Contour profiles of different electrical parameters: potential...

Figure 5.7 Transfer characteristic curves (

I

d

–

V

g

) of fin width variations ...

Figure 5.8 (a) Cross‐sectional view of three stacked nanosheet transistors. ...

Figure 5.9 (a) A schematic representation of 12 nm long Stacked NSFETs (SNSF...

Figure 5.10 Calibration of transfer characteristics with simulated and repor...

Figure 5.11 Transfer characteristics of the nanosheet under the effects of u...

Figure 5.12 The variation of (a) threshold voltage and subthreshold slope an...

Figure 5.13

I

D

–

V

G

characteristics of stress‐enhanced NSFET devices with a ch...

Figure 5.14 Von Mises stress distribution in vertical RSD the initial struct...

Figure 5.15 Geometry‐dependent stress distributions in faceted RSD stressor....

Figure 5.16 Comparison of

I

d

–

V

d

characteristics for vertical and faceted RSD...

Chapter 6

Figure 6.1 Sketch of (a) NCFETs with spacer (Proposed structure) (b) NCFETs ...

Figure 6.2 The curve of drain current and Log scale vs gate voltage for NCFE...

Figure 6.3 Curve of gate voltage and Transconductance for NCFET (spacer) and...

Figure 6.4 Curve of second order and third order of transconductance vs. gat...

Figure 6.5 The curve between second order and third order voltage intercept ...

Figure 6.6 The IIP3 and 1‐dB compression point for NCFETs (spacer) and NCFET...

Figure 6.7 The IMD3 for NCFETs (spacer) and NCFETs at

V

d

 = 0.50 V are shown ...

Chapter 7

Figure 7.1 Schematic diagram of the conceptual electrical doping process.

Figure 7.2 Working flow chart diagram of Quantumwise ATK‐VNL step‐1 (pre‐sim...

Figure 7.3 Working flow chart diagram of Quantumwise ATK‐VNL step‐2 (simulat...

Figure 7.4 Working flow chart diagram of Quantumwise ATK‐VNL step‐3 (post‐si...

Chapter 8

Figure 8.1 Quantum mechanics vs. classical mechanics.

Figure 8.2 P‐n junction schematics of a conventional diode and a tunnel diod...

Figure 8.3 Transfer characteristics of a conventional diode and a tunnel dio...

Figure 8.4 Schematic and energy band diagram of (a–c) conventional MOSFET an...

Figure 8.5 Energy band diagram of conventional TFET at the interface of the ...

Figure 8.6 Energy band diagram of conventional TFET in the off‐state, on‐sta...

Figure 8.7 Trap‐assisted tunneling via the presence of traps in the forbidde...

Figure 8.8 Pocket doping at the source interface for the TFET device.

Figure 8.9 Square‐shaped TFET with pocket doping.

Figure 8.10 Schematic of a semi‐junctionless TFET, which has an identical do...

Figure 8.11 Extended source TFET in the off‐state and on‐state operations. T...

Figure 8.12 Schematic of a pure boron‐doped TFET with extended epitaxial sou...

Figure 8.13 Schematic of an n‐type junctionless TFET in the equilibrium stat...

Figure 8.14 Schematic of a p‐type electrically doped TFET in the equilibrium...

Figure 8.15 Transfer characteristics of an electrically doped TFET as a func...

Figure 8.16 Electrically induced electron concentration in the source region...

Figure 8.17 Energy band diagram of homojunction and different types of heter...

Figure 8.18 Energy band diagram of homojunction and heterojunction TFET.

Figure 8.19 Schematic of a III–V InN/GaN heterojunction TFET.

Figure 8.20 Schematic of heterojunction III–V TFET.

Figure 8.21 Schematic of a p‐i‐n TFET based on monolayer phosphorene.

Figure 8.22 Heterojunction phosphorene TFET. The tri‐layer has a lower band ...

Figure 8.23 Schematic of a F‐shaped TFET with multiple fingers as the source...

Figure 8.24 Schematic of an L‐shaped TFET.

Figure 8.25 Schematic of a vertical dual‐channel TFET with two sidewall chan...

Figure 8.26 Energy band diagram of vertical dual‐channel TFET in the off‐sta...

Figure 8.27 Transfer characteristics of vertical dual‐channel TFET as the si...

Figure 8.28 Schematic of an n‐type EHBTFET in (a) equilibrium state and (b) ...

Figure 8.29 (a) 3D schematic of a heterojunction nanotube core–shell electri...

Chapter 9

Figure 9.1 Bandgap energy and lattice constant for III‐nitride semiconductor...

Figure 9.2 A GaN tetrahedron in a schematic ball‐and‐stick form with in‐plan...

Figure 9.3 Formation of 2DEG at AlGaN/GaN interface.

Figure 9.4 Diagrammatic representation of homojunction semiconductor LED str...

Figure 9.5 Diagrammatic representation of homojunction semiconductor LED str...

Figure 9.6 Diagrammatic representation of radiative recombination in direct ...

Figure 9.7 Diagrammatic representation of GaN/InGaN...

Figure 9.8 Diagrammatic representation of Micro QW...

Figure 9.9 Diagrammatic representation of the white light generation process...

Figure 9.10 Diagrammatic representation of (a) absorption, (b) spontaneous e...

Figure 9.11 Diagrammatic representation of GaN Blue Laser.

Figure 9.12 Diagrammatic representation of an illustration for white solid‐s...

Figure 9.13 Diagrammatic representation of testing for pH sensitivity of die...

Figure 9.14 Diagrammatic representation of

I

DS

–

V

DS

characteristics by changi...

Figure 9.15 Diagrammatic representation of Sensitivity variation for device ...

Chapter 10

Figure 10.1 Energy band structure and electronic density: (a) pristine graph...

Figure 10.2 Scanning tunneling microscopy of (a) B‐doped bilayer graphene an...

Figure 10.3 Conductance as a function of energy: (a) graphene and (b) (10,0)...

Figure 10.4 Atomic geometries of four kinds of two‐layer systems with (a) ,...

Figure 10.5 Top view of atomic structure of C‐doped rotated two‐layer system...

Figure 10.6 Energy band structures of the ‐stacked graphene/‐BN two‐layer ...

Figure 10.7 Energy band structures near the Fermi level of four‐layer system...

Figure 10.8 Simulated STM images of the ‐stacked two‐layer system to be tak...

Figure 10.9 Contour maps of EI‐LDOS of graphene/C‐doped ‐BN at (a) B site a...

Figure 10.10 Simulated STM images (upper panels) and contour maps (lower pan...

Chapter 11

Figure 11.1 Concept of the completely refurbished ideal 3D transistor.

Figure 11.2 Structure of planar N‐channel MOSFET.

Figure 11.3 Energy band diagram beneath the gate oxide.

Figure 11.4 Description of SS and DIBL in transfer characteristics of MOSFET...

Figure 11.5 Evolution of MOSFET structures. (a) Planar MOSFET. (b) UTB‐SOI M...

Figure 11.6 Structure of GAA nanosheet transistor.

Figure 11.7 TCAD model of nanosheet transistor with three vertically stacked...

Figure 11.8 Results of TCAD simulation setup calibration with experimental d...

Figure 11.9 The symbol for N‐channel MOSFET.

Figure 11.10 Low‐frequency small‐signal model of MOSFET.

Figure 11.11 Measurement of discharge time (

t

d

). (a) Circuit for

t

d

measurem...

Figure 11.12 High‐frequency model of MOSFET.

Chapter 12

Figure 12.1 Drain current vs. inversion coefficient plot with channel length...

Figure 12.2 Drain current vs. inversion coefficient plot with channel length...

Figure 12.3 A typical test setup for determining the technology current .

Figure 12.4 vs. plot of an n‐channel MOSFET with

m

and V.

Figure 12.5 vs. plot of a p‐channel MOSFET with

m

and V.

Figure 12.6 vs. IC plot of an n‐channel MOSFET with

m

and V.

Figure 12.7 vs. IC plot of a p‐channel MOSFET with

m

and V.

Figure 12.8 Variation of drain current in weak inversion region, with respec...

Figure 12.9 Plot of Early voltage of n‐channel MOSFET w.r.t inversion coeffi...

Figure 12.10 Plot of Early voltage of p‐channel MOSFET w.r.t inversion coeff...

Figure 12.11 Flow diagram for transistor sizing using IC method.

Figure 12.12 Common source amplifier. (a) Schematic design of a common sourc...

Figure 12.13 Drain current of common source amplifier in pre‐layout ans post...

Figure 12.14 Output voltage of common source amplifier in pre‐layout and pos...

Figure 12.15 Gain of common source amplifier.

Figure 12.16 Differential‐input single‐ended output operational transconduct...

Figure 12.17 Frequency response of the OTA circuit.

Figure 12.18 PSRR of the OTA circuit.

Figure 12.19 Output offset voltage of the OTA circuit.

Figure 12.20 Input common mode range of the OTA circuit.

Figure 12.21 Common mode gain of the OTA circuit.

Chapter 13

Figure 13.1 Basic diagram of a biosensor.

Figure 13.2 Negative capacitance – junctionless tunnel field‐effect transist...

Figure 13.3 High‐

k

DM‐DGJLT biosensor structure.

Figure 13.4 Dependence of measured normalized (a) SS and (b)

I

ON

dependence ...

Figure 13.5 (a) Graph depicting the variation of SS in JL‐TFET for varying d...

Figure 13.6 Shows the surface potential contour of a biosensor based on dopi...

Figure 13.7 Measured hysteresis properties of fabricated negative capacitanc...

Figure 13.8 2‐D schematic of dopingless dual gate negative capacitance ferro...

Figure 13.9 Two‐dimensional diagram of a dopingless negative capacitance fer...

Figure 13.10 (a) depicts the energy band diagram and (b) depicts the surface...

Chapter 14

Figure 14.1 Application areas of nanoscale devices.

Guide

Cover Page

Table of Contents

Series Page

Title Page

Copyright

About the Editors

List of Contributors

Preface

Acknowledgments

Begin Reading

Index

End User License Agreement

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IEEE Press

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IEEE Press Editorial Board

Sarah Spurgeon, Editor‐in‐Chief

Moeness Amin

Ekram Hossain

Desineni Subbaram Naidu

Jón Atli Benediktsson

Brian Johnson

Tony Q. S. Quek

Adam Drobot

Hai Li

Behzad Razavi

James Duncan

James Lyke

Thomas Robertazzi

Joydeep Mitra

Diomidis Spinellis

Advanced Nanoscale MOSFET Architectures

Current Trends and Future Perspectives

Edited byKalyan BiswasMCKV Institute of EngineeringWest BengalIndia

Angsuman SarkarKalyani Govt. Engineering CollegeWest BengalIndia

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About the Editors

Dr. Kalyan Biswas is an a Assistant Professor in the Department of Electronics and Communication Engineering, MCKV Institute of Engineering, Liluah, Howrah, India. He obtained his B Tech and M Tech degrees from the Department of Applied Physics, University of Calcutta, and received his PhD (Engg.) from Jadavpur University. He is a Senior Member of IEEE since 2013 and is currently serving as the Secretary of IEEE SSCS Kolkata Chapter. He worked in different research and industry positions in Japan and Singapore before joining MCKV Institute of Engineering. Along with his teaching, he is involved in research work in the fields of nanoscale electronic devices, MEMS‐based sensors, fibre Bragg gratings, electronics packaging, etc. He has more than 50 publications in reputed international journals, conferences and has contributed in many book chapters. He has served as an organizing committee member and reviewer for several international conferences. He is also a reviewer for many international journals.

Angsuman Sarkar is Professor of Electronics and Communication Engineering at Kalyani Government Engineering College, West Bengal, India. He received his M Tech degree and his PhD from Jadavpur University. His current research interests span the study of short‐channel effects of sub‐100‐nm MOSFETs and nano‐device modelling. He is a Senior Member of IEEE, Life Member of the Indian Society for Technical Education (ISTE), Associate Life Member of the Institution of Engineers (IE) India, and is currently serving as the Chairman of the IEEE Electron Device Society, Kolkata Chapter. He has authored 6 books, 23 contributed book chapters, 97 journal papers in international refereed journals, and 57 research papers in national and international conferences. He is a member of the board of editors of various journals. He is a reviewer for various international journals. He is currently supervising eight PhD scholars and has already guided seven students successfully as principal supervisor. He has delivered invited talks/tutorial speech/expert talks at various international conferences/technical programs. He has organized IEEE international conferences and several workshops/seminars.

List of Contributors

Zahra Ahangari

Department of Electronic

Yadegar ‐e‐ Imam Khomeini (RAH) Shahre Rey Branch

Islamic Azad University

Tehran

Iran

Ruthramurthy Balachandran

Department of Electronics and Communication Engineering

SOEEC

ASTU

Adama

Ethiopia

Arvind Bisht

Department of Electronics Engineering

National Institute of Technology Uttarakhand

Srinagar Garhwal

Uttarakhand

India

Kalyan Biswas

ECE Department

MCKV Institute of Engineering

Liluah

Howrah

West Bengal

India

Rishu Chaujar

Department of Applied Physics

Delhi Technological University

New Delhi

India

Taraprasanna Dash

Department of ECE

Siksha ‘O’ Anusandhan (Deemed to be University)

Bhubaneswar

India

Debashis De

Department of Computer Science and Engineering

Maulana Abul Kalam Azad University of Technology

Kolkata

India

and

Department of Physics

University of Western Australia

Perth

Western Australia

Australia

Palasri Dhar

Electronics and Communication Engineering Department

Guru Nanak Institute of Technology

Maulana Abul Kalam Azad University of Technology

Kolkata

India

Yoshitaka Fujimoto

Graduate School of Engineering

Kyushu University

Fukuoka

Japan

Jhansirani Jena

Department of ECE

Siksha ‘O’ Anusandhan (Deemed to be University)

Bhubaneswar

India

Annada S. Lenka

Department of Electrical Engineering

Nano‐Electronics Lab

NIT

Rourkela

India

Chinmay K. Maiti

SouraNiloy

Kolkata

India

Bansi Dhar Malhotra

Department of Biotechnology

Delhi Technological University

New Delhi

India

Girish S. Mishra

EECE

School of Technology

GITAM

Bengaluru

India

Nagarajan Mohankumar

Symbiosis Institute of Technology

Nagpur Campus

Symbiosis International (Deemed University)

Pune

India

Eleena Mohapatra

Department of ECE

RV College of Engineering

Visvesvaraya Technological University

Bengaluru

India

Koyel Mukherjee

Centre of Advanced Study

Institute of Radio Physics and Electronics

University of Calcutta

Kolkata

India

Pankaj K. Pal

Department of Electronics Engineering

National Institute of Technology Uttarakhand

Srinagar Garhwal

Uttarakhand

India

Soumya Pandit

Centre of Advanced Study

Institute of Radio Physics and Electronics

University of Calcutta

Kolkata

India

Yash Pathak

Department of Applied Physics

Delhi Technological University

New Delhi

India

Soumik Poddar

Electronics and Communication Engineering Department

Guru Nanak Institute of Technology

Maulana Abul Kalam Azad University of Technology

Kolkata

India

Yogendra P. Pundir

Department of Electronics and Communication Engineering

HNB Garhwal (A Central) University

Srinagar Garhwal

Uttarakhand

India

and

Department of Electronics Engineering

National Institute of Technology Uttarakhand

Srinagar Garhwal

Uttarakhand

India

Debarati D. Roy

Department of Electronics and Communication Engineering

B. P. Poddar Institute of Management and Technology

Kolkata

West Bengal

India

and

Department of Computer Science and Engineering

Maulana Abul Kalam Azad University of Technology

Kolkata

India

Pradipta Roy

Department of Computer Application

Dr. B. C. Roy Academy of Professional Courses

Durgapur

West Bengal

India

Sunipa Roy

Electronics and Communication Engineering Department

Guru Nanak Institute of Technology

Maulana Abul Kalam Azad University of Technology

Kolkata

India

Prasanna K. Sahu

Department of Electrical Engineering

Nano‐Electronics Lab

NIT

Rourkela

India

Angsuman Sarkar

ECE Department

Kalyani Government Engineering College

Kalyani

Nadia

West Bengal

India

Savitesh M. Sharma

Chinmaya Vishwa Vidyapeeth

Ernakulam

Kerala

India

Avtar Singh

Department of Electronics and Communication Engineering

SOEEC

ASTU

Adama

Ethiopia

Asutosh Srivastava

School of Computer & Systems Sciences

Jawaharlal Nehru University

New Delhi

India

Kajal Verma

Department of Applied Physics

Delhi Technological University

New Delhi

India

Preface

The field of metal–oxide–semiconductor field‐effect transistor (MOSFET) devices has observed swift growth in the last decade. In recent years, scientists' views on the use of technology have increased. Nanotechnology is a technology that has the potential to significantly impact almost all areas of human activity, raising great hopes for finding solutions to the major needs of society. The fields of application of research in nanoscience include aerospace, defense, national security, electronics, biology, and medicine. In recent years, human knowledge has made great progress through both theoretical analysis and experimental findings in the area of nanoscience and nanoscale devices.

Nanoelectronic devices are the basis of today's powerful computers and are attracting many new applications, including electronic switching, sensing, and other computational applications. However, our purpose is not to discuss specific tools or applications. Rather, it is to illustrate the concept that has emerged in the last two years to understand the flow of electricity at the atomic scale. This is important not only for the creation of new nanoscale materials but also for the insights it provides into some long‐standing questions in transport and quantum physics.

Reasonable attention has been given to editing this book to promote knowledge exchange and collaboration among different stakeholders in the field of nanoscale materials. Nano‐devices include new and broad fields of activity such as physics, chemistry, biology, and materials engineering focusing on the nanoscale. To understand how these devices work, it is crucial to understand the structure, properties, and quantum behavior of these devices.

Modern life is revolutionized by the advancements of complementary metal–oxide–semiconductor (CMOS) technology. Performance of MOSFET has been improved continuously at a dramatic rate via gate length scaling since its invention. In order to serve the next‐generation high‐performance requirements with lower operating power, remorseless scaling of CMOS technology has now reached the atomic scale dimensions. Conventional MOSFET scaling not only involves the reduction of device size but also requires the reduction in the transistor supply voltage (VDD). With the reduction of VDD, the threshold voltage (Vth) must be scaled down simultaneously in order to attain reasonable ON‐state current, reduce delay, and maintain sufficient gate overdrive voltage. As a consequence of scaling of device following Moore's law, the channel length of the MOSFET is reducing every year, causing short channel effects (SCEs). Different strategies have been considered to surmount SCEs using different device architectures and material compositions.

In this book, the problems associated with the emerging nanoscale MOSFET devices and their trends are highlighted. This book is focused on the evaluation of the present development of nanoscale electronic devices and the future projection of device technologies. Basic device physics and MOSFET operation are presented at the beginning. A widespread discussion on basics of MOSFETs and potential difficulties related to scaling and its remedies is presented. Next, discussion on the impact of high‐k gate dielectrics in next‐generation transistors is included. The effects of trap charges on dielectric defects for multiple gate devices, strain engineering for advanced devices like FinFETs, gate all around nanosheet transistors, etc., have been discussed in different chapters. TCAD analysis is a very important methodology for device performance analysis. TCAD simulation is discussed for negative capacitance field‐effect transistors (FETs) and their linearity performance. Quantum‐mechanical tunnelling effect for electrically doped nano‐devices is also included in the scope of this book. The principles and operations of tunnel FETs, graphene‐based FETs, and related issues are discussed. Applications of GaN devices are considered for optoelectronics applications. Performance analysis of nanosheet transistors and low‐power circuit design using advanced MOSFETs is also discussed. Finally, an FET‐based biosensor with negative capacitance is included.

Readers can feel pleasure in learning about nanoscale devices in real‐world applications. Throughout this book, one can discover the amazing developments of nanoelectronics, its challenges, and its future prospects. We hope that this book will appear as a one volume reference for postgraduate students, prospective researchers, and professionals requiring knowledge for design of integrated circuits using nanoscale devices.

November 4th, 2024

Kalyan Biswas

Angsuman Sarkar

Kolkata, West Bengal, India

Acknowledgments

We would like to take this golden opportunity to express our gratitude to all those who have helped us complete this book. First and foremost, we would like to convey our gratitude to all the contributors to this book for contributing chapters and all the necessary information throughout this project.

We would like to express our gratitude to Prof. (Dr.) Chandan Kumar Sarkar, a retired professor at Jadavpur University, who supported us throughout the entire work. Lots of useful discussions with him and his advice on device physics and device simulations made us stay confident and helped us to finalize this book project.

Special thanks to the management of MCKV Institute of Engineering and Kalyani Government Engineering College for their necessary support.

We would like to thank our family members for always cheering us up and helping us a lot unconditionally in all the ways that they can. Finally, we would like to express our gratitude to our colleagues for their love, encouragement, and generous support all the time.

Kalyan Biswas

Angsuman Sarkar

1Emerging MOSFET Technologies

Kalyan Biswas1 and Angsuman Sarkar2

1ECE Department, MCKV Institute of Engineering, Liluah, Howrah, West Bengal, India

2ECE Department, Kalyani Govt. Engineering College, Kalyani, Nadia, West Bengal, India

1.1 Introduction: Transistor Action

The human life of the modern generation has been revolutionized by the progress of complementary metal–oxide–semiconductor (CMOS) technology. Metal–oxide–semiconductor field‐effect transistor (MOSFET) is one of the most noteworthy inventions of the twentieth century. One important milestone in the progress of semiconductor integrated circuits was the famous – Moore's law [1]. Following Moore's law, the performance of MOSFET has been improved continuously at an intense rate through gate length scaling. To serve the next‐generation high‐performance requirements with lower operating power, unrelenting scaling of CMOS technology has now reached the atomic scale dimensions. The trend will continue with emerging areas of applications such as the internet of things (IoT), e‐mobility, artificial intelligence, and 5G. The cutting‐edge innovation in MOSFET technologies is the most important and at the heart of these emerging technologies. A schematic diagram of the Conventional Bulk MOSFET Structure is shown in Figure 1.1.

Figure 1.1 Schematic diagram of the Conventional Bulk MOSFET Structure.

1.2 MOSFET Scaling

This downscaling of dimensions of the device is critical to integrate the greater number of devices in integrated circuits (ICs). As a consequence of the Moore's law, every year channel length of the MOSFET sinks, causing short channel effect (SCEs). SCEs are affecting power consumption of the circuits [2–9]. The transistor scaling target has been made reachable because of the advanced lithographic capability to make shorter/thinner channels. In the early stage, scaling was possible with conventional structures and material technology, but it is understood that conventional scaling technology cannot continue forever. Therefore, investigation of non‐classical device structures became necessary.

1.3 Challenges in Scaling the MOSFET

Scaling of MOSFETS is not an easy task but faces lots of challenges. Normally, six different short‐channel effects can be distinguished such as “Sub‐Threshold Slope,” DIBL and threshold voltage roll‐off, velocity saturation, hot carrier effects, and direct source to drain tunneling [10–12].

As the SCEs set hurdles to device operation and degrade device performance, these effects should be removed or minimized, so that a device with a shorter physical channel length can preserve the required device characteristics. Researchers tried to overcome these problems by reducing the gate oxide thickness and the depth of source/drain junction while reducing the gate length in conventional bulk MOSFETs. But these scales reached the physical limit of dimension. As a remedy, gate dielectric materials with higher permittivity were used. The use of these high‐k materials as gate oxide allowed for achieving smaller equivalent oxide thickness with a thicker physical dimension. But shrinking of MOSFET to the sub‐10 nm scale is challenging and new technologies were necessary. As per ITRS forecasts and published literature, it is understood that the main research is going on in two different directions: possible modification of the planar architecture and use of non‐planner 3D structure [13–17] to push for its physical limits, or a new way of making transistors, such as devices based on III–V group materials, use of nanomaterials and nanotechnologies like silicon nanowires, carbon nanotubes (CNTs) or graphene, single electron transistors, and also some other emerging devices such as quantum cellular automata and spin‐based electronics.

1.4 Emerging MOSFET Architectures

For decades, traditional scaling techniques based on sinking its physical dimensions have largely dominated the development path of MOSFETs. However, this traditional scaling technique is not valid for emerging nanoscale devices. As device scaling enters beyond the 22 nm node, various significant changes in terms of device architecture and materials in the traditional MOSFET would be required for the competent operation of the device and to extend Moore's law [18–21]. To surmount SCEs, researchers are employing different strategies for nanoscale devices. The main approaches are (i) by employing different structures such as multigate MOSFETs (ii) advanced device physics approaches, such as junctionless MOSFET, tunnel FET (TFET), and (iii) different channel materials having higher carrier mobility such as III–V‐based materials, strained silicon, CNTs, Graphene, etc. for continuing the progress in nanoscale.

1.4.1 Tunnel FET

To reduce power consumption in MOSFETs without degrading device performance, operating voltage (Vdd) and threshold voltage (Vth) of the device need to be scaled down. If Vth is reduced keeping sub threshold swing (SS) of MOSFET unchanged, the power consumption increases. The TFET, which is based on the principle of band‐to‐band quantum tunneling, is one of the most favorable devices, having a steep slope for applications in low‐power circuits. The device structure of a TFET differs from that of the conventional MOSFET as a type of doping in the source region and drain region of TFET are of opposite types. A schematic diagram of single‐gate n‐type TFET is shown in Figure 1.2. A positive voltage in the gate and reverse bias between the source and drain is required to switch the n‐type device ON. It is a semiconductor device based on the band‐to‐band tunneling principle of electrons rather than thermal emission. TFETs operate by tunneling through the S/D barrier rather than diffusion over the barrier [22–31]. The device switches between ON‐state as well as OFF‐state at lower voltages than the Vdd of the MOSFET, making it a suitable choice for low‐power consumption applications in the era of emerging nanoscale devices. This type of device can provide extremely low OFF‐current and steeper sub‐threshold slope than conventional MOSFET. Tunneling occurs for an electron between the valence band of the semiconductor to the conduction band through a potential barrier without having enough energy required for this transition, and this phenomenon can only be explained by quantum mechanical physics. The output characteristics of a TFET are dependent on the parameters such as the doping, the gate work function, etc. Therefore, these parameters can be modified to obtain the desired output characteristics of a TFET. However, from the fabrication point of view, TFET faces a few challenges such as the fabrication of an ultra‐thin body required for robust electrostatics, formation of abrupt junction, III–V/high‐k interface with low trap density, etc.

Figure 1.2 Schematic diagram of tunnel FET.

Two‐dimensional crystal semiconductors are being investigated as the materials of the channels for field effect transistors (FETs). The main advantages of such 2D‐transistors consist of outstanding electrostatic control of the gate terminal because of the considerably higher surface‐to‐volume ratio, pristine surfaces to confirm better interface quality with the insulators, and greater electrical conductivity owing to the ballistic/quasi‐ballistic transport. It also offers tunable electronic properties dependent on the layer and stacking providing further flexibility in transistor design. These distinctive attributes offer the chance to acquaint with 2D materials in the design of TFET, which can concurrently combine the benefits of greater electrostatic integrity and tunneling barrier engineering. As a result, the arena of TFET design based on 2D materials has grown significantly in recent years.

1.4.2 Nanowire FET

In the era of sub‐10‐nm technology nodes, cylindrical‐shaped structures with gates all around were proposed to provide better gate controllability on the channel and reduce “Short Channel Effects” [32–35]. In this structure, a gate is wrapped around the cylindrical‐shaped channel region and termed a silicon nanowire FET (Figure 1.3). Nanowires can be fabricated with single‐crystal structures, controllable doping, and diameters as small as several nanometers. Though the silicon nanowire transistors (SNWT) improves device performance, the fluctuations in process parameters rigorously affect the device characteristics. As per the projection of the International Technology Roadmap for Semiconductor (ITRS), the multiple‐gate SOI MOSFETs will be able to scale up to sub‐10 nm dimensions and are capable candidates for nanoscale devices in the future.

Figure 1.3 Schematic 3D view and a cross‐sectional view of a cylindrical FET.

1.4.3 Nanosheet FET

Nanosheet FETs are considered as a transistors of next‐generation technology, which have been broadly adopted by the industry to carry on logic scaling beyond 5 nm technology nodes, and beyond FinFETs. Scaling of FinFET beyond 7 nm node results worsened SCEs, forced them to move from tri‐date to gate all‐around structures. Among different gate all‐around structures, wider nanosheets provide higher “ON” current and better electrostatic control [36]. FinFETs were the first architectural change of devices in transistor history and gate‐all‐around nanosheet FETs are the milestones in the history of transistor devices as they utilize the complete architectural change. To obtain the full advantages of nanosheet FETs, multiple nanosheets should be stacked on one another. The channel thickness during the stacking is fully dependent on the lithographical limit of the fabrication process. Induction of strain to increase hole mobility has also been adopted recently to improve the device's performance (Figure 1.4).

Figure 1.4 Schematic diagram of a gate‐all‐around nanosheet FET [36]/MDPI/CC by 4.0. Cross section view across a) source‐drain region b) gate region.

1.4.4 Negative Capacitance FET

The negative capacitance field effect transistor (NCFET) has become a good solution for extending Moore's Law due to its process compatibility, high on/off current ratio, and low subthreshold swing. In these devices, a layer of ferroelectric material is sandwiched between the gate oxide and gate metal and utilizes the property of polarization inversion of the ferroelectric material under the influence of gate voltage to provide negative capacitance (Figure 1.5).

Figure 1.5 (a) Schematic diagram of the DFR‐negative capacitance FET, (b) equivalent capacitance model of the device [37]/MDPI/CC by 4.0.

Additionally, the use of ferroelectric layers, for example, NCs in the gate stack, helps to reduce the sub‐threshold slope of the FET to less than the theoretical limit of 60 mV/decade [37]. Various additives such as Al (HAO), Zr (HZO), and Si (HSO) in hafnium‐based ferroelectric materials have also been considered to improve the performance of NCFETs.

1.4.5 Graphene FET

CNTs are planar graphite sheets known as graphene that are wrapped into tube shapes. CNTs have outstanding electrical characteristics and they can be fabricated with very small dimensions, as small as 4–8 Å in diameter. The encouraging electrical properties of a CNT depend on its diameter and the wrapping angle of the graphene. Theory shows that the structure of CNTs may be expressed by a chiral vector linked with two integers (n, m). CNTs can be metallic or semiconducting depending on the difference of values in fundamental tube indices (n, m), and their bandgap is dependent on the diameter. The analysis also indicates that semiconducting CNTs have very high low‐field mobility, large current‐carrying capability, excellent thermal and mechanical stability, and high thermal conductivity [38–40]. Because of their superior material properties, nanotubes are attractive as future interconnects and show enormous advantages as a channel material of high‐performance MOSFETs. Though CNT‐based MOSFETs promise great performance lots of processing issues remain such as fabrication of identical nanotubes, control of abrupt doping profiles, etc. A sketch of the graphene FET is shown in Figure 1.6 [39].

Figure 1.6 A sketch of the graphene FET [39]/MDPI/CC by 4.0.

1.4.6 III–V Material‐based MOSFETS

As the performance improvement of silicon‐based MOSFETs reaches its limit of scaling. Interest has been greatly increased in introducing non‐silicon materials as a channel. III–V‐based MOSFETs are considered one of the most efficient devices for high‐performance digital logic applications. Currently, III–V MOSFETs are expected to allow higher drive currents and greater flexibility than silicon‐based MOSFETs. A wide range of compound semiconductor materials can be obtained using elements from the Periodic Table's columns III and V, like GaAs, InP, and InxGa(1−x)As. The main parameter which defines the important characteristics of these materials is the bandgap energy. The integration of Ge/III–V and Si CMOS platforms is promising in providing low‐power integrated circuits in 10 nm technology nodes and beyond [41]. One of the key challenges of the III–V MOSFET technology is thermodynamically stable, high‐quality gate dielectrics that passivate the interface states.

1.4.7 HEMT

In recent times, high electron mobility transistor (HEMT) accomplished excessive interest due to its superior electron transport. HEMT devices are facing tremendous challenges and replacing traditional field‐effect transistors (FETs) because of their outstanding performance at high frequencies [42]. HEMT technology was first innovated by T. Mimura who was involved in compound semiconductor device development at Fujitsu Laboratories Ltd, Japan [43]. HEMT devices incorporate heterojunctions formed at the junction of two different bandgap materials in which electrons are trapped in quantum wells to avoid scattering by impurities. Thanks to their higher electron mobility and dielectric constant, GaAs having direct bandgap have been used in high‐frequency applications and the field of optoelectronic integrated circuits. AlGaAs having nearly similar lattice constant but larger bandgap in comparison to GaAs, are considered the most suitable contender for barrier material and one of the most prevalent choices to be used in HEMTs [44–46]. However, another excellent material that has been widely studied for HEMT devices in recent years is AlGaN/GaN. AlGaN/GaN HEMTs can operate at very high frequencies with high breakdown strength and high saturation electron velocity. GaN also shows very robust piezoelectric polarization that helps to accumulate huge carriers at the interface of AlGaN/GaN. The performance of the MEMS devices depends on many factors such as a combination of material layers, concentration of doping, and different layer thicknesses, which provide flexibility in the device design process.

1.4.8 Strain Engineered MOSFETs

Strained silicon technology based on the improvement of carrier mobility under the influence of axial strain. Proper use of strain in the silicon channel has emerged as a powerful technique for improved MOSFET performance [47]. Usually, epitaxial layer growth of Si on SiGe allows the formation of strained silicon. Carrier mobility can also be altered by changing content of the “Ge” on “SiGe” layer [48]. The application of strain helps to enhance the ON‐current considerably without altering the transistor design and helps to meet the projected performance improvement. Strain engineering has evolved from the conventional structure of 2D MOSFET to 3D FinFET structure in silicon‐based advanced CMOS technology. Strain engineering is also studied in non‐silicon based functional materials like gallium nitride (GaN) and 2D materials [49]. Tremendous growth with innovative ideas of introducing stress into the device channel is realized with each technology node.

1.5 Organization of this Book

This book is focused on the evaluation of the present development of nanoscale electronic devices and the future projection of device technologies. Basic device physics and MOSFET operation are presented in Chapter 2. In this chapter, a widespread discussion on the basics of MOSFETs and potential difficulties related to scaling and its remedies is presented. Chapter 3 discusses the impact of high‐k gate dielectrics in next‐generation transistors. Chapter 4 deals with the effects of trap charges on dielectric defects for multiple gate devices. Strain engineering for advanced devices like FinFETs, gates all around nanosheet transistors, etc. has been discussed in Chapter 5. TCAD analysis for NCFETs and its linearity performance is presented in Chapter 6. In Chapter 7, quantum‐mechanical tunnelling effect for electrically doped nanodevices is discussed. Chapter 8 elaborates on the principles and operations of TFETs. Applications of GaN devices are provided for optoelectronics in Chapter 9. An illustrative idea of graphene‐based FETs and related issues are presented in Chapter 10. Performance analysis of nanosheet transistors is considered Chapter 11. Low‐power circuit design using advanced MOSFETs is discussed in Chapter 12. Chapter 13 presents FET‐based biosensors with negative capacitance. An overall conclusion is drawn in Chapter 14.

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