Advanced Ultra Low-Power Semiconductor Devices E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 442

Veröffentlichungsjahr: 2023

Beschreibung

ADVANCED ULTRA LOW-POWER SEMICONDUCTOR DEVICES Written and edited by a team of experts in the field, this important new volume broadly covers the design and applications of metal oxide semiconductor field effect transistors. This outstanding new volume offers a comprehensive overview of cutting-edge semiconductor components tailored for ultra-low power applications. These components, pivotal to the foundation of electronic devices, play a central role in shaping the landscape of electronics. With a focus on emerging low-power electronic devices and their application across domains like wireless communication, biosensing, and circuits, this book presents an invaluable resource for understanding this dynamic field. Bringing together experts and researchers from various facets of the VLSI domain, the book addresses the challenges posed by advanced low-power devices. This collaborative effort aims to propel engineering innovations and refine the practical implementation of these technologies. Specific chapters delve into intricate topics such as Tunnel FET, negative capacitance FET device circuits, and advanced FETs tailored for diverse circuit applications. Beyond device-centric discussions, the book delves into the design intricacies of low-power memory systems, the fascinating realm of neuromorphic computing, and the pivotal issue of thermal reliability. Authors provide a robust foundation in device physics and circuitry while also exploring novel materials and architectures like transistors built on pioneering channel/dielectric materials. This exploration is driven by the need to achieve both minimal power consumption and ultra-fast switching speeds, meeting the relentless demands of the semiconductor industry. The book's scope encompasses concepts like MOSFET, FinFET, GAA MOSFET, the 5-nm and 7-nm technology nodes, NCFET, ferroelectric materials, subthreshold swing, high-k materials, as well as advanced and emerging materials pivotal for the semiconductor industry's future.

Leseprobe

Table of Contents

Cover

Table of Contents

Series Page

Title Page

Copyright Page

Preface

1 Subthreshold Transistors: Concept and Technology

1.1 Introduction

1.2 Major Sources of Leakage and Possible Methods of Prevention

1.3 Possibilities and Challenges

1.4 Conclusions

References

2 Introduction to Conventional MOSFET and Advanced Transistor TFET

2.1 Introduction

2.2 Device Structure

2.3 TFET Principle of Operation

2.4 Material Characterization

2.5 Characteristics of TFET

2.6 Comparison of OFF-State Characteristics

2.7 Phonon Scattering’s Impact

2.8 ON-State Performance Comparison

2.9 Performance Analysis Based on Intrinsic Delay

2.10 Bandgap’s Effect on Device Performance

2.11 MOSFET and TFET Scaling Behaviour

2.12 Surface Potential of an N-TFET and N-MOSFET

2.13 Professional Advantages of TFET over MOSFET

2.14 Conclusion

References

3 Operation Principle and Fabrication of TFET

3.1 Introduction

3.2 Planar MOSFET’s Limitations

3.3 Demand for Low Power Operation

3.4 TFET: Operation Principle of TFET

3.5 TFET: Recent Design Issues in TFET

3.6 TFET: Modeling and Application

3.7 TFET: Fabrication Perspective

3.8 TFET: Applications and Future of Low-Power Electronics

3.9 Expected Challenges in Replacing MOSFET with TFET

3.10 Conclusion

References

4 Mathematical Modeling of TFET and Its Future Applications: Ultra Low-Power SRAM Circuit and III-IV TFET

4.1 Introduction

4.2 Modeling Approaches

4.3 Structure

4.4 Applications of Tunnel Field-Effect Transistor

4.5 Road Ahead for Tunnel Field Effect Transistors

References

5 Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency Performance of F-TFET

5.1 Introduction

5.2 Simulated Device Structure and Parameters

5.3 DC Characteristics

5.4 Analysis of Analog/RF FOMs

5.5 Conclusion

References

6 Comparative Study of Gate Engineered TFETs and Optimization of Ferroelectric Heterogate TFET Structure

6.1 Introduction

6.2 Study of Different TFET Structures

6.3 Proposed Structure

6.4 Results and Discussion

6.5 Conclusion

6.6 Future Scope

References

7 State of the Art Tunnel FETs for Low Power Memory Applications

7.1 Static Random Access Memory

7.2 Performance Parameters of SRAM Cell

7.3 TFET-Based SRAM Cell Design

7.4 Conclusion

References

8 Epitaxial Layer-Based Si/SiGe Hetero-Junction Line Tunnel FETs: A Physical Insight

8.1 Fundamental Limitation of CMOS: Tunnel FETs

8.2 Working Principle of Tunnel FET

8.3 Point and Line TFETs: Tunneling Direction

8.4 Perspective of Line TFETs

8.5 Analytical Models of Line TFETs

8.6 Line TFETs for Analog & Digital Circuits Design

8.7 Other Steep Slope Devices

8.8 Conclusion

References

9 Investigation of Thermal Performance on Conventional and Junctionless Nanosheet Field Effect Transistors

9.1 Introduction

9.2 Device Simulation Details

9.3 Results and Discussion

9.4 Conclusion

Acknowledgement

References

10 Introduction to Newly Adopted NCFET and Ferroelectrics for Low-Power Application

10.1 Introduction

10.2 NCFET and Its Design Constraints

10.3 NCFET for Low-Power Applications

10.4 Summary

References

11 Application of Ferroelectrics: Monolithic-3D Inference Engine with IGZO Based Ferroelectric Thin Film Transistor Synapses

11.1 Introduction

11.2 Ferroelectricity in Hafnium Oxide

11.3 IGZO Based Ferroelectric Thin Film Transistor

11.4 Applications in Neural Networks

11.5 Conclusion

References

12 Radiation Effects and Their Impact on SRAM Design: A Comprehensive Survey with Contemporary Challenges

12.1 Introduction

12.2 Literature Survey

12.3 Impact of Radiation Effects on Sram Cells

12.4 Results and Discussion

12.5 Conclusion

Declarations

References

13 Final Summary and Future of Advanced Ultra Low Power Metal Oxide Semiconductor Field Effect Transistors

13.1 Introduction

13.2 Challenges in Future Ultra-Low Power Semiconductors

13.3 Conclusion

References

Index

Also of Interest

End User License Agreement

List of Tables

Chapter 1

Table 1.1 Impact of reverse short channel effect (RSCE) on device and circuit ...

Table 1.2 Parameter comparison between Bulk CMOS and DGSOI at equal supply vol...

Table 1.3 Impact of parameters variation in strong inversion and sub-threshold...

Chapter 3

Table 3.1 Supply voltage scaling trend at various technology nodes [8].

Table 3.2 Displays the noise margin for FinField effect transistors and tunnel...

Chapter 5

Table 5.1 Overview of critical parameters for different doping levels of chann...

Chapter 6

Table 6.1 Comparative results of memory window.

Chapter 7

Table 7.1 Summary of performance parameters of TFET and FinFET based SRAM [25]...

Table 7.2 Benchmarking between SRAM cell implementation using TFET and FinFET ...

Table 7.3 Comparison on SRAM circuits based on GaN TFET, FinFET, and graphene ...

Table 7.4 Comparison on SRAM circuits based on GaN TFET, FinFET [35].

Table 7.5 Comparison of performance parameters of proposed TFET SRAM and other...

Chapter 9

Table 9.1 Design parameters of NSFET.

Chapter 10

Table 10.1 Negative capacitance based different device structures and their pe...

Chapter 11

Table 11.1 Benchmarking table.

Chapter 13

Table 13.1 Overview of disadvantages and advantages of structure engineering....

Table 13.2 Overview of disadvantages and advantages of material engineering.

Guide

Cover

Table of Contents

Series Page

Title Page

Copyright Page

Preface

Begin Reading

Index

Also of Interest

End User License Agreement

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Scrivener Publishing100 Cummings Center, Suite 541JBeverly, MA 01915-6106

Publishers at ScrivenerMartin Scrivener ([email protected])Phillip Carmical ([email protected])

Advanced Ultra Low-Power Semiconductor Devices

Design and Applications

Edited by

Shubham Tayal

Abhishek Kumar Upadhyay

Shiromani Balmukund Rahi

and

Young Suh Song

This edition first published 2023 by John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, USA and Scrivener Publishing LLC, 100 Cummings Center, Suite 541J, Beverly, MA 01915, USA© 2023 Scrivener Publishing LLCFor more information about Scrivener publications please visit www.scrivenerpublishing.com.

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Library of Congress Cataloging-in-Publication Data

ISBN 9781394166411

Front cover images supplied by Pixabay.comCover design by Russell Richardson

Preface

Recently, the advent of portable electronic devices (Apple iPhone, Apple Watch, Galaxy Watch, Galaxy Gear) and social media platforms (TikTok, Instagram, Facebook) has revolutionized the modern information technology (IT) market. Since we are now living in an extremely mobile society, we cannot only make and receive calls anytime but also send and receive photos and videos anytime, no matter where we are. Nowadays, many people are also looking at their phones when they are taking subways, buses, trains, and even airplanes.

For these reasons, there have been steady demands for low-power semiconductor design so that low power consumption can be realized in electronic devices. In particular, the advent of electronic watches, driverless cars (unmanned vehicles), drones, and artificial intelligence (AI) requires further low power consumption, or ‘ultra-low power consumption’, so that people can use portable electronic devices for longer.

In this regard, the design of an ‘ultra-low power semiconductor’ is essential and will be paramount in future semiconductor design. In this book, several state-of-the-art technologies have been carefully selected and introduced, including tunnel field-effect transistors (TFET), fin-shaped field-effect transistors (FinFET), gate-all-around (GAA) MOSFET, nanosheet field-effect transistors (NSFET), static random-access memory (SRAM), and negative capacitance field-effect transistors (NCFET).

This book is a selective collection of recent cutting-edge technologies that have been suggested for future ultra-low power semiconductor design. Several intuitive graphical images and mathematical equations have been carefully presented so that non-IT majors can also easily understand the contents. This book may be used as teaching material for undergraduate (especially for 3rd and 4th year students) and post-graduate course work, as well as for advanced researchers working in several engineering industries.

Shubham Tayal, Shiromani Balmukund Rahi, Abhishek Kumar Upadhyay, and Young Suh Song

1Subthreshold Transistors: Concept and Technology

Ball Mukund Mani Tripathi

Electronics and Communication Engineering, Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, Andhra Pradesh, India

Abstract

The continuous downscaling of Si MOS transistors facilitated technology to follow Moor’s Law which states that transistor density doubles every 18 months. However, the fundamental material limitation of Si, popularly known as Boltzmann’s tyranny, sets a limit on the subthreshold swing up to 60mV/ decade, which means the minimum voltage required for a decade of change in the current is 60 mV. In addition, the various short channel effects, including VT roll-off, increasing IOFF, DIBL, and GIDL, also increase with downscaling. These two effects decrease the ION/IOFF ratio and increase the power dissipation in the transistor, which is very significant, particularly in sub-nanometre technology. So, it is pertinent to think about applications where subthreshold current can be utilized, particularly in ultra-low power and very low-power applications. In the past few years, subthreshold region operation has gained attention and encouraging results have been reported. The presented chapter deals with the scope, challenges, and possible solutions for subthreshold transistors. It also presents developments in the recent past, new devices, structures, and materials with better subthreshold performance, such as high-k transistors, transistors on SOI, thin film transistors, multi-gate transistors, FinFETs, gate-all-around transistors, nanowire, Nano sheet, and TFETs. Recently, NCFET also reported it promises to improve subthreshold performance without changing the conventional structure of the transistor, which is encouraging.

Keywords: Subthreshold transistor, tunnel FET, NC FET, scaling

1.1 Introduction

The market for power-efficient systems, such as personal digital assistants, cellular phones, and other communication devices, has grown significantly due to the fast growth of battery-operated portable applications. To meet the demand, the size of the transistor and supply voltages are scaled down. But, as the size of the transistor is getting smaller at every technology node to increase functionality and high performance, various leakages, such as sub-threshold leakage current increase, gate leakage, and band-to-band tunneling (BTBT) currents through source/drain-substrate junctions are also increasing. These leakages deteriorate device performance and inhibit further downscaling. To overcome these issues, exhaustive research has been carried out in the past that is still going on, such as a reduction in switching frequency and the development of new architectures for pipelining, connections, and logic optimization. Unfortunately, this is not sufficient for future demands for ultra-low power applications below Giga Hertz frequency applications, e.g., instruments used in medical and portable applications. Therefore, various design techniques have been proposed for power-efficient applications and subthreshold transistors are one of them. The subthreshold transistors, as the name suggests, are operated below the threshold voltage or in the subthreshold region [1–4]. The subthreshold current, which is known as the leakage current in conventional terms, can be used for ultra-low power applications. In the subthreshold region, transistors have ideal voltage transfer characteristics, high trans-conductance, and lower gate input capacitance compared to the inversion region and are therefore better for logic circuits. It provides power efficiency at the cost of performance and can be a future choice for ultra-low-power digital and memory applications [5–7]. This chapter is organized as follows. In Section 1.2, the major sources of subthreshold leakage and their possible methods of prevention are analyzed. Various challenging issues confronting the current and future robust subthreshold circuit design are discussed and the scope of subthreshold technology is also presented in Section 1.3. Finally, conclusions are drawn in Section 1.4.

1.2 Major Sources of Leakage and Possible Methods of Prevention

1.2.1 Leakage Mechanisms in MOS Transistors

In Figure 1.1 the various sources of leakage are shown: reverse-bias PN junction leakage (I1); subthreshold leakage (I2); oxide tunneling current (I3); gate current due to hot-carrier injection (I4); GIDL (I5); and channel punch through current (I6). The leakage current components in 2, 5, and 6 are offstate leakage mechanisms, 1 and 3 occur in both ON and OFF states, and 4 occurs in the OFF state.

Figure 1.1 Major components of leakage [8].

1.2.1.1 Current I1

This current is due to leakage through reverse-biased drain/source PN junctions and electron-hole pair generation in the depletion region. Additionally, leakage also occurs through overlapping gates to the drainwell PN junctions or carrier generation in drain-to-well depletion regions. Shallow junctions with high doping are used to overcome this leakage, but it also enhances band-to-band tunneling (BTBT) leakage [9].

1.2.1.1.1 Band-to-Band Tunnelling (BTBT) Current

The electric field increases up to 106 V/cm due to heavily doped shallow junctions, which facilitate quantum mechanical band-to-band tunneling (BTBT) across the reverse-biased PN junction and, therefore, tunneling leakage increases. Considering the step junction, the mathematical expression for tunneling current density is as follows [9]:

where q, h, m*, EG, VRB, E, NA, ND, and Vbi are electronic charge, Planck’s constant, effective mass of electron, energy-band gap, applied reverse bias, electric field at the junction doping on the p side, doping on the n side, permittivity of silicon, and built-in voltage across the junction, respectively. In state-of-the-art technology, smaller node devices are used where abrupt and high doping concentration profiles are used and therefore, BTBT leakage through the drain-well junction is high.

1.2.1.2 Current I2

Above the threshold, voltage channel is said to be fully inverted and its concentration is compared to the bulk concentration, while below the threshold voltage, the channel is not fully inverted, but the channel has some charge and it is weakly inverted. Therefore, the leakage current varies exponentially with gate voltage flows in the device. This current is primarily diffusion current because most of the voltage drop occurs across the drain substrate PN junction, which is inherently reverse-biased. So, the vertical and horizontal fields in the channel do not vary significantly and the drift current is less compared to the diffusion current, unlike in the strong inversion region where the drift current dominates over the diffusion current. The mathematical expression of the subthreshold leakage current is as follows [10]:

where VTH, VT, COX, µ0, ή, TD, CD, and TOX are the threshold voltage, thermal voltage, gate oxide capacitance, zero bias mobility, body effect coefficient, maximum depletion layer width, depletion layer capacitance, and the thickness of the gate oxide. Another important parameter in the sub-threshold region is the subthreshold slope, which indicates the speed of turning off the transistor below the threshold voltage and is given by [10].

The lower the value of SS, the better the device is. At 300 K, its minimum value is 60mV/decade. As suggested by the expression, the lower value can be obtained by reducing temperature T, higher Cox or a thinner oxide layer, and lower Cdm or a thicker depletion layer or lower substrate doping.

1.2.1.2.1 DIBL (Drain-Induced Barrier Lowering)

Ideally, the drain voltage should have a minimum effect on the source-channel barrier or the threshold voltage of the MOSFETs.

In real devices, particularly the short-channel ones, drain voltage affects the channel conduction and the barrier between the source and channel at high drain voltage. This is known as the drain induced barrier-lowering phenomenon and thus, the drain voltage directly affects the threshold voltage along with the gate voltage. The shorter the device, the greater the impact of DIBL. Therefore, this increases the subthreshold leakage and lowers the subthreshold slope significantly as we go to smaller nodes [11]. To reduce DIBL, shallow junctions at the source and drain and higher channel doping are used [11–13].

1.2.1.2.2 Effect of Body Bias

As the expression of threshold voltage indicates, it increases with increasing reverse body bias and therefore, the off current decreases.

where VTH, VFB, NA, Ψ, VBS, and, ή are threshold voltage, flat-band voltage, doping density in the substrate, difference between the Fermi potential and the intrinsic potential in the substrate, and substrate sensitivity. The expression of subthreshold leakage including weak inversion, DIBL, and body effect is as follows [14]:

VTH0 is the zero bias threshold voltage and VT is the thermal voltage. The effect of body bias for small voltage is linear and αVSα is the linearized body effect coefficient. λ is the DIBL coefficient, COX is the gate oxide capacitance, µ0 is the zero-bias mobility, and m is the subthreshold swing coefficient of the transistor. ΔVTH is a term introduced to account for transistor-to-transistor leakage variations.

1.2.1.2.3 Effect of Width Narrowing

The effect of the gate-narrowing effect can be expressed as follows:

where VTH, Cox, VFB, QBK, and Ψs are threshold voltage, capacitance across the oxide, flat band voltage, depletion charge in bulk, and surface potential. The QBK increases due to gate narrowing and therefore, VTH also increases [15]. The narrower the gate width, the higher the QBK and threshold voltage of a transistor and eventually, the subthreshold leakage decreases.

1.2.1.2.4 Channel Length Variation and Vth Roll-Off

The reduction in threshold voltage with a reduction in channel length is termed as Vth roll-off. In long channel devices, the electric field is 1D, but in short, in devices where the distance between the source and drain is comparable to the vertical depletion width, it is 2D.

It is more pronounced in depletion regions near the source and drains and therefore, lesser gate voltage is required for inversion and threshold voltage is reduced (Figure 1.2) [16–18]. The reduced threshold voltage causes more subthreshold current leakage.

1.2.1.2.5 Impact of Temperature Change

The threshold voltage of MOSFET decreases as temperature increases, therefore the subthreshold leakage current and subthreshold slope also increase (Figure 1.3). So, the applications at elevated temperatures cause significant power loss.

Figure 1.2 Threshold voltage variation with channel length and width [8, 15, 17].

Figure 1.3 Temperature effect on current [8, 13].

1.2.1.3 Current I3

Leakage through gate oxide occurs through the tunneling of electrons. The thinner the gate oxide layer the more tunneling there will be due to an increased electric field across the oxide, therefore causing leakage. The tunneling current is proportional to the tunneling probability of electrons. Fowler–Nordheim (FN) tunneling and direct tunneling are the two primary causes of tunneling leakage in MOSFETs. The expression for FN tunneling is [19]:

Figure 1.4 FN tunnelling [8].

where m*, EOX, ǾOX, and VOX are the effective mass of an electron in the conduction band of silicon, the field across the oxide, the barrier height for electrons in the conduction band, and the voltage drop across the oxide.

As the Figure 1.4 shows, the tunneling of electrons occurs through a triangular potential barrier (VOX·> ǾOX) into the conduction band of the oxide layer. (Ignoring the effect of finite temperature and image-force-induced barrier lowering.) FN tunneling is insignificant in short-channel devices.

1.2.1.3.1 Direct Tunnelling

In a thinner oxide layer, the tunneling of electrons occurs through a trapezoidal potential barrier (VOX < ǾOX) directly from the inverted silicon surface to the gate, as shown in Figure 1.5[20]. The direct tunneling current is significant in thin oxide layer MOSFETs and is given as [20]:

Figure 1.5 Direct tunnelling [20].

1.2.1.4 Current I4

The hot electron injection from the substrate to the gate oxide is another leakage due to direct tunneling. In a short-channel transistor, the electric field is high near the Si–SiO2 interface, therefore electrons gain sufficient energy to cross the interface potential barrier and enter the oxide layer. This phenomenon is known as hot-carrier injection [21].

1.2.1.5 Current I5

Gate-Induced Drain Leakage, or GIDL, is another high field effect leakage near the drain in MOSFETs. When the gate is biased in the accumulation region, the hole concentration near the surface increases, causing a narrower depletion layer and an increased local electric field near the surface compared to elsewhere [22]. Now, at high negative gate bias or when the gate is at negative/zero voltage and the drain is at high/supply voltage, the highly n-doped drain region under the gate can be depleted/inverted, causing avalanche multiplication and BTBT due to increased field crowding and peak field [22]. The probability of tunneling through near-surface traps increases too. Due to these effects, minority carriers are emitted in the drain depletion region underneath the gate and are swept laterally to the substrate, forming a path for the GIDL [23, 24]. The increment in the electric field by using thinner oxide or higher potential between the gate and drain enhances GIDL. For very high doped drains, the depletion width and, therefore, the tunneling volume decreases, causing less GIDL. Therefore, a very high and abruptly doped drain is preferred for minimizing GIDL [21–24].

1.2.1.6 Current I6

In state-of-the-art devices, at high reverse biased S/D junctions, the merging of the S/D depletion regions is known as punch through [24]. A drain voltage beyond the value required to establish the punch through lowers the potential barrier for the majority carriers in the source and the sub-threshold current increases (Figure 1.6). It degrades the subthreshold slope too. Punch-through is directly proportional to substrate doping, channel length, and junction width. Therefore, a halo implant at the leading edges of the drain and source junctions is performed to reduce the punch-through effect [24].

1.2.2 Leakage Reduction Techniques

Low-voltage circuits need to be power efficient, so reduction of the leakage power in both the active and standby modes of the operation is essential. It can be achieved using both process and circuit-level techniques. In the former, leakage reduction can be achieved by controlling the dimensions of the device, such as length, oxide thickness, junction depth, etc., and the doping profile, and in the latter, threshold voltage and leakage current are controlled by controlling the voltages of different device terminals such as drain, source, gate, and body.

Figure 1.6 GIDL effect on subthreshold current [24].

1.2.2.1 Leakage Reduction by Channel Processing

For keeping SCE under control, the electric field is kept constant [4]. This can be achieved by scaling down the vertical dimensions of the transistor, such as gate insulator thickness and junction depth, along with the horizontal dimensions, while decreasing the applied voltages proportionally. This ensures the reliability of the scaled device in terms of hot-carrier injection. Besides changing the doping profile in the channel region, using techniques such as retrograde doping or halo implant changes the electric field and potential distributions in the channel and thus are helpful in OFF state leakage [7–10].

1.2.2.1.1 Retrograde Doping

Non-uniform vertical retrograde channel doping is done by creating a low surface channel concentration followed by a highly doped subsurface region. Channel impurity scattering reduces in the low doping region, therefore carrier mobility increases, while the highly doped subsurface region acts as a barrier against punch through [25, 26].

1.2.2.1.2 Halo Doping

Halo doping, non-uniform channel doping in the lateral direction, is an effective way to control the threshold voltage variation with channel length. In this, p-type regions with higher doping are introduced near the source and drain end of the n-channel transistor [27]. The presence of a higher doped p-type substrate near the source/drain reduces the charge-sharing effects from the source and drain fields and therefore reduces the threshold voltage degradation due to channel length reduction. Now, the threshold voltage vs. channel length curve becomes flatter and the off-current becomes less sensitive to channel length variation. The halo implant also reduces DIBL and punch through by reducing the drain and source junction depletion region width. The price paid for this is higher BTBT and GIDL near the high field drain region [25].

1.2.2.2 Leakage Reduction Through Different Circuit Techniques

Transistor stacking, multiple threshold voltage, dynamic threshold voltage, and supply voltage scaling are the major circuit design techniques for leakage reduction in digital circuits.

1.2.2.2.1 Self-Reverse Bias Technique

Subthreshold leakage through a stack of series-connected transistors reduces due to the stacking effect, that is when more than one transistor in the stack is turned off [28–31].

1.2.2.2.2 Multiple Threshold Voltage Designs Technique

In multiple-threshold CMOS technologies, the high- and low-threshold voltage transistors are used to suppress the subthreshold leakage current and achieve high performance, respectively. These can be achieved by non-uniform channel doping [31], variations in gate oxide thickness [32], multiple channel lengths [33], or by using multiple body bias [33]. These techniques are used to design multi-threshold-voltage CMOS (MTCMOS), dual-threshold CMOS, variable threshold CMOS (VTCMOS), and dynamic threshold CMOS, which are used to control leakage and for achieving high performance according to the circuits or applications [34–37].

1.2.2.3 Scaling of Supply Voltage

Supply voltage scaling is an effective way for switching power reduction because of the quadratic dependence of switching power on the supply voltage. It also reduces the decrease in subthreshold leakage due to DIB decreases [38, 39]. There are two ways of lowering the supply voltage: static and dynamic supply scaling. In the former, multiple supply voltages are used. For high-speed requirements, high-supply voltages, and low-speed circuits, low supply voltages are used [40]. In dynamic supply scaling, the highest supply voltage delivers the highest performance at the highest frequency of operation and when the demand is low, the supply voltage and clock frequency are lowered, therefore delivering reduced performance with substantial power reduction [41].

1.3 Possibilities and Challenges

The conventional MOSFETs work as a switch in the saturation (ON state) or strong inversion region and cut-off (OFF state) regions, while subthreshold transistors work in either subthreshold or weak inversion (ON state) and cut-off (OFF state) regions. Due to reduced supply voltage, the power consumption is reduced considerably, resulting in a more power-efficient device for low-power applications. Moreover, the exponential current-voltage relationship and the logic gates made of subthreshold transistors have better voltage transfer characteristics than conventional MOSFETs. In addition, the input capacitance in subthreshold transistors is lower than in conventional MOSFETs and it consumes less power at the same frequency of operation [10]. However, due to the smaller current, it cannot be used at higher frequencies like the conventional MOSFETS. So, possible areas for such transistors are related to ultra-low power and low frequencies or low-speed applications, such as personal digital assistants (PDA), laptops, etc. There are some applications where high-performance periods are low compared to low-performance applications and subthreshold transistors are suitable for such burst-type applications.

Despite several advantages, the market feasibility and acceptability of these transistors must go a long way in comparison to the established conventional MOSFET technology, particularly in device circuits and architecture design. One of the major challenges is to design long-life subthreshold logic gates with a considerable frequency range. The variation in device characteristics due to temperature, voltage, and process, particularly in weak inversion regions, is more due to exponential dependence and therefore, needs to be addressed urgently [42–46]. The pros and cons of device size scaling have been studied exhaustively for conventional MOSFETs, but not for subthreshold transistors. Similarly, the models for such scaling and its impact on threshold voltage and other variations must be studied for making it a potential candidate for ultra-low power applications [47–49]. Semiconductor memories have a large market, particularly for SRAM, which has high density but is very sensitive to process and other variations. This could be even worse for small-sized subthreshold transistors, so efforts must be made. In addition, the smaller ION/IOFF causes difficulties in memory write and read operations.

To check the performance and variations with respect to parameters such as power, delay, etc., of a device, some standard circuits or standards are needed. Unfortunately, there are very few subthreshold operating devices/circuits that have been reported, so some international standards must be defined to compare the performances of the new devices. Similarly, new simulation tools are to be developed for better compatibility with the subthreshold technology.

Often, a system has both high and low-performance devices needing high and low currents, respectively. Since sub-threshold devices are suitable for low-current applications, their integration with high-current devices or switching of the device from strong inversion to weak inversion will be needed according to the requirement. So, very flexible or dynamic voltage scaling is required for combining low and high-performance devices [50, 51].

The CMOS technology is well-optimized for all regions of operations, but sub-threshold transistor technology is not mature enough so devicelevel optimization is necessary. The common methodologies used for device optimization are reducing SCEs, such as DIBL, punch through, and subthreshold slope, halo implant, and retrograde doping in conventional MOS technology. Since the electric field is weaker in subthreshold devices, the impact of SCEs, DIBL, punch-through, halo doping, and retrograde doping may not be essential for device optimization. This reduces fabrication cost and complexity. In addition, the junction capacitance and delay are also reduced. It is reported that the junction capacitance and power delay product become half compared to the standard device after channel doping profile optimization.

Oxide thickness optimization is crucial for conventional as well as sub-threshold transistors for better performance, but they behave differently with respect to oxide thickness variation. In conventional MOSFETs, the gate capacitance is dominated by oxide capacitance in a strong inversion region, so a minimum oxide thickness is required for a better subthreshold slope. In the subthreshold region, the net gate capacitance is comprised of intrinsic depletion, fringe, and overlap capacitances and the variation of these capacitances with respect to oxide thickness is different. For example, the fringe and overlap capacitances vary logarithmically and inversely with respect to oxide thickness. Figure 1.7a shows that the behaviors of subthreshold swing and net gate capacitance are opposite with respect to oxide thickness variations. Similarly, from Figure 1.7b, for a fixed value of current, the requirement of supply voltage decreases with oxide thickness but increases after a minimum point. So, careful oxide thickness optimization is necessary for better capacitance and subthreshold swing [52].

Threshold voltage roll-off phenomenon is significant in short-channel MOSFETs and gets worse when combined with DIBL. To mitigate its effect, a halo implant is done in conventional devices and a reverse short channel effect is observed where threshold voltage decreases as channel length increases, known as a reverse short channel effect (RSCE). RSCE is more effective in subthreshold transistors compared to SCE and allows using longer channel devices with improved drive current without increasing the capacitance. Therefore, RSCE improves performances such as capacitance, drive current, and subthreshold swing of subthreshold transistors, as shown in Table 1.1[12].

The conventional device sizing paradigm is based on the current-voltage relationship in the strong inversion region and, therefore, in logical effort calculations the width ratio of PMOS and NMOS is 2.5 (mobility ratio of electrons and holes) for equal currents. However, the current-voltage relationship in subthreshold transistors is different and a new device sizing paradigm must be adopted. The width ratio of PMOS and NMOS has been found to be 1.5 for equal rise and fall delays at the same supply voltage.

Figure 1.7 (a) Gate capacitance, subthreshold sope; (b) field and supply voltage, variation with oxide thickness [52].

Table 1.1 Impact of reverse short channel effect (RSCE) on device and circuit performance [12].

Parameter

At the device level

At the circuit-level

S (mV/dec)

71 (16 mV1 ss)

—

I

ON

/

I

OFF

2.5X improvement

—

Device capacitance

Low

—

Process variations

—

Reduce

Avg. delay

—

13% improvement

Avg. power

—

31% reduction

Op. frequency

—

100 MHz

PDP (energy)

—

40% reduction

The performance of multiple gate MOSFETs and TFETs [53–65] for subthreshold region operations has been proven to be encouraging [53, 54]. The double gate provides better control over the channel and therefore, on current conduction in inversion, as well as the subthreshold region of operations. This gives better subthreshold slope, lower junction capacitance, resiliency to variations in gate length, oxide thickness, etc. and thus enhances performance for low-power and high-performance circuits with better scalability [53–65]. The salient features of multiple-gate MOS technology are discussed below. Figure 1.8a shows that the delay decreases with gate length, but after a certain point it does not change much with gate length. So, a larger gate length can be used without much compromise in delay for the inverter.

Figure 1.8b shows that in the subthreshold region, the variation of the gate capacitance is negligible (the overlap and fringe capacitance dominate in this region of operation and do not vary much with gate length) for DG n-channel MOSFET. As the intrinsic capacitance is negligible in the sub-threshold region, the total gate capacitance is a combination of overlap and fringe capacitances. Therefore, from Figure 1.8, it can be concluded that a longer device can be used with better ON current, delay, and subthreshold slope without much compromise in the device performance (see Figure 1.8c). In addition, SCEs are less prominent in longer devices [65].

Figure 1.8 (a) Delay vs gate length of an inverter (b) Gate capacitance vs gate voltage of a DG n-channel MOSFET and (c) ON current and subthreshold slope vs gate length [65].

It is reported that properly optimized multi-gate devices can improve the performance of delay, power delay product, gate capacitance, energy consumption, and range of frequency significantly in subthreshold regions. In addition, if a suitable Codesign methodology is developed at the device, circuit, and architecture level for multi-gate devices operating in a sub-threshold regime, the above-mentioned performances can be improved even more [66]. Thus, it shows that properly optimized multi-gate gate devices are more suitable for subthreshold transistors as they have more control over current conduction, lesser gate capacitance, and therefore, better performance.

Device structures and materials, such as DGSOI, carbon nanotube, gate-all-around transistors, SOI-MOSFETs, FinFETs, and stacked transistors, have low power consumption, better performance and scalability, and excellent channel electrostatics and subthreshold swing compared to planar bulk MOSFETs [67]. FinFETs have been used successfully up to a 7-nm node due to their thin body and enhanced gate control on the channel from three sides [68–70]. It is also reported that the multi-fin FinFET structure has better trans-conductance and current drive by increasing the effective channel width by increasing the number of fins [71]. The nanosheet transistors have better gate control compared with FinFETs and therefore, less short channel effects, which are more suitable for logic applications. The single-stack Nanosheet with three vertically stacked channels has larger effective channel width compared to multi-fin FinFET transistors and therefore, better performance for the same footprint dimension [72, 73]. Therefore, if these structures with proper optimization are used for sub-threshold transistors, better performance can be expected. However, very few applications of these structures have been reported for subthreshold transistors [74–78].

Recently, the use of the negative capacitance effect in transistors for increasing the effective gate capacitance and improving gate control over the channel and subthreshold slope without changing the device structure is reported [79–84].

The negative capacitance phenomenon is an old concept but its application in semiconductor devices, particularly in MOSFET and TFET, is new.