Advances in Semiconductor Technologies E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 789

Veröffentlichungsjahr: 2022

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Advances in Semiconductor Technologies Discover the broad sweep of semiconductor technologies in this uniquely curated resource Semiconductor technologies and innovations have been the backbone of numerous different fields: electronics, online commerce, the information and communication industry, and the defense industry. For over fifty years, silicon technology and CMOS scaling have been the central focus and primary driver of innovation in the semiconductor industry. Traditional CMOS scaling has approached some fundamental limits, and as a result, the pace of scientific research and discovery for novel semiconductor technologies is increasing with a focus on novel materials, devices, designs, architectures, and computer paradigms. In particular, new computing paradigms and systems--such as quantum computing, artificial intelligence, and Internet of Things--have the potential to unlock unprecedented power and application space. Advances in Semiconductor Technologies provides a comprehensive overview of selected semiconductor technologies and the most up-to-date research topics, looking in particular at mainstream developments in current industry research and development, from emerging materials and devices, to new computing paradigms and applications. This full-coverage volume gives the reader valuable insights into state-of-the-art advances currently being fabricated, a wide range of novel applications currently under investigation, and a glance into the future with emerging technologies in development. Advances in Semiconductor Technologies readers will also find: * A comprehensive approach that ensures a thorough understanding of state-of-the-art technologies currently being fabricated * Treatments on all aspects of semiconductor technologies, including materials, devices, manufacturing, modeling, design, architecture, and applications * Articles written by an impressive team of international academics and industry insiders that provide unique insights into a wide range of topics Advances in Semiconductor Technologies is a useful, time-saving reference for electrical engineers working in industry and research, who are looking to stay abreast of rapidly advancing developments in semiconductor electronics, as well as academics in the field and government policy advisors.

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Advances in Semiconductor Technologies

Selected Topics Beyond Conventional CMOS

Edited by

An Chen

IBM Research – Almaden, CA, USA

Copyright © 2023 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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Names: Chen, An (Electronics engineer), editor.

Title: Advances in semiconductor technologies : selected topics beyond conventional CMOS / An Chen.

Description: Hoboken, New Jersey : Wiley-IEEE Press, [2023] | Includes bibliographical references and index.

Identifiers: LCCN 2022018684 (print) | LCCN 2022018685 (ebook) | ISBN 9781119869580 (cloth) | ISBN 9781119869597 (adobe pdf) | ISBN 9781119869603 (epub)

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Preface

Since the invention of the solid‐state transistors, the semiconductor technologies have advanced at an exponential pace and become the foundation for numerous industries, e.g. computing, communication, consumer electronics, autonomous systems, and defense. Guided by Moore's law, the scaling of transistors has provided new generations of chips every one to two years, with ever‐increasing density and better performance. Today, silicon transistors are approaching some fundamental limits of dimensional scaling. The semiconductor industry has also transformed through several phases and foundational technologies. The emergence of Internet of Things (IoT), big data, artificial intelligence (AI), and quantum computing has created new opportunities for advanced semiconductor technologies. The complementary metal‐oxide‐semiconductor (CMOS) technology dominates the semiconductor industry today, but there are numerous technologies and active research beyond conventional CMOS. Although semiconductors are often associated with high‐performance computing chips such as central processing unit (CPU) and graphics processing unit (GPU), there is a wide range of applications beyond computing for semiconductor products, e.g. sensors, displays, and power electronics. Silicon (Si) is the most important semiconductor, but the semiconductor research also covers a variety of materials, e.g. germanium (Ge), III–V compounds, organic materials, carbon nanotube, 2D materials, magnetic materials, and topological materials.

This book is a collection of articles reviewing advanced semiconductor technologies beyond conventional Si CMOS for various applications. These articles written by the experts in the fields can be read independent of each other. The variety of topics reflects the breadth of the semiconductor R&D and applications today, but these articles only cover a very small fraction of semiconductor technologies.

With the transistor scaling approaching the fundamental limits, heterogeneous integration is a promising direction to sustain the improvement of performance and functionalities without relying on reducing transistor sizes. Chapter 1, “Heterogeneous Integration at Scale,” provides a comprehensive review of technologies, design/architecture considerations, reliability issues, applications, and future directions of large‐scale heterogeneous integration.

While technology innovation has been a primary driver for the semiconductor industry, the future of semiconductor systems will increasingly resort to novel computing paradigms. Chapter 2, “Hyperdimensional Computing: An Algebra for Computing with Vectors,” presents an example of entirely new ways of computing inspired by the information processing in the brain. Instead of traditional model of computing with numbers, hyperdimensional (HD) computing encodes information in a holographic representation with wide vectors and unique operations. HD computing is extremely robust against noise, matches well with 3D circuits, and is uniquely suitable to process a variety of sensory signals without interference with each other.

The majority of semiconductor chips are digital circuits; however, analog and mixed‐signal circuits are crucially important. The physical world is analog; therefore, analog circuits are always needed to connect digital chips with real world, e.g. sensory data, power management, and communication. Although digital circuit design is highly automated, analog circuit design still relies on manual effort. Chapter 3, “CAD for Analog/Mixed‐Signal Integrated Circuits,” reviews the progress toward automated computer‐aided design (CAD) of analog and mixed‐signal circuits.

Modern computers are built based on the von Neumann architecture with separate logic/computing units and memory/storage units. Emerging memory devices not only provide new technologies to improve memory systems but also enable novel computing architectures, e.g. in‐memory computing. One of the most promising emerging memories is based on magnetic materials and properties. Chapters 4 and 5 focus on a so‐called magnetoelectric field effect transistor (MEFET) based on the programming of the polarization in a 2D semiconductor channel with large spin‐orbit coupling, via the proximity effect of a magnetoelectric gate. Chapter 4, “Magnetoelectric Transistor Devices and Circuits with Steering Logic,” presents various logic gate designs based on a one‐source two‐drain MEFET configured with a steering function. Chapter 5, “Nonvolatile Memory Based Architectures Using Magnetoelectric FETs,” describes MEFET memory designs with the performance and size suitable to fulfill the application space between static random‐access‐memory (SRAM) and dynamic random‐access‐memory (DRAM).

Novel materials beyond Si, Ge, and III–V compounds may enable new semiconductor products and applications. Among them, organic semiconductors are promising materials for low‐cost, flexible, and bio‐compatible electronics. Chapter 6, “Organic Electronics,” discusses the opportunities of organic semiconductors for large‐area flexible electronics, including organic light‐emitting diode (OLED), organic displays, organic solar cells, and thin‐film transistors. Chapter 7, “Active‐Matrix Electroluminescent Displays,” delves into the details of flat panel electroluminescent displays based on light‐emitting diodes (LEDs) that have been utilized in a wide range of applications including smart phones, tablets, laptops, and TVs. Various underlying LED technologies, associated circuits, and design considerations are reviewed. Another interesting application of organic materials is memory. Chapter 8, “Organic and Macromolecular Memory – Nanocomposite Bistable Memory Devices,” discusses the mechanisms, characteristics, and current status of organic memories. One of the advantages of organic materials is their low‐cost processing and the potential to stack up multiple layers. Chapter 9, “Next Generation of High‐Performance Printed Flexible Electronics,” summarizes different printing technologies for flexible electronics, showcases the state‐of‐the‐art printed flexible electronic circuits, and discusses the challenges and future directions of large‐scale cost‐effective printed electronics. The vision of integrating electronic components onto polymer foils leads to the flexible electronics version of systems‐on‐chip (SoC), known as systems‐in‐foil (SiF). A wide range of applications can benefit from SiF, e.g. smart labels, intelligent electronic skin, and implanted devices. Chapter 10 “Hybrid Systems‐in‐Foil” reviews the opportunities of SiF and challenges in materials, integration, and testing.

The electronic systems need an interface with the physical world. Semiconductor chips rely on sensors to “see,” “hear,” and “smell.” Optical sensing is utilized in a wide range of applications, e.g. camera, fiber optics and communication, light source and laser, data storage, medical monitoring and diagnostics, and manufacturing. Chapter 11, “Optical Detectors,” reviews the photodiodes based on Si, III–V, and emerging materials as the essential components for highly sensitive detectors for a broad spectrum of wavelengths. Chapter 12, “Environmental Sensing,” covers comprehensively different air pollution sources, air quality metrics, and various sensing approaches for particulate matters and volatile organic compounds. The advancement of semiconductor technologies contributes to the miniaturization of the sensing equipment and the improvement of their performance.

Unlike computer chips operating with very low voltage and current, power electronics handle very high voltage (e.g. thousands of volt or higher) and current required to operate machinery, vehicles, appliances, etc. Special device designs and unique material properties are required to sustain such high voltage and current in semiconductor chips. Chapter 13, “Insulated Gate Bipolar Transistors (IGBTs),” reviews an important high‐power device known as Si insulated gate bipolar transistors (IGBTs). IGBT not only dominates power electronics today but also continues to be innovated for further gains in power density and efficiency. At the same time, significant progress has been made on wide bandgap semiconductors. Chapter 14, “III–V and Wide Bandgap,” reviews promising materials (e.g. diamond, GaN) and their applications in high‐frequency power conversion and high‐temperature electronics. While wide bandgap power modules may be combined with Si‐based control circuits in near‐term solutions, considerable effort is made to advance integrated circuits based on wide bandgap semiconductors. Chapter 15, “SiC MOSFETs,” reviews SiC‐based power semiconductor devices including diodes and transistors. SiC is well positioned to fulfill the requirements of power electronics, e.g. energy efficiency, scaling, system integration, and reliability. The unique ability of SiC to form a native SiO2 as the gate dielectric makes it particularly attractive for power metal‐oxide‐semiconductor field‐effect‐transistors (MOSFETs). At the end, Chapter 16, “Multiphase VRM and Power Stage Evolution,” provides a detailed overview of the evolution of CPU power delivery technologies and explains the reasons driving the technology shifts.

This book could be considered as a small‐scale reference of advanced semiconductor technologies, which may potentially be expanded into a large‐scale reference with more comprehensive coverage. It is our wish that this collection of chapters will provide useful tutorials on selected topics of advanced semiconductor technologies.

An Chen

IBM Research – Almaden, CA, USA

September 2022

List of Contributors

Mohamed B. Alawieh

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Mohammed Alomari

Institut für Mikroelektronik Stuttgart

Stuttgart

Germany

Shaahin Angizi

Department of Electrical and Computer Engineering

New Jersey Institute of Technology

Newark, NJ

USA

Ahmet F. Budak

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Hao Chen

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Danny Clavette

Infineon Technologies Americas Corporation

El Segundo, CA

USA

Abhishek S. Dahiya

University of Glasgow

James Watt School of Engineering, Bendable Electronics and Sensing Technologies (BEST) Group

Glasgow

UK

Ravinder Dahiya

University of Glasgow

James Watt School of Engineering, Bendable Electronics and Sensing Technologies (BEST) Group

Glasgow

UK

Li'ang Deng

Department of Electronic Engineering

Shanghai Jiao Tong University

China

Peter A. Dowben

Department of Physics and Astronomy

Jorgensen Hall, University of Nebraska

Lincoln, NE

USA

Mourad Elsobky

Institut für Mikroelektronik Stuttgart, Sensor Systems

Stuttgart

Germany

Peter Friedrichs

IFAG IPC T, Infineon Technologies AG

Neubiberg

Germany

Xiaojun Guo

Department of Electronic Engineering

Shanghai Jiao Tong University

China

Subramanian S. Iyer

Electrical Engineering Department

University of California

Los Angeles, CA

USA

Pentti Kanerva

University of California at Berkeley

Redwood Center for Theoretical Neuroscience

Berkeley, CA

USA

Hagen Klauk

Max Planck Institute for Solid State Research

Stuttgart

Germany

Tihomir Knežević

Faculty of Electrical Engineering Mathematics & Computer Science

MESA+ Institute of Technology

University of Twente

Enschede

The Netherlands

Yogeenth Kumaresan

University of Glasgow

James Watt School of Engineering, Bendable Electronics and Sensing Technologies (BEST) Group

Glasgow, UK

Thomas Laska

Infineon Technologies AG

Germany

Mingjie Liu

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Andrew Marshall

Department of Electrical Engineering, The Erik Johnson School of Engineering and Computer Science

University of Texas at Dallas

Richardson, TX

USA

Lis Nanver

Faculty of Electrical Engineering Mathematics & Computer Science

MESA+ Institute of Technology

University of Twente

Enschede

The Netherlands

Arokia Nathan

Darwin College

University of Cambridge

Cambridge

UK

David Z. Pan

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Shashi Paul

Emerging Technologies Research Centre

De Montfort University

Leicester

UK

Wei Shi

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Xiyuan Tang

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Boris Vaisband

McGill University

Electrical and Computer Engineering Department

Montreal, QC

Canada

Tarek Zaki

Munich, Germany

Shuhan Zhang

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Keren Zhu

Department of Electrical and Computer Engineering

The University of Texas at Austin

Austin, TX

USA

Deliang Fan

Department of Electrical, Computer and Energy Engineering

Arizona State University

Tempe, AZ

USA

1Heterogeneous Integration at Scale

Subramanian S. Iyer1 and Boris Vaisband2

1Electrical Engineering Department, University of California, Los Angeles, CA, USA

2McGill University, Electrical and Computer Engineering Department, Montreal, QC, Canada

1.1 Introduction

Microelectronics has made tremendous progress over the last several decades adhering to what is popularly called Moore's Law. One measure of Moore's law is the scaling factor of minimum features on a silicon integrated circuit (IC). This trend is shown in the dark gray (left‐hand y‐axis) curve in Figure 1.1 [1] exhibiting over a 1,000‐fold decrease in minimum feature size, corresponding to a million‐fold transistor density improvement. This improvement corresponds to reduction in power per function as well as reduction of cost and price per function. Nonetheless, until recently, packaging did not scale as seen in the light gray (right‐hand y‐axis) curve in Figure 1.1. For example, in 1967, when flip‐chip bonding was first introduced, the bump pitch was 400 µm. Even today, the pitch of the bump (die to laminate) has scaled to about 130 µm, while ball grid array (BGA) pitch and trace pitch on laminates and printed circuit boards (PCBs) have not fared better. However, in the last few years, we have seen an acceleration of these metrics as shown in the inset in Figure 1.1. Note that the silicon (Si) scale is in nanometers, while the packaging scale is in micrometers. There are two key factors that have mediated this acceleration: (i) the adoption of silicon‐like processing materials and methods to achieve scaling, including silicon interposers, and, importantly, (ii) fan‐out wafer‐level packaging (FOWLP).

This trend has manifested itself in two ways: (i) The extensive use of interposers, which is an additional level in the packaging hierarchy as shown in Figure 1.2. At a basic level, interposers provide a first‐level platform for the integration of several (eight) heterogeneous dielets on a thinned silicon substrate that is then further packaged on a laminate and attached to a PCB. This allows the dielets on the interposer to communicate intimately within the interposer, though communication outside the interposer is more conventional. (ii) Three‐dimensional (3D) integration, where dies are stacked one on top of the other, typically face to back with through silicon vias (TSVs) or alternatively face to face through surface connections. These face‐to‐face connections can be at high bandwidth and low latency. Both of these techniques have transformed packaging, especially when it comes to the memory subsystem. A roadmap using the memory subsystem as a paradigm for advanced packaging is depicted in Figure 1.3. Another area in which interposers and 3D integration can play a big role is the integration of analog and mixed signal functions. Moore's law scaling does a good job in scaling digital logic, but is at best marginal when it comes to analog and mixed signal functions. This is shown in Figure 1.4, where the analog/mixed signal components can occupy an increasing percentage of real estate at finer geometries. In these cases, retaining the analog/mixed signal functions in an older node makes sense as long as one can provide compatible voltage domains and ensure low latency as well as low analog signal distortion. These are not very difficult to do on interposers.

Figure 1.1 Scaling trends for CMOS features as well as package features. Package scaling has lagged significantly as compared to Si scaling. Adoption of silicon‐like technology for packaging has somewhat accelerated scaling.

Figure 1.2 Current packaging hierarchy. Left: die‐laminate‐PCB. Right: die‐interposer‐laminate‐PCB.

Why is it important to scale packaging? Packaging dimensions determine the size of the system especially since the scale is 10–100 times larger than chip dimensions. Power too is a major consideration. Communication power between chips accounts for 30–40% of total system power. So for size, weight, and power (SWaP), as well as cost, scaling the package has advantages. The key parameters that affect SWaP are dominated by packaging metrics, and scaling the package has greater impact on SWaP than additional Si scaling. For flexible hybrid electronics (FHE), form factor and power play a critical role. Most FHE devices are mobile and dependent on battery power. As such, FHE packages will benefit immensely from scaling.

Figure 1.3 Packaging evolution – the memory paradigm.

Figure 1.4 Percent of area dedicated to analog circuits is increasing with scaling (squares). Thus, practical die area (normalized to 180 nm technology) is increasing with scaling (rhombuses) as compared to ideal die area (triangles).

Another aspect of advanced packaging that has the focus of attention in recent years is heterogeneous integration. This term requires some clarification. Most packaging constructs do in fact achieve heterogeneous integration via the integration of diverse packaged chips on an extended substrate such as a PCB. Heterogeneous integration, therefore, in general and in itself, is not new. However, in the context of advanced packaging, heterogeneous integration refers to the integration of bare dies on a first‐level packaging substrate. This could be an organic, ceramic, or silicon interposer. The key features that distinguish heterogeneous integration from classical or conventional packaging are the pitch of the connections between the bare die and the substrate, the number of connections between the interconnected bare dies, the size of the dies, and hence a significant simplification in the communication protocols of interdie signaling. It is generally accepted that for bump pitches <50 µm, interdie spacing of <2 mm, and trace pitches (wiring between the dies) of <5 µm, the integration is considered in the regime of advanced packaging.

Finally, “chiplets” and “dielets” are another feature of advanced packaging. A complex system or large chip design is fragmented into smaller entities called chiplets and then instantiated in Si as dielets. These dielets are then intimately reintegrated at fine pitch (bump and trace) as well as short interdie spacing, as previously described, to synthesize a subsystem or a module. This construct can be further assembled on a PCB or, in the case of wafer scale systems, and can represent the entire system [2, 3].

1.2 Technology Aspects of Heterogeneous Integration

Technology innovation is the main driver of the various heterogeneous integration platforms. In the past several decades, packaging technology (e.g. vertical interconnect pitch) has been scaling at a significantly slower rate as compared to IC technology (e.g. device dimensions), as shown in Figure 1.1. Specifically, on‐chip dimensions have scaled approximately 200 times more than package features. This disparity in scaling of parts of a single system led the package hierarchy to become the bottleneck of modern integrated systems.

Nonetheless, in the last five years, the electronic packaging community has picked up the pace proposing various novel integration technologies to reduce the dimensions of the packaging hierarchy. Specifically, novel heterogeneous integration platforms have been proposed, significantly driving down the features of the packaging hierarchy. Realization of the heterogeneous integration concept is predicated on several important technology considerations. A review of the vertical interconnect pitch (between dielets and substrate), substrate material, interdielet spacing, and dielet termination is provided in this section.

1.2.1 Interconnect Pitch

Typical package‐level interconnect pitch is several hundreds of micrometers. These are solder‐based BGA or land grid array (LGA) connections between the package and the PCB. Connections between dies and package laminate, i.e. solder‐based C4/pillar, exhibit a smaller pitch (50 to 100 µm). Nonetheless, comparing to the last metal levels on the die (pitch of 2–10 µm), the package‐level interconnects are approximately between 10 and 500 times larger. In fact, the main purpose of the packaging hierarchy is to fan‐out the interconnect pitch from the small die‐level pitch, to the large PCB‐level pitch, and then vice versa when connecting to the neighboring packaged die. Solder has the advantage of deforming at low temperature and pressure, to accommodate warpage of the PCB, laminate, and die. A typical Cu pillar capped with solder is shown in Figure 1.5a, a cross section after mass reflow is shown in Figure 1.5b, and a micrograph of two shorted pillars is shown in Figure 1.5c. Shorting of neighboring solder balls is the main challenge to the continuous scaling of solder‐based interconnects below about 50 µm.

Figure 1.5 (a) A 50 mm diameter Cu pillar capped with solder. (b) After mass reflow with compression showing the solder extrusions. (c) Micrograph showing extrusions that cause adjacent pillars to become electrically shorted.

Source: Photo courtesy: Eric Perfecto.

Another possible integration approach is to attach dielets directly to a substrate without solder (or other intermetallics), using direct metal‐to‐metal thermal compression bonding (TCB). In this integration approach, two metals are bonded together by applying pressure and temperature for a certain amount of time. After this process, a very strong low‐contact resistance bond is formed. To ensure high‐quality connections using TCB, the surfaces of the metals must be pristine and atomically smooth. Additional conditions must be met when bonding Cu for example, such as surface preparation to avoid oxidation of the Cu prior to bonding (by using plasma or formic acid).

Alignment is another challenge in small pitch connections for heterogeneous integration. Solder‐based interconnects are easier to align due to the larger dimensions and since they exhibit a form of self‐alignment property due to surface tension at solder melting temperature. Unlike solder, direct metal‐to‐metal integration requires a high level of alignment accuracy which is difficult to achieve by optical means since the die and substrate are typically not transparent. A second‐order optical alignment is therefore required, where the die and the substrate are aligned to a virtual reference. For example, in the silicon interconnect fabric (Si‐IF) technology, an alignment accuracy of 1 µm has been achieved [4]. Although this alignment accuracy is good, it is still about an order of magnitude worse than die‐level conventional optical lithography.

1.2.2 Substrate Material

Different substrate materials are currently used in heterogeneous integration. The most commonly used materials are compared in Table 1.1.

Hybrid substrate materials are also used in industry. For example, the embedded multidie interconnect bridge (EMIB) [5] approach supports the integration of small Si bridges within an organic substrate. The EMIB enables different interconnect pitches, coarse pitch on the organic FR4 and fine pitch on the Si bridge. This technology, however, exhibits increased complexity and therefore higher cost.

Table 1.1 Key structural and thermal properties of Si and other relevant materials.

Material

Young's modulus (GPa)

Tensile strength (MPa)

CTE (ppm)

Thermal conductivity (W/m K)

Warpage

Cost

Notes

Organic (FR4)

0.1–20

2,000–3,000

14–70

0.3–1

High

Low

Large horizontal and vertical interconnect pitch

Glass

50–90

33–3,500

4–9

1–2

Low

High

Low electrical losses. Metallization is difficult

Silicon

130–185

5,000–9,000

3–5

148

Low

Low

High electrical losses

Steel

190–200

400–500

11–13

16–25

Copper

128

200–350

17

400

The Si‐IF [2] is a silicon wafer‐scale platform that supports integration of small dies at fine vertical pitch (2–10 µm). Si is a highly mature substrate that benefits from decades of technology optimization. Furthermore, passive Si with micrometer size interconnects is a relatively inexpensive construct.

1.2.3 Inter‐Die Spacing

In conventional packaging, dies are packaged and placed on PCBs. Interposers, an additional hierarchical layer, is often utilized in modern systems as a stepping stone to close integration of heterogeneous components. However, interposers are expensive and limited to only several components. In any of the abovementioned integration approaches, the inter‐die spacing is large. In interposers the spacing is a few hundreds of micrometers, whereas the spacing between two packaged dies on a PCB reaches tens of millimeters. The large inter‐die spacing significantly increases the latency and power of communication. In standard von Neumann architectures, where processor‐memory communication is a key bottleneck, the excessive performance degradation of communication is especially limiting.

In the Si‐IF technology, dies are integrated at high proximity (50 µm). This is enabled since the dies are not packaged. The only limitations on interdielet spacing in the Si‐IF platform are the roughness of the edge of the die (due to wafer dicing), and edge seals and crack stops that are typically present at the edge of the die, effectively increasing the interdie spacing. Novel technologies, such as plasma dicing [6], will enable further reduction of the interdie spacing on the Si‐IF.

1.2.4 Die Size Considerations

Modern systems‐on‐chips (SoCs) are typically very large in area (excluding mobile SoCs). For example, AMD's Rome server SoC includes up to 1,000 of cumulative silicon area [7]. The reason for such a large area is the attempt to integrate as many components as possible at the IC level to leverage the small interconnect dimensions and intercomponent spacing. Large SoCs integrated on interposers, are, however, prone to yield degradation and are typically expensive to fabricate. The concept of heterogeneous integration aims to solve this problem by enabling platforms that support IC‐level interconnect dimensions at the package level and eliminate the need for complex and expensive integration hierarchy, (e.g. the use of interposers).

Figure 1.6 Parametric space to determine optimal die size for heterogeneous integration. The key plotted parameters are: intellectual property (IP) reuse, die handling, yield, I/O complexity/power, and testing complexity. Those parameters are plotted as a function of the die size. An optimal parametric space in the center of the figure drives the optimal die size to be 1–100 .

Since integration at fine pitch and small inter‐component spacing is enabled at the package level by various heterogeneous integration platforms, the components (or dies) need not be very large. Several parameters are key to determine the optimal die size for integration, as shown in Figure 1.6. The optimal die size is represented by the light gray block in the center of Figure 1.6, driven by the optimal parametric space. Following is a discussion of the parameters that determine the die size for heterogeneous integration.

IP reuse

: Enables reduced

nonrecurring engineering

(

NRE

) cost and faster time to market. Ability to reuse IP significantly increases with smaller die size. The smaller the die, the simpler and potentially more fundamental the function, the higher probability to reuse the die. For example, at the leftmost side of the bar in

Figure 1.6

, a simple logic block (e.g. multiplexer), has a high probability to be reused many times in a other projects or systems. Alternatively, a very large system (e.g. an entire SoC), will not likely to be reused in other projects or systems. Therefore, according to the IP reuse parameter, the smaller the die, the better.

Handling

: This parameter prefers large dies since handling very small dielets (smaller than 1

) is difficult. Special tools, alignment techniques, and handling procedures are required to handle such small dies. On the other hand, handling large dies is easy and established tooling can be used.

Yield

: A key parameter and potentially the main driver of any fabrication facility. Statistically, large dies are prone to high probability of defects leading to low yield and therefore high cost. Alternatively, small dies typically exhibit a very high yield in an established process, driving down the cost of the dies and the entire system. Small dies are therefore preferred to optimize the yield parameter.

I/O complexity/power

: Rent's rule drives this parameter, i.e. the number of I/Os is related to the complexity of the component (further described in

Section 1.2.5

). Small components (or dies) require fewer I/Os and therefore less I/O‐related power. Integration of small dies supports local highly parallel communication, as compared to large dies that required high‐speed

serializer/deserializer

(

SerDes

) communication, which is both power and area‐hungry. Smaller are therefore preferred to satisfy this parameter.

Testing complexity

: This is a unique parameter that is prohibitive for both very small and very large dies. Small dies, although exhibit low complexity and require simpler testing approach, are difficult to probe and expensive. Alternatively, large dies are highly complex requiring sophisticated testing approaches and significantly limit testing at speed.

1.2.5 Dielet to Substrate Pitch Considerations

Rent's rule [8] determines a relation between the number of I/Os of a chip and the complexity of that chip. Specifically, the number of signal terminals T is related to the number of internal chip components, g (e.g. gates, blocks)

(1.1)

where t and p are constants that represent the technology and circuit complexity. Typical values of p are 0 < p < 1 and approach unity for low‐complexity dies. In microprocessors, for example the values of t and p are, respectively, 0.8 and 0.45 [9]. Current system integration technologies do not support the number of I/O terminals that are required according to Rent's rule. Power‐hungry SerDes circuitry is used to “bypass” Rent's rule. In [2], the following expression is derived for the pitch of the I/Os between the die and substrate

(1.2)

where A is the area of the die, and is the area per transistor (for the specific technology).

From (1.2) and assuming SerDes circuitry is to be eliminated, an I/O pitch of 3 to 7 µm will be required for SoCs (in technologies of 45 nm and smaller). Note that this pitch is similar to the fat wire pitches of ICs. Advanced heterogeneous integration platforms will, therefore, have to support a similar range of vertical interconnect pitch between the dies and substrates. The Si‐IF platform, for example borrows heavily from standard Si fabrication techniques and supports a fine integration pitch of 2–10 µm. Heterogeneous integration platforms that utilize solder‐based vertical interconnects will not be able to reduce the pitch to the required range, as previously discussed. The notion of the fine pitch and small interdie spacing, positions the Si‐IF as a natural platform to realize an SoC‐like system‐on‐wafer (SoW).

In addition to the power savings due to the elimination of SerDes, the fine I/O pitch on the Si‐IF supports a significant increase in the number of I/Os. The data rate of each I/O can, therefore, be lower as compared to the data rate per I/O in current packaging technologies. The aggregate bandwidth of the IBM POWER9 chip, for example is 1,206 GB/s [10] with 2,359 C4 pads dedicated to differential signaling [11], resulting in a data rate per pad of 8.2 Gb/s. Whereas, if integrated using a fine pitch of 3.5 µm [2