Analog Devices and Circuits 2 E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 221

Veröffentlichungsjahr: 2024

Beschreibung

At the end of the Second World War, a new technological trend was born: integrated electronics. This trend relied on the enormous rise of integrable electronic devices. Analog Devices and Circuits is composed of two volumes: the first deals with analog components, and the second with associated analog circuits. The goal here is not to create an overly comprehensive analysis, but rather to break it down into smaller sections, thus highlighting the complexity and breadth of the field. This first volume, after a brief history, describes the two main devices, namely bipolar transistors and MOS, with particular importance given to the modeling aspect. In doing so, we deal with new devices dedicated to radio frequency, which touches on nanoelectronics. We will also address some of the notions related to quantum mechanics. Finally, Monte Carlo methods, by essence statistics, will be introduced, which have become more and more important since the middle of the twentieth century. The second volume deals with the circuits that "use" the analog components that were introduced in Volume 1. Here, a particular emphasis is placed on the main circuit: the operational amplifier.

Leseprobe

Table of Contents

Cover

Table of Contents

Title Page

Copyright Page

Preface

1 On Analog Circuits

1.1. Introduction: miscellaneous

1.2. A simple but realistic amplifier circuit: the bipolar junction transistor with a common emitter

1.3. Integrated circuit design

1.4. Current sources

1.5. A historic circuit: the 741 operational amplifier

1.6. Electric simulator

1.7. Simulation of a system with several active devices

1.8. Basic analog functional blocks in (C)MOS technology

1.9. Conclusion

2 Noise and Interference in Mixed Circuits

2.1. Introduction

2.2. Ground or power supply noise and substrate coupling

2.3. Noise in integrated oscillator circuits

2.4. Sensitivity functions

2.5. New developments in impulse sensitivity function

3 From 2D to 3D: Opportunities and Challenges

3.1. Introduction

3.2. 3D integration

3.3. Conclusion

References

Index

Other titles from ISTE in Electronics Engineering

End User License Agreement

List of Tables

Chapter 1

Table 1.1. Differentially mounted coupled emitters: SPICE program

Chapter 3

Table 3.1. Electrical parameters for various materials involved.

List of Illustrations

Chapter 1

Figure 1.1. A folded resistor

Figure 1.2. Chronogram of the circuit

Figure 1.3. Bipolar junction transistor, NPN, with common emitter, with emitte...

Figure 1.4. Small signal diagram of the common emitter.

Figure 1.5. Single current source

Figure 1.6. Wilson source

Figure 1.7. Wilson source: equivalent diagram.

Figure 1.8. Sources.

Figure 1.9. Current divider.

Figure 1.10. Wilson source.

Figure 1.11. Cascode mounted current source

Figure 1.12. A simple current source.

Figure 1.13. An improved Wilson current source schematic.

Figure 1.14. A historical operational amplifier: 741

Figure 1.15. Simplified diagram of 741.

Figure 1.16. Active charge.

Figure 1.17. Characteristics of the active charge.

Figure 1.18. Input: polarization.

Figure 1.19. 741 polarization source

Figure 1.20. 741 polarization currents.

Figure 1.21. 741 output.

Figure 1.22. (a) Push-pull. (b) Voltage gain

Figure 1.23. Input resistance.

Figure 1.24. (a) Toward the calculation of Gm1 transconductance; (b) small sig...

Figure 1.25. Calculation of the output resistance.

Figure 1.26. Input resistor.

Figure 1.27. Input stage.

Figure 1.28. Central gain amplifier.

Figure 1.29. Serial diode in emitter follower.

Figure 1.30. Output resistance

Figure 1.31. The whole amplifier.

Figure 1.32. Electrical simulator flowchart

Figure 1.33. From circuit to graph

Figure 1.34. Laws of nodes

Figure 1.35. Branch equations

Figure 1.36. Current generator

Figure 1.37. Trapeze surface approximation

Figure 1.38. An equivalent scheme: a current source

Figure 1.39. Equivalent diagram

Figure 1.40. Convergence to the solution.

Figure 1.41. Buffon’s needle

Figure 1.42. Random distribution of R

Figure 1.43. Bell curve

Figure 1.44. A simple circuit.

Figure 1.45. Partial derivative values

Figure 1.46. Atypical responses of a circuit

Figure 1.47. Diagram of a differential pair

Figure 1.48. “Differential” amplifier.

Figure 1.49. Input/output characteristic

Figure 1.50. Equivalent diagram.

Figure 1.51. Input impedance of a quadripole.

Figure 1.52. Input impedances, relative to each input, in common mode.

Figure 1.53. Equivalent circuit.

Figure 1.54. A differential amplifier and its current source

Figure 1.55. Bipolar junction transistors with coupled emitters.

Figure 1.56. Characteristics I

c

(V

id

)

Figure 1.57. Small signal schematic for the differential mode.

Figure 1.58. Equivalent half circuit.

Figure 1.59. Simplified diagram.

Figure 1.60. Small signal diagram.

Figure 1.61. Differential amplifier and its voltage gain.

Figure 1.62. Output resistance: equivalent diagram.

Figure 1.63. Active charge differential amplifiers.

Figure 1.64. Output stage.

Figure 1.65. Output saturation.

Figure 1.66. Early curves and charge lines: RL > R?’L > R??”L....

Figure 1.67. Early curves.

Figure 1.68. Output push-pull

Figure 1.69. Power constraints

Figure 1.70. Input and output.

Figure 1.71. Common source mounting

Figure 1.72. Equivalent scheme in small signals

Figure 1.73. Gain module

Figure 1.74. Frequency versus R

L

Figure 1.75. Location of pole and zero as a function of RL. Asymptotic log-log...

Figure 1.76. Asymptotic Bode Diagram of the voltage gain module of Figure 1.71...

Figure 1.77. Effect of the separation of poles on the location of poles and ze...

Figure 1.78. Cascode assembly

Figure 1.79. Small signal equivalent schematic (R

L

= Rp // R

L

)

Figure 1.80. Small signal diagram to calculate the output impedance of Figure ...

Figure 1.81. Diagram log–asymptotic log of the module of the voltage gain BF o...

Figure 1.82. Diagram log–asymptotic log of the module of the voltage gains LF ...

Figure 1.83. Block diagram of the principle of the O.A

Figure 1.84. Entry stage of an O.A

Figure 1.85. Equivalent diagram of the differential pair

Figure 1.86. NMOS differential stage: common mode

Figure 1.87. Id (VMC) according to operating areas

Figure 1.88. I

N

and g

m

depending on the operating areas

Figure 1.89. Low-frequency voltage gain.

Figure 1.90. i

N

and i

P

depending on common mode voltage

Figure 1.91. NMOS differential pair.

Figure 1.92. Symbols for the two MOS.

Figure 1.93. NMOS inverter

Figure 1.94. Equivalent diagram in small signals.

Figure 1.95. Input and output impedance.

Figure 1.96. I

D

characteristics.

Figure 1.97. I

D

versus V

DS

: saturated M

2

.

Figure 1.98. Static regime for a NMOS inverter: output voltage versus input vo...

Figure 1.99. A layout of the NMOS inverter

Figure 1.100. MOS differential amplifier.

Figure 1.101. Two quadrant multipliers

Figure 1.102. Analog multiplier (differential input, one output).

Figure 1.103. Analog multiplier.

Figure 1.104. Two inputs/one output converter.

Figure 1.105. Phase detection

Figure 1.106. Block diagram of a PLL.

Figure 1.107. Detector output.

Figure 1.108. Block diagram of a PLL.

Figure 1.109. Pole/zero loci and voltage gain (in dB).

Figure 1.110. Transfer function

Figure 1.111. Root loci and voltage gain transfer function

Figure 1.112. Phase detector wave multiplied by a synchronous square wave sign...

Figure 1.113. A VCO.

Figure 1.114. Root loci and voltage gain transfer function.

Chapter 2

Figure 2.1. Mechanisms for injecting substrate noise into a digital inverter

Figure 2.2. Current flow lines for low-resistance substrate layer, with epitax...

Figure 2.3. Equivalent model for low-resistance substrate with epitaxial layer...

Figure 2.4. Distance equivalent resistance function for low-resistance substra...

Figure 2.5. Current flow lines for high-resistance substrate (thickness) with ...

Figure 2.6. Equivalent model for high-resistance substrate (thickness) with gr...

Figure 2.7. Distance equivalent resistance function for high-resistance substr...

Figure 2.8. Conceptual architecture of the extended ICEM model

Figure 2.9. Basic architecture of the extended ICEM model.

Figure 2.10. Equivalent digital capacity; this depends on the technology (numb...

Figure 2.11. Dedicated application to quantify digital bounces of ground and p...

Figure 2.12. Simulated power supply bounces for different line resistances

Figure 2.13. Simulated analog mass fluctuations

Figure 2.14. Disposition substrate insulation techniques: guard ring and tripl...

Figure 2.15. Comparative substrate insulation study on a virtual test case stu...

Figure 2.16. Topography of the VCO using a cross-coupled differential pair

Figure 2.17. Phase noise at 1 MHz (dBc/Hz) offset (carrier frequency is close ...

Figure 2.18. Topography of a Colpitts oscillator

Figure 2.19. Photograph of a VCO (core: 0.25 μm).

Figure 2.20. 20 GHz VCO spectrum.

Figure 2.21. VCO phase noise.

Figure 2.22. Oscillation frequency versus setting voltage

Figure 2.23. Noise distribution.

Figure 2.24. (a) Core of the VCO with contact injection; (b) VCO layout

Figure 2.25. (a) Microphotography of an evaluation circuit; (b) a layout of th...

Figure 2.26. Bias current sensitivity function (K

bias

)

Figure 2.27. Adjustment voltage sensitivity function (K

tune

).

Figure 2.28. VCO spectrum (process node: 0.25 mm) sensitivity due to the injec...

Figure 2.29. Measured Psbc function of the control voltage (50 m Vpk at 100 kH...

Figure 2.30. Control voltage sensitivity.

Figure 2.31. Colpitts oscillator diagram

Figure 2.32. (a) Device diagram (DDM) surrounded by passive elements (SPICE). ...

Figure 2.33. Phase shift (at collector) versus injected charges (mixed mode co...

Figure 2.34. Mixed-mode simulations: (a) crossing zero when descending, (b) bo...

Figure 2.35. Phase shifts at different nodes of interest

Figure 2.36. Phase shift for high pulse at tank capacity node

Figure 2.37. (a) Functional diagram of the parasitic signal propagation chain....

Figure 2.38. Typical power supply noise measurements, with different basic cap...

Figure 2.39. Overall noise spectrum/typical calculation of a gate disturbing a...

Chapter 3

Figure 3.1. (a) Stacked chips with wire bonding. (b) 3D TSV: stack structure...

Figure 3.2. Example of SIPO structure (stacked 5-chip SIP technology)

Figure 3.3. Example of a vertical/3D stack with three ICs

Figure 3.4. Classic 2D solution versus 3D concept.

Figure 3.5. Integration trend (STMicroelectronics/LETI).

Figure 3.6. A 3D image processor uses TSV technology that incorporates an imag...

Figure 3.7. Example of use of through via (drawing not to scale) (STMicroelect...

Figure 3.8. Example of an embodiment of a through via (LETI)

Figure 3.9. Computer tool for extracting resistances and substrate capacitance...

Figure 3.10. A typical IC design technology process

Figure 3.11. (a) Front view: medium-density TSVs and modeling including curren...

Figure 3.12. (a) Two contacts provided on the top surface of a single-layer su...

Figure 3.12bis. Multilayers with surface contacts to be tested (a) and corresp...

Figure 3.13. Template for some built-in contacts

Figure 3.14. Template for all integrated contacts

Figure 3.15. Potential of each layer.

Figure 3.16. Equivalent TSV model and contact

Figure 3.17. General steps of the algorithm (inverse DCT (IDCT))

Figure 3.18. Doping profile: 0.35 μm technology (p+/p region).

Figure 3.19. Characteristic of substrate geometry in Z-direction (region) and ...

Figure 3.20. (a) Impedance of 12 substrate layers with separation distance Dx ...

Figure 3.21. Substrate surface potentials obtained from 3D-IE (a) versus COMSO...

Figure 3.22. Model schematic: (a) TSV-contact and (b) TSV-model. The TSV dimen...

Figure 3.23. Resistance (a) and absolute value of reactance (b) of 3D-IE and C...

Figure 3.24. Potential: TSV-contact model with a TSV in an anisotropic materia...

Figure 3.25. Impedance modulus: 3D-IE and COMSOL between TSVs: (a) a function ...

Figure 3.26. Improvement of the equivalent model of coupling between TSV and c...

Figure 3.27. TSV/contact model diagram, wherein the TSV has an oxide coating. ...

Figure 3.28. Different contact shapes that can be considered in 3D-IE.

Figure 3.29. A technique for modeling a lateral variation of dielectric consta...

Figure 3.30. A high-density analytical TSV model.

Figure 3.31. Text file structure to define a specific substrate structure

Figure 3.32. Diagram of a CPW structure used for testing

Figure 3.33. “U” structure: a signal line located at the RDL level + 2 TSV + 2...

Figure 3.34. TSV RLCG model. TSV + current paths between the TSV and the two g...

Figure 3.35. Geometric and technological data of layers in the CPW and TSV cha...

Figure 3.36. Top view of a 2xTSV chain structure configuration.

Figure 3.37. SEM cross-section of the average TSV density used in TSV chains (...

Figure 3.38. Measurements with a vector network analyzer (VNA).

Figure 3.39. Effects of calibration and removal of coating.

Figure 3.40. Lumped ports.

Figure 3.41. Physical mesh control (left) and manual use of Swept Mesh Tech me...

Figure 3.42. Mesh layers on TSV surface

Figure 3.43. S parameter for the simple CPW structure (S

21

left; S

11

right).

Figure 3.44. Potential distribution on oxide layer (a and c) and below oxide l...

Figure 3.45. A potential distribution, below the oxide layer, via 3D-IE.

Figure 3.46. Comparison of S parameters, up to 20 GHz, between measurements ma...

Figure 3.47. Comparison of S parameters for a 240 m coplanar waveguide system ...

Figure 3.48. Temperature map in an SRAM.

Guide

Cover Page

Table of Contents

Title Page

Copyright Page

Preface

Begin Reading

References

Index

Other titles from ISTE in Electronics Engineering

WILEY END USER LICENSE AGREEMENT

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Analog Devices and Circuits 2

Analog Circuits

Christian Gontrand

First published 2024 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.

Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:

ISTE Ltd27-37 St George’s RoadLondon SW19 4EUUKwww.iste.co.uk

John Wiley & Sons, Inc.111 River StreetHoboken, NJ 07030USAwww.wiley.com

© ISTE Ltd 2024The rights of Christian Gontrand to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988.

Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s), contributor(s) or editor(s) and do not necessarily reflect the views of ISTE Group.

Library of Congress Control Number: 2023947046

British Library Cataloguing-in-Publication DataA CIP record for this book is available from the British LibraryISBN 978-1-78630-900-6

Preface

At the end of the Second World War, a new technological trend was born: integrated electronics. This relied on the enormous rise of integrable electronic circuits. This field has invaded our societies, and it is far from over!

Since the 1970s, modeling has contributed a great deal to the understanding of basic electric functions, making it possible to carry out “numerical experiments”, accelerating the effective development of circuits. In these studies, we hope to detect assembly errors as quickly as possible; for example, the arrows of currents, indicated in the diagrams of devices and circuits, allow us to verify that there is no break in the current flow between the plus and minus “rails”, typically correcting any “assembly” error of the circuit.

But, of course, this simulation has allowed for significant productivity gains, avoiding, in particular, the effective and overly-upstream manufacture of demonstrators.

This book is in fact a second volume, wherein the first discusses analog devices constituting these circuits. Of course, in this volume we will focus a little more on the “flagship chip”: the operational amplifier.

Acknowledgments

The author would like to thank the Union for the Mediterranean (UfM), Euromed University of Fes (UEMF), and Institut National des Sciences Appliquées (INSA) for supporting this study.

November 2023

1On Analog Circuits

1.1. Introduction: miscellaneous

1.1.1. SPICE

SPICE (Simulation Program with Integrated Circuit Emphasis) is the standard for simulating analog circuits. Anyone who does not know this does not belong to the fraternity of electronic circuit analogists.

SPICE was created at the University of California (Berkeley) in the early 1970s by Ron Rohrer’s team, including Larry Nagel (see his famous thesis). It later became the standard for analog simulators. Three versions followed one another, including SPICE3, dated 1985.

1.1.1.1. A brief history of SPICE

The need for a circuit simulation program, “smart” people with a vision and hardworking teams of students and professionals have all contributed to the realization and evolution of SPICE. A brief history of this powerful simulator is explained below, which is organized primarily according to the different versions of SPICE.

CANCER

In the early 1970s, Ron Rohrer hoped to develop a simulation program for his work on optimization at the University of California, Berkeley.

Rohrer’s students, including Larry Nagel, created CANCER (Computer Analysis of Nonlinear Circuits Excluding Radiation).

It performs DC, AC, and transient analysis.

The devices include diodes (Shockely equations) and bipolar junction transistors (Ebers–Moll equations).

Other simulation programs at the time included ECAP (Electronic Circuit Analysis Program) and IBM’s Autonetics TRAC.

SPICE1

In 1972, Nagel and Pederson launched SPICE1 (Simulation Program with IC Emphasis) in the public domain.

SPICE became the industry standard simulation tool.

Bipolar junction transistor models were replaced by Gummel–Poon equations.

JFET and MOSFET templates were added.

It was based on nodal analysis.

It was written in FORTRAN code and runs on large computers.

SPICE2

Nagel’s 1975 version offered significant improvements.

Modified nodal analysis (MNA), replacing the old analysis, supported voltage sources and inductors from this point onwards.

Memory was dynamically allocated to accommodate the increasing size and complexity of circuits.

It has adjustable simulation of time step control speeds.

The MOSFET and bipolar models were revised and extended.

SPICE2G.6 (1983) is the latest version of FORTRAN.

At present, it is still available in Berkeley. Many commercial simulators today are based on SPICE2G.6.

SPICE3

SPICE code was rewritten in programming language C (1985).

It has a graphical interface to display the results.

It included polynomial capacitors, inductors and voltage-controlled sources.

The new version eliminated many convergence problems.

Models added were as follows: MESFET, lossy transmission line and nonideal switch.

Improved semiconductor models adapted to smaller transistor geometries.

It is not backward compatible with SPICE2.

1980s and beyond

Published commercial versions include HSPICE, IS_SPICE and MICROCAP.

MicroSim launched PSPICE, the first PC version of SPICE.

SPICE attracted many more users in industry and academia.

EDLO is dedicated to RF.

HICUM is dedicated to microwaves.

Companies integrated SPICE versions into their “schematics” entry and layout packages (geometry/pattern).

1.1.1.2. A SPICE program

SPICE is therefore the essential software for studying analog circuits.

1.1.1.3. Program example

The program example is given as follows.

I-V characteristics for SS model of CMOS devices

MODEL NSS NMOS LEVEL =3 RSH=0 TOX=275E-10 LD=0 . 1E-6 XJ=0 . 14E-6

+ CJ=1 . 6E-4 CJSW=1 8E-10 UO550 VTO=1 . 022 CGSO=1 . 3E10

+ CGDO=1 3E-10 NSUB=4E15 NFS=1E10

+ VMAX=12E4 PB=0 . 7 MJ=0 . 5 MJSW=0 . 3 THETA=0 . 06 KAPPA=0 . 4 ETA=0 . 14

. MODEL PSS PMOS LEVEL=3RSH=0 TOX=275E-10 LD=0 . 3E-6 XJ=0 . 42E-6

+ CJ=7 . 7E-4 CJSW=5 . 4E-10 UO=180 VTO=-1 . 046 CGSO=4E-10

+ CGDO=4E-10 TPG=-1 NSUB=7E15 NFS=1E10

+ VMAX=12E4 PB=0 . 7 MJ=0 . 5 MJSW=0 . 3 ETA=0 . 06 THETA=0 . 03 KAPPA=0 . 4

M1 1 10 0 0 NSS W=13 . 2U L=2 . 25U

VDS 20 0

* VGS is positive for nMOS and negative for pMOS

VGS 10 0 5V

* VIDS defines current direction for drain

VIDS 20 1

.DC VDS 0 5 0 . 05

.PRINT DC I (VIDS)

.PLOT DC I (VIDS)

.WIDTH IN=75 OUT=75

.END

Calculation of current-voltage characteristics of .CMOS

Used for the SPICE (Simulation Program with Integrated Circuits Emphasis) simulation program.

* CMOS OPERATIONAL AMPLIFIER *

**** INPUT LISTING   TEMPERATURE = 27.000 DEG C**************************************************************************************

.MODEL MP1 PMOS (LEVEL=3 TOX=250E-10 VTO=0 . 55

+ GAMMA=0 . 38 KP=25 . 2E-6 NSUB=2E16 THETA=0 . 163

+VMAX=1E5 FTA=0 DELTA=0 KAPPA=0 . 8 CGSO=0 . 65N CGDO=0 . 65N )

.MODEL MN1 NMOS (LEVEL=3 TOX=250E-10 VTO=0 . 55

+ GAMMA=0 . 1 KP=86 . 8E-6 NSUB=2E16 THETA=0 . 08

+ VMAX=1E5 FTA=0 DELTA=0 KAPPA=0 . 8 CGSO=0 . 42N CGDO= 0 . 42N )

VDD 10 0 DC 5

VSS 11 0 DC -5

CCR 4 5 10P

CCH 5 0 20P

RIN 16 0 1

* AMPLIFIER

VIN 15 0 AC 1

.AC DEC 5 100 100MEG

.PLOT AC VD8 (5) VP (5)

.WIDTH OUT =80

.END

1.1.2. Technologies: conception-aided design

CMOS operational amplifier

Technology

The technology used is as follows:

passivation: e

sio2

: 0.5 − 1 μm;

N

++

: heavily doped buried layer → low resistance;

P

+

zones: insulation wells;

P

+

-N junction in reverse → insulation;

N

++

zone: only for “beep”;

Si

3

N

4

: silicon nitride (mask for implants);

Si

3

N

4

: prevents oxide growth (but beaks of parasitic birds at the edge of masks: birds peaks).

Below, we shall resume the basic steps of manufacturing the two preferred devices of microelectronics. Diagrams for this have been given in Volume 1.

Bipolar junction transistor

N_epitaxy collector region (0.1–10 Ω.cm):

Opening windows are used to create the base and insulation wells. Opening in the base region is used to create the emitter.

Base: a few

N+: ohmic collector contact

Evaporation of contacts

P-channel MOS:

thermal oxidation: ;

P

+

implementation for drain.

Reoxidation takes place and then so does photo-etching of the oxide.

Gate oxide (dry O2 for good dielectric quality); thickness: 0.1–0.15 μm.

Field oxide (FOX: Field OXide; LOCOS: LOCal Oxide on Silicon); very thick: 1–1.5 μm.

Self-aligned gate

I2: (ionic implantation) = 80 keV; the oxide lets boron through (a very small atom), but the gate stops it, and therefore serves as a natural mask.

Polysilicon gate NMOS inverter

Fabrication process steps:

Si

3

N

4

is impermeable to O

2

;

boron: P type;

LOCOS:

Si

3

N

4

;

Bird beak: SiO

2

;

threshold voltage adjustment is expressed as: V

T

adjust;

phosphorus → N type.

The I2 of phosphorus creates source and drain zones and, at the same time, dopes the polysilicone.

The polysilicone “embedded” in the oxide makes it possible to manufacture several levels of interconnections.

Self-aligned polysilicon gate

Phase 1: Local oxidation:

Thermal growth of a thin layer of silicon oxide.

Engraving according to level 1:

field insulation implantation (B

+

ion);

annealing of the implantation (annealing, for redistribution).

Localized thermal oxidation, followed by the removal of the resin from the nitride and the thin oxide.

Phase 2: Implementation of depletion:

Thin gate oxide growth (≃ 500 Å).

Implementation of depletion (P−) according to level 2.

Phase 3: Adjustment of enhancement transistors:

Adjustment implementation (B+) according to level 3.

Phase 4: Buried contacts or pre-contacts:

Etching of the thin oxide according to level 4.

Phase 5: Gates:

Uniform deposition of polycrystalline silicon and etching thereof according to level 5.

Source and drain implementation (P

or

As

), annealing and oxidation.

Phase 6: Contacts:

Deposition of insulating oxide and etching of contacts according to level 6.

Phase 7: Metallization:

Uniform deposition of aluminum and then etching according to level 7.

Phase 8: Deposition of final protective oxide and then etching according to level 8. This level only concerns the electric accesses of the circuit: contact and test pads.

Insulated multi-collector outputs

This device operates in reverse mode (the emitter is replaced by the collector and vice versa).

Here, the buried layer serves as the emitter.

It has five manufacturing steps, as follows:

I

2

 N

−

;

I

2

 P;

−I

2

 N

−

;

contact window;

metallization.

Power transistor

Double diffusion D.MOS

To ensure a high voltage withstand, we need to create weakly doped areas that are highly resistive, which “take in” the potential differences.

Purpose: Reducing the channel

L< 1 μm

Note: Asymmetric field region → high breakdown voltage.

L: effective length of the channel.

Highly N-doped substrate is used (→ N-channel MOS).

Boron implantation is performed (P type).

Epitaxy (p) from silane (exodiffusion of impurities P from

N

−

to P): the

N

−

resting zone will be the field region of the transistor; and the P region (1 μm) will be the channel zone. The drain region is then protected by SiO

2

− Si

3

N

4

−SiO

2

(?•) during the growth of the field oxide (*).

The oxynitride is then removed, and the thick oxide is etched to implant the source region.

Then oxidation occurs. V-shaped anisotropic chemical attack (direction 100>) takes place faster than 111>.

Growth of the gate oxide; metallization: source, gate and drain.