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Neuromorphic electronic engineering takes its inspiration from the functioning of nervous systems to build more power efficient electronic sensors and processors. Event-based neuromorphic systems are inspired by the brain's efficient data-driven communication design, which is key to its quick responses and remarkable capabilities. This cross-disciplinary text establishes how circuit building blocks are combined in architectures to construct complete systems. These include vision and auditory sensors as well as neuronal processing and learning circuits that implement models of nervous systems. Techniques for building multi-chip scalable systems are considered throughout the book, including methods for dealing with transistor mismatch, extensive discussions of communication and interfacing, and making systems that operate in the real world. The book also provides historical context that helps relate the architectures and circuits to each other and that guides readers to the extensive literature. Chapters are written by founding experts and have been extensively edited for overall coherence. This pioneering text is an indispensable resource for practicing neuromorphic electronic engineers, advanced electrical engineering and computer science students and researchers interested in neuromorphic systems. Key features: * Summarises the latest design approaches, applications, and future challenges in the field of neuromorphic engineering. * Presents examples of practical applications of neuromorphic design principles. * Covers address-event communication, retinas, cochleas, locomotion, learning theory, neurons, synapses, floating gate circuits, hardware and software infrastructure, algorithms, and future challenges.
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Seitenzahl: 919
Veröffentlichungsjahr: 2014
Edited by
Shih-Chii Liu Tobi Delbruck Giacomo Indiveri Adrian Whatley Rodney Douglas
University of Zürich and ETH Zürich Switzerland
This edition first published 2015 © 2015 John Wiley & Sons, Ltd
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Library of Congress Cataloging-in-Publication Data applied for.
ISBN: 9780470018491
This book is dedicated to the memories of Misha Mahowald, Jörg Kramer, and Paul Mueller.
List of Contributors
Foreword
Acknowledgments
List of Abbreviations and Acronyms
Chapter 1: Introduction
1.1 Origins and Historical Context
1.2 Building Useful Neuromorphic Systems
References
Part I: Understanding Neuromorphic Systems
Chapter 2: Communication
2.1 Introduction
2.2 Address-Event Representation
2.3 Considerations for AER Link Design
2.4 The Evolution of AER Links
2.5 Discussion
References
Notes
Chapter 3: Silicon Retinas
3.1 Introduction
3.2 Biological Retinas
3.3 Silicon Retinas with Serial Analog Output
3.4 Asynchronous Event-Based Pixel Output Versus Synchronous Frames
3.5 AER Retinas
3.6 Silicon Retina Pixels
3.7 New Specifications for Silicon Retinas
3.8 Discussion
References
Chapter 4: Silicon Cochleas
4.1 Introduction
4.2 Cochlea Architectures
4.3 Spike-Based Cochleas
4.4 Tree Diagram
4.5 Discussion
References
Chapter 5: Locomotion Motor Control
5.1 Introduction
5.2 Modeling Neural Circuits in Locomotor Control
5.3 Neuromorphic CPGs at Work
5.4 Discussion
References
Chapter 6: Learning in Neuromorphic Systems
6.1 Introduction: Synaptic Connections, Memory, and Learning
6.2 Retaining Memories in Neuromorphic Hardware
6.3 Storing Memories in Neuromorphic Hardware
6.4 Toward Associative Memories in Neuromorphic Hardware
6.5 Attractor States in a Neuromorphic Chip
6.6 Discussion
References
Part II: Building Neuromorphic Systems
Chapter 7: Silicon Neurons
7.1 Introduction
7.2 Silicon Neuron Circuit Blocks
7.3 Silicon Neuron Implementations
7.4 Discussion
References
Chapter 8: Silicon Synapses
8.1 Introduction
8.2 Silicon Synapse Implementations
8.3 Dynamic Plastic Synapses
8.4 Discussion
References
Chapter 9: Silicon Cochlea Building Blocks
9.1 Introduction
9.2 Voltage-Domain Second-Order Filter
9.3 Current-Domain Second-Order Filter
9.4 Exponential Bias Generation
9.5 The Inner Hair Cell Model
9.6 Discussion
References
Chapter 10: Programmable and Configurable Analog Neuromorphic ICs
10.1 Introduction
10.2 Floating-Gate Circuit Basics
10.3 Floating-Gate Circuits Enabling Capacitive Circuits
10.4 Modifying Floating-Gate Charge
10.5 Accurate Programming of Programmable Analog Devices
10.6 Scaling of Programmable Analog Approaches
10.7 Low-Power Analog Signal Processing
10.8 Low-Power Comparisons to Digital Approaches: Analog Computing in Memory
10.9 Analog Programming at Digital Complexity: Large-Scale Field Programmable Analog Arrays
10.10 Applications of Complex Analog Signal Processing
10.11 Discussion
References
Chapter 11: Bias Generator Circuits
11.1 Introduction
11.2 Bias Generator Circuits
11.3 Overall Bias Generator Architecture Including External Controller
11.4 Typical Characteristics
11.5 Design Kits
11.6 Discussion
References
Chapter 12: On-Chip AER Communication Circuits
12.1 Introduction
12.2 AER Transmitter Blocks
12.3 AER Receiver Blocks
12.4 Discussion
References
Note
Chapter 13: Hardware Infrastructure
13.1 Introduction
13.2 Hardware Infrastructure Boards for Small Systems
13.3 Medium-Scale Multichip Systems
13.4 FPGAs
13.5 Discussion
References
Notes
Chapter 14: Software Infrastructure
14.1 Introduction
14.2 Chip and System Description Software
14.3 Configuration Software
14.4 Address Event Stream Handling Software
14.5 Mapping Software
14.6 Software Examples
14.7 Discussion
References
Notes
Chapter 15: Algorithmic Processing of Event Streams
15.1 Introduction
15.2 Requirements for Software Infrastructure
15.3 Embedded Implementations
15.4 Examples of Algorithms
15.5 Discussion
References
Note
Chapter 16: Towards Large-Scale Neuromorphic Systems
16.1 Introduction
16.2 Large-Scale System Examples
16.3 Discussion
References
Chapter 17: The Brain as Potential Technology
17.1 Introduction
17.2 The Nature of Neuronal Computation: Principles of Brain Technology
17.3 Approaches to Understanding Brains
17.4 Some Principles of Brain Construction and Function
17.5 An Example Model of Neural Circuit Processing
17.6 Toward Neuromorphic Cognition
References
Index
End User License Agreement
Chapter 2
Table 2.1
Chapter 3
Table 3.1
Chapter 8
Table 8.1
Chapter 16
Table 16.1