Handbook of 3D Integration, Volume 3 E-Book

• Herausgeber: Wiley-VCH
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 665

Veröffentlichungsjahr: 2014

Beschreibung

Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology. As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology.
Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.

Leseprobe

CONTENTS

Cover

Related Titles

Title Page

Copyright

List of Contributors

Chapter 1: 3D IC Integration Since 2008

1.1 3D IC Nomenclature

1.2 Process Standardization

1.3 The Introduction of Interposers (2.5D)

1.4 The Foundries

1.5 Memory

1.6 The Assembly and Test Houses

1.7 3D IC Application Roadmaps

References

Chapter 2: Key Applications and Market Trends for 3D Integration and Interposer Technologies

2.1 Introduction

2.2 Advanced Packaging Importance in the Semiconductor Industry is Growing

2.3 3D Integration-Focused Activities – The Global IP Landscape

2.4 Applications, Technology, and Market Trends

References

Chapter 3: Economic Drivers and Impediments for 2.5D/3D Integration

3.1 3D Performance Advantages

3.2 The Economics of Scaling

3.3 The Cost of Future Scaling

3.4 Cost Remains the Impediment to 2.5D and 3D Product Introduction

References

Chapter 4: Interposer Technology

4.1 Definition of 2.5D Interposers

4.2 Interposer Drivers and Need

4.3 Comparison of Interposer Materials

4.4 Silicon Interposers with TSV

4.5 Lower Cost Interposers

4.6 Interposer Technical and Manufacturing Challenges

4.7 Interposer Application Examples

4.8 Conclusions

References

Chapter 5: TSV Formation Overview

5.1 Introduction

5.2 TSV Process Approaches

5.3 TSV Fabrication Steps

5.4 Yield and Reliability

References

Chapter 6: TSV Unit Processes and Integration

6.1 Introduction

6.2 TSV Process Overview

6.3 TSV Unit Processes

6.4 Integration and Co-optimization of Unit Processes in Via Formation Sequence

6.5 Co-optimization of Unit Processes in Backside Processing and Via-Reveal Flow

6.6 Integration and Co-optimization of Unit Processes in Via-Last Flow

6.7 Integration with Packaging

6.8 Electrical Characterization of TSVs

6.9 Conclusions

References

Chapter 7: TSV Formation at ASET

7.1 Introduction

7.2 Via-Last TSV for Both D2D and W2W Processes in ASET

7.3 TSV Process for D2D

7.4 TSV Process for W2W

7.5 Conclusions

References

Chapter 8: Laser-Assisted Wafer Processing: New Perspectives in Through-Substrate Via Drilling and Redistribution Layer Deposition

8.1 Introduction

8.2 Laser Drilling of TSVs

8.3 Direct-Write Deposition of Redistribution Layers

8.4 Conclusions and Outlook

References

Chapter 9: Temporary Bonding Material Requirements

9.1 Introduction

9.2 Technology Options

9.3 Requirements of a Temporary Bonding Material

9.4 Considerations for Successful Processing

9.5 Surviving the Backside Process

9.6 Debonding

References

Chapter 10: Temporary Bonding and Debonding – An Update on Materials and Methods

10.1 Introduction

10.2 Carrier Selection for Temporary Bonding

10.3 Selection of Temporary Bonding Adhesives

10.4 Bonding and Debonding Processes

10.5 Equipment and Process Integration

References

Chapter 11: ZoneBOND®: Recent Developments in Temporary Bonding and Room-Temperature Debonding

11.1 Introduction

11.2 Thin Wafer Processing

11.3 ZoneBOND Room-Temperature Debonding

11.4 Conclusions

References

Chapter 12: Temporary Bonding and Debonding at TOK

12.1 Introduction

12.2 Zero Newton Technology

12.3 Conclusions

References

Chapter 13: The 3M™ Wafer Support System (WSS)

13.1 Introduction

13.2 System Description

13.3 General Advantages

13.4 High-Temperature Material Solutions

13.5 Process Considerations

13.6 Future Directions

13.7 Summary

Reference

Chapter 14: Comparison of Temporary Bonding and Debonding Process Flows

14.1 Introduction

14.2 Studies of Wafer Bonding and Thinning

14.3 Backside Processing

14.4 Debonding and Cleaning

References

Chapter 15: Thinning, Via Reveal, and Backside Processing – Overview

15.1 Introduction

15.2 Wafer Edge Trimming

15.3 Thin Wafer Support Systems

15.4 Wafer Thinning

15.5 Thin Wafer Backside Processing

References

Chapter 16: Backside Thinning and Stress-Relief Techniques for Thin Silicon Wafers

16.1 Introduction

16.2 Thin Semiconductor Devices

16.3 Wafer Thinning Techniques

16.4 Fracture Tests for Thin Silicon Wafers

16.5 Comparison of Stress-Relief Techniques for Wafer Backside Thinning

16.6 Process Flow for Wafer Thinning and Dicing

16.7 Summary and Outlook on 3D Integration

References

Chapter 17: Via Reveal and Backside Processing

17.1 Introduction

17.2 Via Reveal and Backside Processing in Via-Middle Process

17.3 Backside Processing in Back-Via Process

17.4 Backside Processing and Impurity Gettering

17.5 Backside Processing for RDL Formation

References

Chapter 18: Dicing, Grinding, and Polishing (Kiru Kezuru and Migaku)

18.1 Introduction

18.2 Grinding and Polishing

18.3 Dicing

18.4 Summary

Further Reading

Chapter 19: Overview of Bonding and Assembly for 3D Integration

19.1 Introduction

19.2 Direct, Indirect, and Hybrid Bonding

19.3 Requirements for Bonding Process and Materials

19.4 Bonding Quality Characterization

19.5 Discussion of Specific Bonding and Assembly Technologies

19.6 Summary and Conclusions

References

Chapter 20: Bonding and Assembly at TSMC

20.1 Introduction

20.2 Process Flow

20.3 Chip-on-Wafer Stacking

20.4 CoW-on-Substrate (CoWoS) Stacking

20.5 CoWoS Versus CoCoS

20.6 Testing and Known Good Stacks (KGS)

20.7 Future Perspectives

References

Chapter 21: TSV Packaging Development at STATS ChipPAC

21.1 Introduction

21.2 Development of the 3DTSV Solution for Mobile Platforms

21.3 Alternative Approaches and Future Developments

References

Chapter 22: Cu–SiO2 Hybrid Bonding

22.1 Introduction

22.2 Blanket Cu–SiO2 Direct Bonding Principle

22.3 Aligned Bonding

22.4 Blanket Metal Direct Bonding Principle

22.5 Electrical Characterization

22.6 Conclusions

References

Chapter 23: Bump Interconnect for 2.5D and 3D Integration

23.1 History

23.2 C4 Solder Bumps

23.3 Copper Pillar Bumps

23.4 Cu Bumps

23.5 Electromigration

References

Chapter 24: Self-Assembly Based 3D and Heterointegration

24.1 Introduction

24.2 Self-Assembly Process

24.3 Key Parameters of Self-Assembly on Alignment Accuracies

24.4 How to Interconnect Self-Assembled Chips to Chips or Wafers

References

Chapter 25: High-Accuracy Self-Alignment of Thin Silicon Dies on Plasma-Programmed Surfaces

25.1 Introduction

25.2 Principle of Fluidic Self-Alignment Process for Thin Dies

25.3 Plasma Programming of the Surface

25.4 Preparation of Materials for Self-Alignment Experiments

25.5 Self-Alignment Experiments

25.6 Results of Self-Alignment Experiments

25.7 Discussion

25.8 Conclusions

References

Chapter 26: Challenges in 3D Fabrication

26.1 Introduction

26.2 High-Volume Manufacturing for 3D Integration

26.3 Technology Challenges

26.4 Front-Side and Backside Wafer Processes

26.5 Bonding and Underfills

26.6 Multitier Stacking

26.7 Wafer Thinning and Thin Die and Wafer Handling

26.8 Strata Packaging and Assembly

26.9 Yield Management

26.10 Reliability

26.11 Cost Management

26.12 Future Perspectives

References

Chapter 27: Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices

27.1 Introduction

27.2 Cu Stress in TSV

27.3 Mitigation of Cu Pumping

27.4 Impact of TSVs on FEOL Devices

References

Chapter 28: Implications of Stress/Strain and Metal Contamination on Thinned Die

28.1 Introduction

28.2 Impacts of Cu Contamination on Device Reliabilities in Thinned 3DLSI

28.3 Impacts of Local Stress and Strain on Device Reliabilities in Thinned 3DLSI

References

Chapter 29: Metrology Needs for 2.5D/3D Interconnects

29.1 Introduction: 2.5D and 3D Reference Flows

29.2 TSV Formation

29.3 MEOL Metrology

29.4 Assembly and Packaging Metrology

29.5 Summary

References

Index

End User License Agreement

List of Tables

Table 1.1

Table 1.2

Table 1.3

Table 3.1

Table 3.2

Table 4.1

Table 4.2

Table 4.3

Table 6.1

Table 6.2

Table 6.3

Table 7.1

Table 7.2

Table 8.1

Table 10.1

Table 10.2

Table 11.1

Table 11.2

Table 12.1

Table 12.2

Table 13.1

Table 14.1

Table 16.1

Table 16.2

Table 16.3

Table 21.1

Table 22.1

Table 22.2

Table 22.3

Table 22.4

Table 27.1

List of Illustrations

Figure 1.1

Figure 1.2

Figure 1.3

Figure 1.4

Figure 1.5

Figure 1.6

Figure 1.7

Figure 1.8

Figure 1.9

Figure 1.10

Figure 1.11

Figure 2.1

Figure 2.2

Figure 2.3

Figure 2.4

Figure 2.5

Figure 2.6

Figure 2.7

Figure 2.8

Figure 2.9

Figure 2.10

Figure 2.11

Figure 2.12

Figure 2.13

Figure 2.14

Figure 2.15

Figure 2.16

Figure 2.17

Figure 2.18

Figure 2.19

Figure 2.20

Figure 3.1

Figure 3.2

Figure 3.3

Figure 3.4

Figure 3.5

Figure 3.6

Figure 3.7

Figure 4.1

Figure 4.2

Figure 4.3

Figure 4.4

Figure 4.5

Figure 4.6

Figure 4.7

Figure 4.8

Figure 4.9

Figure 4.10

Figure 4.11

Figure 4.12

Figure 4.13

Figure 4.14

Figure 4.15

Figure 4.16

Figure 4.17

Figure 4.18

Figure 4.19

Figure 4.20

Figure 4.21

Figure 4.22

Figure 4.23

Figure 4.24

Figure 4.25

Figure 5.1

Figure 5.2

Figure 5.3

Figure 5.4

Figure 5.5

Figure 5.6

Figure 6.1

Figure 6.2

Figure 6.3

Figure 6.4

Figure 6.5

Figure 6.6

Figure 6.7

Figure 6.8

Figure 6.9

Figure 6.10

Figure 6.11

Figure 7.1

Figure 7.2

Figure 7.3

Figure 7.4

Figure 7.5

Figure 7.6

Figure 7.7

Figure 7.8

Figure 7.9

Figure 7.10

Figure 7.11

Figure 7.12

Figure 7.13

Figure 7.14

Figure 7.15

Figure 7.16

Figure 7.17

Figure 7.18

Figure 7.19

Figure 7.20

Figure 7.21

Figure 7.22

Figure 7.23

Figure 7.24

Figure 7.25

Figure 7.26

Figure 7.27

Figure 7.28

Figure 7.29

Figure 7.30

Figure 7.31

Figure 7.32

Figure 7.33

Figure 8.1

Figure 8.2

Figure 8.3

Figure 8.4

Figure 8.5

Figure 8.6

Figure 8.7

Figure 8.8

Figure 8.9

Figure 8.10

Figure 9.1

Figure 9.2

Figure 9.3

Figure 9.4

Figure 9.5

Figure 9.6

Figure 9.7

Figure 9.8

Figure 10.1

Figure 10.2

Figure 10.3

Figure 10.4

Figure 10.5

Figure 10.6

Figure 10.7

Figure 10.8

Figure 11.1

Figure 11.2

Figure 11.3

Figure 11.4

Figure 11.5

Figure 11.6

Figure 12.1

Figure 12.2

Figure 12.3

Figure 12.4

Figure 12.5

Figure 12.6

Figure 12.7

Figure 12.8

Figure 13.1

Figure 13.2

Figure 13.3

Figure 13.4

Figure 13.5

Figure 13.6

Figure 13.7

Figure 14.1

Figure 15.1

Figure 15.2

Figure 15.3

Figure 15.4

Figure 15.5

Figure 15.6

Figure 15.7

Figure 15.8

Figure 15.9

Figure 15.10

Figure 15.11

Figure 15.12

Figure 15.13

Figure 15.14

Figure 15.15

Figure 16.1

Figure 16.2

Figure 16.3

Figure 16.4

Figure 16.5

Figure 16.6

Figure 16.7

Figure 16.8

Figure 16.9

Figure 16.10

Figure 16.11

Figure 16.12

Figure 17.1

Figure 17.2

Figure 17.3

Figure 17.4

Figure 17.5

Figure 17.6

Figure 17.7

Figure 17.8

Figure 17.9

Figure 17.10

Figure 17.11

Figure 17.12

Figure 17.13

Figure 17.14

Figure 17.15

Figure 18.1

Figure 18.2

Figure 18.3

Figure 18.4

Figure 18.5

Figure 18.6

Figure 18.7

Figure 18.8

Figure 18.9

Figure 18.10

Figure 18.11

Figure 18.12

Figure 18.13

Figure 18.14

Figure 18.15

Figure 18.16

Figure 18.17

Figure 18.18

Figure 18.19

Figure 18.20

Figure 18.21

Figure 18.22

Figure 18.23

Figure 18.24

Figure 18.25

Figure 18.26

Figure 19.1

Figure 19.2

Figure 19.3

Figure 19.4

Figure 19.5

Figure 19.6

Figure 19.7

Figure 19.8

Figure 19.9

Figure 19.10

Figure 19.11

Figure 19.12

Figure 19.13

Figure 19.14

Figure 20.1

Figure 20.2

Figure 20.3

Figure 20.4

Figure 21.1

Figure 21.2

Figure 21.3

Figure 21.4

Figure 21.5

Figure 21.6

Figure 21.7

Figure 21.8

Figure 21.9

Figure 21.10

Figure 22.1

Figure 22.2

Figure 22.3

Figure 22.4

Figure 22.5

Figure 22.6

Figure 22.7

Figure 22.8

Figure 22.9

Figure 22.10

Figure 22.11

Figure 22.12

Figure 22.13

Figure 22.14

Figure 22.15

Figure 22.16

Figure 22.17

Figure 22.18

Figure 22.19

Figure 22.20

Figure 22.21

Figure 23.1

Figure 23.2

Figure 23.3

Figure 23.4

Figure 23.5

Figure 23.6

Figure 23.7

Figure 23.8

Figure 23.9

Figure 23.10

Figure 23.11

Figure 24.1

Figure 24.2

Figure 24.3

Figure 24.4

Figure 24.5

Figure 24.6

Figure 25.1

Figure 25.2

Figure 25.3

Figure 25.4

Figure 25.5

Figure 25.6

Figure 25.7

Figure 25.8

Figure 26.1

Figure 26.2

Figure 26.3

Figure 26.4

Figure 26.5

Figure 26.6

Figure 26.7

Figure 26.8

Figure 26.9

Figure 26.10

Figure 26.11

Figure 26.12

Figure 26.13

Figure 26.14

Figure 26.15

Figure 26.16

Figure 26.17

Figure 26.18

Figure 26.19

Figure 26.20

Figure 26.21

Figure 26.22

Figure 26.23

Figure 26.24

Figure 26.25

Figure 27.1

Figure 27.2

Figure 27.4

Figure 27.3

Figure 27.5

Figure 27.6

Figure 27.7

Figure 27.8

Figure 27.9

Figure 27.10

Figure 27.11

Figure 27.12

Figure 27.13

Figure 27.14

Figure 27.15

Figure 28.1

Figure 28.2

Figure 28.3

Figure 28.4

Figure 28.5

Figure 28.6

Figure 28.7

Figure 28.8

Figure 28.9

Figure 28.10

Figure 28.11

Figure 28.12

Figure 28.13

Figure 28.14

Figure 28.15

Figure 29.1

Figure 29.2

Figure 29.3

Figure 29.4

Figure 29.5

Figure 29.6

Figure 29.7

Figure 29.8

Figure 29.9

Figure 29.10

Figure 29.11

Figure 29.12

Figure 29.13

Figure 29.14

Figure 29.15

Figure 29.16

Figure 29.17

Figure 29.18

Figure 29.19

Figure 29.20

Figure 29.21

Figure 29.22

Figure 29.23

Figure 29.24

Figure 29.25

Figure 29.26

Figure 29.27

Figure 29.28

Figure 29.29

Figure 29.30

Figure 29.31

Figure 29.32

Figure 29.33

Figure 29.34

Figure 29.35

Figure 29.36

Figure 29.37

Figure 29.38

Figure 29.39

Figure 29.40

Figure 29.41

Guide

Cover

Table of Contents

List of Contributors

Chapter 1

Pages

ii

iii

iv

xvii

xviii

xix

xx

xxi

xxii

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

Related Titles

Brand, O., Dufour, I., Heinrich, S.M., Josse, F. (eds.)

Resonant MEMS

Principles, Modeling, Implementation and Applications

2014

Print ISBN: 978-3-527-33545-9

Iannacci, J.

Practical Guide to RF-MEMS

2013

Print ISBN: 978-3-527-33564-0

Ramm, P., Lu, J.J., Taklo, M.M. (eds.)

Handbook of Wafer Bonding

2012

Print ISBN: 978-3-527-32646-4

Saile, V., Wallrabe, U., Tabata, O., Korvink, J.G. (eds.)

LIGA and its Applications

2009

Print ISBN: 978-3-527-31698-4

Garrou, P., Bower, C., Ramm, P. (eds.)

Handbook of 3D Integration

Technology and Applications of 3D Integrated Circuits

2008

Print ISBN: 978-3-527-33265-6

Handbook of 3D Integration

3D Process Technology

Edited by Philip Garrou, Mitsumasa Koyanagi, and Peter Ramm

All books published by Wiley-VCH are carefully produced. Nevertheless, authors, editors, and publisher do not warrant the information contained in these books, including this book, to be free of errors. Readers are advised to keep in mind that statements, data, illustrations, procedural details or other items may inadvertently be inaccurate.

Library of Congress Card No.: applied for

British Library Cataloguing-in-Publication Data

A catalogue record for this book is available from the British Library.

Bibliographic information published by the Deutsche Nationalbibliothek

The Deutsche Nationalbibliothek lists this publication in the Deutsche Nationalbibliografie; detailed bibliographic data are available on the Internet at <http://dnb.d-nb.de>.

©2014 Wiley-VCH Verlag GmbH & Co. KGaA, Boschstr. 12, 69469 Weinheim, Germany

All rights reserved (including those of translation into other languages). No part of this book may be reproduced in any form – by photoprinting, microfilm, or any other means – nor transmitted or translated into a machine language without written permission from the publishers. Registered names, trademarks, etc. used in this book, even when not specifically marked as such, are not to be considered unprotected by law.

Print ISBN: 978-3-527-33466-7

ePDF ISBN: 978-3-527-67013-0

ePub ISBN: 978-3-527-67012-3

mobi ISBN: 978-3-527-67011-6

oBook ISBN: 978-3-527-67010-9

List of Contributors

Richard A. Allen

National Institute of Standards and Technology (NIST)

100 Bureau Drive

Gaithersburg, MD 20899

USA

Wilfried Bair

SUSS MicroTec AG

Schleißheimer Str. 90

85748 Garching

Germany

Floriane Baudin

CEA/LETI

Department of Heterogeneous Integration on Silicon

17, rue des Martyrs

38054 Grenoble CEDEX 9

France

Jicheol Bea

Tohoku University

New Industry Creation Hatchery Center (NICHe)

6-6-10 Aza-Aoba, Aramaki

Sendai 980-8579

Japan

Rozalia Beica

Yole Developpement

Le Quartz

75, cours Emile Zola

69100 Lyon-Villeurbanne

France

Yann Beilliard

CEA/LETI

Department of Heterogeneous Integration on Silicon

17, rue des Martyrs

38054 Grenoble CEDEX 9

France

Eric Beyne

IMEF

Kapeldreef 75

3001 Leuven

Belgium

Karlheinz Bock

Fraunhofer Research Institution for

Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Jürgen Burggraf

E. Thallner GmbH

EV Group

DI-Erich-Thallner-Straße 1

4782 Sankt Florian am Inn

Austria

Daniel Burgstaller

E. Thallner GmbH

EV Group

DI-Erich-Thallner-Straße 1

4782 Sankt Florian am Inn

Austria

Joke De Messemaeker

IMEF

Kapeldreef 75

3001 Leuven

Belgium

Léa Di Cioccio

CEA/LETI

Department of Heterogeneous Integration on Silicon

17, rue des Martyrs

38054 Grenoble CEDEX 9

France

Blake Dronen

3M Electronics Markets Materials

Building 225-3S-06

St. Paul, MN 55144-1000

USA

Jean-Christophe Eloy

Yole Developpement

Le Quartz

75, cours Emile Zola

69100 Lyon-Villeurbanne

France

Takafumi Fukushima

Tohoku University

New Industry Creation Hatchery Center (NICHe)

6-6-10 Aza-Aoba, Aramaki

Sendai 980-8579

Japan

Philip Garrou

Microelectronic Consultants of North Carolina

3021 Cornwallis Road

Research Triangle Park, NC 27709

USA

Pierric Gueguen

CEA/LETI

Department of Heterogeneous Integration on Silicon

17, rue des Martyrs

38054 Grenoble CEDEX 9

France

Wei Guo

IMEF

Kapeldreef 75

3001 Leuven

Belgium

Mitsuru Hiroshima

Panasonic Factory Solutions Co., Ltd.

2-7 Matsuba-cho, Kadoma

Osaka 571-8502

Japan

Marc B. Hoppenbrouwers

Dutch Organization of Applied Scientific Research (TNO)

5600 HE Eindhoven

The Netherlands

Alan Huffman

RTI International

3040 East Cornwallis Road

Post Office Box 12194

Research Triangle Park, NC 27709

USA

Klaus Hummler

SEMATECH

257 Fuller Road

Albany, NY 12203

USA

Hiroaki Ikeda

ASET

1-28-38 Shinkawa, Chuo-ku

Tokyo 104-0033

Japan

Anne Jourdain

IMEF

Kapeldreef 75

3001 Leuven

Belgium

Akihito Kawai

DISCO CORPORATION

13-11 Omori-Kita 2 Chome, Ota-ku

Tokyo 143-8580

Japan

Guido Knippels

Advanced Laser Separation International (ALSI)

Platinawerf 20-G

6641 TL Beuningen

The Netherlands

Mitsumasa Koyanagi

Tohoku University

New Industry Creation Hatchery Center

6-6-10 Aza-Aoba, Aramaki

Sendai 980-8579

Japan

Christof Landesberger

Fraunhofer Research Institution for Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Kangwook Lee

Tohoku University

New Industry Creation Hatchery Center

6-6-10 Aza-Aoba, Aramaki

Sendai 980-8579

Japan

Paul Lindner

E. Thallner GmbH

EV Group

DI-Erich-Thallner-Straße 1

4782 Sankt Florian am Inn

Austria

James J.-Q. Lu

Rensselaer Polytechnic Institute

Department of Electrical, Computer, and Systems Engineering

110 8th St.

Troy, NY 12160

USA

Matthew Lueck

RTI International

3040 East Cornwallis Road

Post Office Box 12194

Research Triangle Park, NC 27709

USA

Dean Malta

RTI International

3040 East Cornwallis Road

Post Office Box 12194

Research Triangle Park, NC 27709

USA

Thorsten Matthias

E. Thallner GmbH

EV Group

DI-Erich-Thallner-Straße 1

4782 Sankt Florian am Inn

Austria

S. Moreau

CEA/LETI

Department of Heterogeneous Integration on Silicon

17, rue des Martyrs

38054 Grenoble CEDEX 9

France

Sebastien Mermoz

CEA/LETI

Department of Heterogeneous Integration on Silicon

17, rue des Martyrs

38054 Grenoble CEDEX 9

France

Mariappan Murugesan

Tohoku University

New Industry Creation Hatchery Center

6-6-10 Aza-Aoba, Aramaki

Sendai 980-8579

Japan

Steve Olson

State University of NY (SUNY) at Albany

College of Nanoscience and Engineering (CNSE)

Albany, NY 12203

USA

Gerrit Oosterhuis

Dutch Organization of Applied

Scientific Research (TNO)

5600 HE Eindhoven

The Netherlands

Shoji Otaka

TOK (Tokyo Ohka Kogya) Co. Ltd.

150 Nakamaruko, Nakahara-ku

Kawasaki 211-0012

Japan

Christoph Paschke

Fraunhofer Research Institution for Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Rajendra D. Pendse

STATS ChipPAC

#05-17/20 Techpoint

10 Ang Mo Kio Street

Singapore 569059

Singapore

Alain Phommahaxay

IMEF

Kapeldreef 75

3001 Leuven

Belgium

Rama Puligadda

Brewer Science

2401 Brewer Drive

Rolla, MO 65401

USA

Sesh Ramaswami

Applied Materials, Inc.

Silcon Systems Group

974 East Arques Avenue

Sunnyvale, CA 94085

USA

Peter Ramm

Fraunhoffer EMFT

Device and 3D Integration

Hansastrasse 27d

80686 Munich

Germany

Fred Roozeboom

Dutch Organization of Applied Scientific Research (TNO)

5600 HE Eindhoven

The Netherlands

Loïc Sanchez

CEA/LETI

Department of Heterogeneous Integration on Silicon

17, rue des Martyrs

38054 Grenoble CEDEX 9

France

Brian Sapp

SEMATECH

257 Fuller Road

Albany, NY 12203

USA

Larry Smith

SEMATECH

257 Fuller Road

Albany, NY 12203

USA

Hans-Peter Spöhrle

Fraunhofer Research Institution for Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Venky Sundaram

Georgia Tech

School of Electrical and Computational Engineering

777 Atlantic Drive NW

Atlanta, GA 3033-0250

USA

Rachid Taibi

CEA/LETI

Department of Heterogeneous Integration on Silicon

17, rue des Martyrs

38054 Grenoble CEDEX 9

France

Tetsu Tanaka

Tohoku University

Graduate School of Biomedical Engineering

6-6-01 Aza-Aoba, Aramaki

Sendai 980-8579

Japan

Rao R. Tummala

Georgia Tech

School of Electrical and Computational Engineering

777 Atlantic Drive NW

Atlanta, GA 3033-0250

USA

Victor H. Vartanian

SEMATECH

257 Fuller Road

Albany, NY 12203

USA

Richard Webb

3M Electronics Markets Materials

Building 225-3S-06

St. Paul, MN 55144-1000

USA

Josef Weber

Fraunhofer Research Institution for Modular Solid State Technology EMFT

Hansastrasse 27d

80686 Munich

Germany

Markus Wimplinger

E. Thallner GmbH

EV Group

DI-Erich-Thallner-Straße 1

4782 Sankt Florian am Inn

Austria

Douglas C.H. Yu

TSMC

No.8, Li-Hsin Rd. Vl, Science Park

Hsinchu

Taiwan 300-78

P. R. China

Dingyou Zhang

Rensselaer Polytechnic Institute

Department of Electrical, Computer and Systems Engineering

110 8th St.

Troy, NY 12160

USA

13D IC Integration Since 2008

Philip Garrou, Peter Ramm, and Mitsumasa Koyanagi

In Volume 1, we covered some of the history of the development of the 3D integrated circuit (3D IC) concept and we direct you to that chapter for such content [1].

Since the first two volumes of the Handbook of 3D Integration appeared in 2008, significant progress has been made to bring 3D IC technology to commercialization. This chapter will attempt to summarize some of the key developments during that period.

We previously described 3D IC integration as “an emerging, system level integration architecture wherein multiple strata (layers) of planar devices are stacked and interconnected using through-silicon (or other semiconductor material) vias (TSV) in the Z direction” as depicted schematically in Figure 1.1a and in cross section in Figure 1.1b [1].

Figure 1.1 3D IC with TSV: (a) schematic (courtesy of IMEC) and (b) cross section (courtesy of IBM). Note that the IBM cross section is connected at a higher (fatter) on chip interconnect level.

With the continued pressure to miniaturize portable products and the near universal agreement that scaling as we have known it is soon coming to an end [2], a perfect storm has been created. The response to this dilemma at both the device and the package level has been to move into the third dimension.

It is commonly accepted that chip stacks wire-bonded down to a common laminate base and stacked packages such as package-on-package (PoP) are categorized as “3D packaging.” Transistor design has also gone vertical [3] as Intel [4] and others move to “finfet” stacked transistor structures at the 22 nm generation. These are compared pictorially in Figure 1.2.

Figure 1.2 3D packaging, 3D finfet transistors, and 3D IC integration.

In Figure 1.3, we compare system-on-chip (SoC), 3D packaging, and 3D IC with through-silicon via (TSV) in various performance categories [5].

Figure 1.3 Comparison of SoC, 3D packaging, and 3D IC [5].

1.1 3D IC Nomenclature

Since 2008 there have been attempts to further refine the nomenclature for 3D IC integration, although it has not yet been universally adopted in publications. In 2009 the International Technology Roadmap for Semiconductors (ITRS) proposed the following nomenclature in an attempt to define the possible different levels of connections possible as circuits are deconstructed onto separate strata (see Table 1.1) [6].

Table 1.1 2009 ITRS roadmap [6]

Level

Suggested name

Supply chain

Key characteristics

Package

3D packaging (3D-P)

OSAT assembly printed circuit board (PCB)

Traditional packaging of interconnect technologies, for example, wire-bonded die stacks, package-on-package stacks

Also includes die in PCB integration

No through-Si vias

Bond-pad

3D wafer-level package (3D-WLP)

Wafer-level packaging

WLP infrastructure, such as RDL and bumping

3D interconnects are processed after the IC fabrication, “post IC passivation” (via-last process). Connections on bond-pad level

TSV density requirements follow bond-pad density roadmaps

Global

3D stacked integrated circuit/3D system-on-chip (3D-SIC/3D-SoC)

Wafer fab

Stacking of large circuit blocks (tiles, IP blocks, memory banks), similar to an SoC approach but having circuits physically on different layers

Unbuffered I/O drivers (low C, little or no ISD protection on TSVs)

TSV density requirement significantly higher than 3D-WLP: Pitch requirement down to 4–16 μm

Intermediate

3D-SIC

Wafer fab

Stacking of smaller circuit blocks, parts of IP blocks stacked in vertical dimensions

Mainly wafer-to-wafer stacking

TSV density requirements very high: Pitch requirement down to 1–4 μm

Local

3D IC

Wafer fab

Sticking of transistor layers

Common back-end-of-line (BEOL) interconnect stack on multiple layers of front-end-of-line (FEOL)

Requires 3D connections at the density level of local interconnects

1.2 Process Standardization

3D IC requires three new pieces of technology: (1) insulated conductive vias through a thinned silicon substrate (i.e., TSV); (2) thinning and handling technology for wafers as thin as 50 μm or less; (3) technology to assemble and package such thinned chips.

In the mid-2000s, practitioners were bewildered by the multitude of proposed technical routes to 3D IC. It has become clear, since then, that for most applications, the preferred process flow is what has been called a “via-middle” approach, where the TSVs are inserted after front-end transistor formation and early on during the on-chip interconnect process flow. This requires that TSVs are manufactured in back end of fab, not during or after the assembly process. This requires that TSV fabrication will be done by vertically integrated IDMs or foundries. TSV technology appears to be stabilized as depicted in Figure 1.4 and Table 1.2.

Figure 1.4 Standard 3D IC process flow. Courtesy of Yole Developpement.

Table 1.2 Standard 3D IC process flow options

Process

Preferred option

Alternative options available

TSV formation

Bosch deep reactive ion etching (DRIE)

Laser

TSV Insulation

SiO

2

Polymer

Conductor

Cu

W

pSi

Process flow

Via-middle

Via-last (backside)

a)

Via-first (for pSi)

Via-last (front side)

Stacking

Bonding

IMC

Cu–Cu

Oxide bonding

Polymer bonding

Hybrid bonding (oxide–metal or polymer–metal)

Thin wafer handling

On carrier

On stack

a)

Preferred flow for CMOS image sensors.

1.3 The Introduction of Interposers (2.5D)

Many believe the introduction of interposers (also known as 2.5D) was due to the failure of 3D IC, but this is not the case. Interposers were and are needed due to the lack of chip interface standardization and the need for a better thermal solution than is currently available for some 3D stacking situations.

The term “2.5D” is usually credited to Ho Ming Tong from Advanced Semiconductor Engineering (ASE), who in 2009 (or even earlier) declared that we might need an intermediate step toward 3D since the infrastructure and standards were not ready yet. The silicon interposer, Tong felt, would get us a major part of the way there, and could be ready sooner than 3D technology, thus the term “2.5D,” which immediately caught on with other practitioners [7].

2.5D interposers resemble silicon multichip module technology of the 1990s, with the addition of TSV [8]. In today's applications, they provide high-density redistribution layers (RDLs), so the chips can be connected either through the interposer or next to each other on the top surface of the interposer as shown in Figure 1.5. The latter is the superior thermal solution since all chips can be attached to a heat sink for cooling.

Figure 1.5 Interposer configurations.

Interposers will add cost and probably will not be a broadly accepted solution for low-cost mobile products, which would prefer straight 3D stacking [9].

1.4 The Foundries

1.4.1 TSMC

In October 2012, TSMC announced the readiness of their 2.5D CoWoS™ (chip-on-wafer-on-substrate) technology within their “Open Innovation Platform®” and made public their reference flows supporting CoWoS. Several EDA companies including Cadence, Mentor, Synopsys, and Ansys were announced as partners in the CoWoS reference flow [10]. Their first public CoWoS demonstrator vehicle (Figure 1.6) included logic and DRAM in a single module using the wide I/O interface [11].

Figure 1.6 2.5D TSMC demonstrator vehicle [11].

Early TSMC customers reportedly included Xilinx, AMD, Nvidia, Qualcomm, Texas Instruments, Marvell, and Altera [12], with Xilinx being the first to production in late 2011.

Reportedly due to “…the numerous technical challenges that make the conventional collaboration infrastructure more difficult” for 2.5 and 3D IC, TSMC has taken the position of being responsible for the full process (chip design and fabrication through module test).

1.4.2 UMC

UMC announced in the spring of 2011 that it had acquired production equipment for TSV and other 3D IC technologies. In 2013 UMC and STATS ChipPAC announced a jointly developed TSV-enabled 3D IC chip stack consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28 nm processor test chip [13].

1.4.3 GlobalFoundries

GlobalFoundries (GF) announced installation of TSV production tools for 20 nm technology wafers in their Fab 8 New York facility. The first full-flow silicon with TSVs was expected to start running in the third quarter of 2012 [14].

In contrast to TSMC, which announced a one-stop-shop turnkey line that included all of the assembly and test steps traditionally handled by outsourced semiconductor assembly and test (OSAT) facilities, UMC and GlobalFoundries indicated a preference to work under the open ecosystem model where they would handle TSV fabrication (Cu, via-middle) and other front-end steps while chips from various vendors would be back-end processed (i.e., temporary bonding/debonding, thinning, assembly, and test by their OSAT partners).

1.5 Memory

DRAM performance is constrained by the capacity of the data channel that sits between the memory and the processor. No matter how much faster the DRAM chip itself gets, the channel typically chokes due to the lack of transfer capacity; that is, they require more bandwidth. Wide I/O memory has been developed as the solution to this bandwidth problem [15].

Also, as more and more memory is required for a given application, power consumption also becomes important to both portable products and server farms, which need special cooling to keep them from overheating. Samsung reports that TSV-based RDIMM shows a 32% decrease in power consumption versus LRDIMM at 1333 Mbps [16].

1.5.1 Samsung

In late 2010, Samsung, who first revealed 3D TSV stacked memory prototypes in 2006, announced 40 nm, 8 GB RDIMM based on 4 Gb, 1.5 V, 40 nm DDR3 memory chips operating at 1333 MHz and 3D TSV chip-stacking technology [17]. In 2011, they announced the development of wide I/O 1 Gb DRAM (Figure 1.7) [18]. Samsung has not announced any commercial memory products as of late 2013. Samsung is a member of the Micron hybrid memory cube consortium.

Figure 1.7 1.2 V 12.8 GB s−1 2 Gb mobile wide I/O DRAM with 4 × 128 I/Os using TSV-based stacking [18].

1.5.2 Micron

Micron developed a “hybrid memory cube” (HMC), which is a stack of multiple thinned memory dies sitting atop a logic chip bonded together using TSV (Figure 1.8). This greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs. The controller layer in the HMC allows a higher speed bus from the controller chip to the CPU and the thinned and TSV connected memory layers mean memory can be packed more densely in a given volume. The HMC requires about 10% of the volume of a DDR3 memory module. It is claimed that the technology provides 15× the performance of a DDR3 module, uses 70% less energy per bit than DDR3, and occupies 90% less space than today's RDIMMs. Micron has announced that they will be manufacturing the memory layers and have contracted IBM to manufacture the logic layer. Commercialization is scheduled for 2013–2014.

Figure 1.8 Micron hybrid memory cube (HMC) [19].

HMC electrical performance is compared to other DRAM modules in Table 1.3.

Table 1.3 Comparison of Micron HMC to DDR memories [20]

Technology

VDD

BW (Gb s

−1

)

Power (W)

SDRAM PC133 1 Gb module

3.3

1.06

4.96

DDR-333 1 Gb module

2.5

2.66

5.48

DDR2-667 2 Gb module

1.8

5.34

5.18

DDR3-1333 2 Gb module

1.5

10.66

5.52

DDR4-2667 4 Gb module

1.2

21.34

6.60

HMC Gen 1 512 Mb cube

1.2

128.0

10.73

1.5.3 Hynix

Hynix reported that they expect “2 and 4 chip memory stacks with TSV to be in commercial production in 2014 and graphics solutions on interposers soon thereafter” [21].

1.6 The Assembly and Test Houses

Amkor was involved with commercial 3D IC assembly as part of their TSMC Xilinx program [22]. ASE, SPIL, and Powertech are all boosting 3D IC package and test capacity. SPIL (Siliconware) announced the instillation of dual damascene processing for high density interposers in 2013 [23]. Powertech, which has been in a 3D IC joint development program with Elpida (now Micron) and UMC for several years, announced volume production of 3D IC packaging and test capability in 2013.

1.7 3D IC Application Roadmaps

The first commercial application has been field-programmable gate arrays (FPGAs) with Xilinx (commercial) [22] and Altera (developing) [24] interposer-based solutions with TSMC.

Looking at the roadmap of GlobalFoundries in Figure 1.9, we see that 2.5D graphics processor modules and 3D application processors with baseband and/or memory should be coming soon.

Figure 1.9 3D IC application timing.Courtesy of GlobalFoundries 2012.

The latest projections by Yole Developpement are shown in Figures 1.10 and 1.11. 3D IC volume is expected to increase to nearly 10 MM wafers over the next 4 years with major increases in stacked memory, wide I/O DRAM, and logic plus memory system-in-packages (SiPs).

Figure 1.10 TSV chip wafer forecast 2010–2017.Courtesy of Yole Developpement.

Figure 1.11 Global TSV chip end applications in 2017.Courtesy of Yole Developpement.

Examining 2.5/3D device product insertion, we see that most of these devices will eventually be incorporated in the smartphone and tablet markets.

References

1.

Garrou, P. (2008)

Chapter 1

: Introduction to 3D integration, in

Handbook of 3D Integration

, vol.

1

(eds. P. Garrou, C. Bower, and P. Ramm), Wiley-VCH Verlag GmbH, Weinheim.

2.

Heron, N.Z. (2008) Why is CMOS scaling coming to an end. 3rd International Design & Test Workshop, pp. 98–103.

3.

Adee, S. (2007) Transistors go vertical.

IEEE Spectrum

,

44

, 14.

4.

James, D. (2012) Intel Ivy Bridge unveiled the first commercial tri-gate, high-k, metalgate CPU. IEEE Custom Integrated Circuit Conference, p. 1.

5.

Garrou, P. (2011) 3D integration – are we there yet. Suss MicroTech Workshop, Semicon 2011. [6]Interconnect (2009) International Technology Roadmap for Semiconductors. Available at

www.itrs.net/links/2009ITRS/2009Chapters_2009Tables/2009_Interconnect.pdf

(accessed December 31, 2013).

7.

Garrou, P. (2012) 3.5D interposers to someday replace PWBs – TSMC; GF engaging with 3D customers; Intel predicts Consolidation.

Solid State Technology: Insights from the Leading Edge

,

102

, May 19, 2012.

8.

Garrou, P. and Turlik, I. (1998)

Multichip Module Handbook

, McGraw-Hill.

9.

Garrou, P. (2013) Interposer supply/ecosystem examined at IMAPS Device Packaging Conference. Available at

www.electroiq.com/articles/ap/2012/03/interposer-supply-ecosystem-examined-atimaps-device-packaging.html

(accessed December 31, 2013).

10.

Garrou, P. (2012) TSMC officially ready for 2.5D, Apple order impact on TSMC.

Solid State Technology: Insights from the Leading Edge

,

122

, November 11, 2012. Available at

http://electroiq.com/insights-from-leading-edge/2012/11/iftle-122-tsmc-officially-ready-for-2-5d-apple-order-impact-on-tsmc/

(accessed December 31, 2013).

11.

EDA 360 Insider (2012) 3D Thursday: want to see a closeup of the TSMC 3D IC test vehicle? June 6, 2012. Available at

http://eda360insider.wordpress.com/2012/06/06/3d-thursday-want-to-see-a-closeup-of-the-tsmc-3d-ic-test-vehicle/

(accessed December 31, 2013).

12.

Liu, K. (2012) TSC builds up 3DIC assembling capability to vie for lucrative business.

Taiwan Economic News

, August 14, 2012. Available at

http://news.cens.com/cens/html/en/news/news_inner_40986.html

(accessed December 31, 2013).

13.

Garrou, P. (2013) UMC/SCP memory on logic; SEMI Europe 3D Summit Part 2.

Solid State Technology: Insights from the Leading Edge

,

135

, February 12, 2013. Available at

http://electroiq.com/insights-from-leading-edge/2013/02/iftle-135-umc-scp-memory-on-logic-semi-europe-3d-summit-part-2/

(accessed December 31, 2013).

14.

Garrou, P. (2013) GlobalFoundries 2.5/3D at 20 nm; Intel Haswell GT3; UMC/SCP prototype details.

Solid State Technology: Insights from the Leading Edge

,

142

, April 9, 2013. Available at

http://electroiq.com/insights-from-leading-edge/2013/04/iftle-142-globalfoundries-2-5-3d-at-20nm-intel-haswell-gt3-umc-scp-prototype-details/

(accessed December 31, 2013).

15.

JEDEC (2012) JEDEC publishes breakthrough standard for wide I/O mobile DRAM. Available at

http://www.jedec.org/news/pressreleases/jedec-publishes-breakthrough-standard-wide-io-mobile-dram

(accessed December 31, 2013).

16.

Schauss, G. (2011) Samsung memory solution for HPC. Available at

http://www.ena-hpc.org/2011/talks/schauss-slides.pdf

(accessed December 31, 2013).

17.

Kang, U. (2009) 8 Gb DDR3 DRAM using TSV technology.

IEEE ISSCC

.

18.

Kim, J.S. (2011) A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4_128 I/O's using TSV-based stacking.

IEEE ISSCC

.

19.

Jeddeloh, J. and Keeth, B. (2012) New DRAM architecture increases density and performance. 2012 Symposium on VLSI Technology, p. 87.

20.

Pawlowski, J.T. (2011) Hybrid memory cube: breakthrough DRAM performance with a fundamentally re-architected DRAM subsystem. Proceedings of the 23rd Hot Chips Symposium.

21.

Suh, M. (2013) TSV application in memory devices. RTI 3D Architectures for Semiconductor Integration and Packaging Conference, Burlingame CA, December 2013.

22.

Saban, K. (2010) Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Available at

//www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf

(accessed December 31, 2013).

23.

Ma, M. (2013) The expanding role of OSATS in the era of system integration. ConFab 2013, Las Vegas, NV.

24.

Rahman, A.

et al.

(2013) Application requirements of system-in-package FPGAs. RTI 3D Architectures for Semiconductor Integration and Packaging Conference, Burlingame, CA, December 2013.

2Key Applications and Market Trends for 3D Integration and Interposer Technologies

Rozalia Beica, Jean-Christophe Eloy, and Peter Ramm

2.1 Introduction

Improvements in microprocessors and memory devices, through scaling of CMOS technologies have, for more than four decades, consistently followed Moore's law. While miniaturization is expected to continue, the benefits achieved through scaling, in terms of functionality, performance, and cost, are starting to weaken. Corresponding shrinking of transistors will probably only keep up until 2022 [1]. Fueled by research and developments of new materials and processes (various nanomaterials, carbon nanotubes, graphene, III–V compound semiconductors, and Ge channels), integration and architecture schemes, and so on (Figure 2.1), a growing trend in the industry is seen in moving from CMOS to package and system architecture value-added proposition (see Figure 2.1) [2,3].

Figure 2.1 The taxonomy of emerging research information processing devices. The yellow boxes outlined with red show current CMOS technologies, based on electric charge and binary computational state variables; the remaining boxes are innovative technologies and ideas under development to continue to support further miniaturization and scaling [3]. Courtesy of ITRS.

For example, in the case of system-on-chip (SoC), which is a platform for horizontal integration of various devices (memory, logic, analog/RF), increased performance is achieved through CMOS technology and transistor miniaturization. All the devices integrated in SoC have to be manufactured using the same technology node that results in unnecessary increased costs. Horizontal integration also increases the total surface area of the system, increasing the form factor and added costs associated with the increase of the silicon surface (Figure 2.2).

Figure 2.2 2D SoC and 3D IC comparison [4]. Courtesy of Yole Developpement.

As shown in Figure 2.2, system-in-package (SiP) architectures, in comparison to 2D SoC, bring several advantages, including reduced cost, increased performance, and smaller size. SiP and 3D ICs are achieving value from the various functions vertically integrated within the same package and their value proposition is not limited to CMOS scaling. There is no need for the devices package in a SiP to use the same CMOS technology nodes, rather each device (either being a memory, logic, analog, MEMS, passive component, etc.) is manufactured using optimum technology for the particular function it brings to the package. SiP and vertical integration enables heterogeneous integration of disparate technologies (digital and nondigital) reusing already proven and reliable technologies and designs from existing products, thus giving significant advantage over SoC-type integration. 3D IC integration, benefiting by the stacking of known good dies [5], can combine various functions on different lithography nodes, devices processed on different wafer sizes, and in different wafer fabs by different players in the industry.

This functional diversification, based on 3D integration, is known as “More than Moore” (MtM) (Figure 2.3).

Figure 2.3 3D integration – enabling miniaturization and diversification [4]. Courtesy of Yole Developpement.

2.2 Advanced Packaging Importance in the Semiconductor Industry is Growing

As the semiconductor industry moves toward the systematic integration of stacked heterogeneous chips, 3D integration is expanding its reach in advanced packaging. 3D stacking includes chip-level, device-level, and wafer-level approaches.

One may ask, “Why package?” Packaging is done for speed, power, cost, and size advantages. Advanced packaging is transitioning to high-performance, high-density, low-cost collective wafer-level packaging techniques.

Several platforms have been developed in advanced packaging. For the past 40 years, the semiconductor packaging industry has continuously worked on developing new technologies and platforms to bridge the increasing I/O interconnect gap between the quickly decreasing silicon geometries (driven by Moore's law) and the slower speed at which the printed circuit geometries are shrinking (Figure 2.4).

Figure 2.4 I/O interconnect gap between CMOS transistors and printed circuit board (PCB) features [4]. Courtesy of Yole Developpement.

This created opportunities for several packaging technologies to be developed over the years. Looking back at the major developments every 10 years, we can see a large variety of different technologies developed, from through-hole technology in the 1970s; surface mount devices (SMDs) in the 1980s; chip-scale packaging (CSP), ball grid arrays (BGAs), and SiPs in the 1990s; wafer-level chip-scale packaging (WLCSP), flip-chip BGAs, and more SiPs and package-on-packages (PoPs) developed around 2000; and more recently, 3D IC and through-silicon vias (TSVs), fan-out WLCSPs, Cu pillars, microbumping, silicon interposers, and embedded technologies. Advanced packaging is like a flower that bloomed over the years into a multicolor array of pastels. Many of these technologies, although developed several decades ago, are still available today and successfully supporting various packaging platforms.

Advanced packaging, especially wafer-level packaging, technologies are gaining more significance and importance within the semiconductor industry. They have the potential for notable growth in this industry. In 2012, 13 million wafers, which is approximately 16% of semiconductor IC wafers, were manufactured using various packaging technologies such as bumping, redistribution layers (RDLs), and TSV interconnect technologies. By 2017, the growth of advanced packaging is forecasted to reach approximately 23% penetration rate; that means 35 million wafers (in 300 mm equivalent wafers) out of the forecasted 148 million IC wafers will be using packaging technologies. The advanced packaging industry is growing significantly, outpacing the growth expected of the total semiconductor industry. With a 21% compound annual growth rate (CAGR), the advanced packaging industry is growing twice as fast as the semiconductor industry, which is forecasted to have a 10% CAGR (as illustrated in Figure 2.5).

Figure 2.5 Wafer-level packaging in the semiconductor IC processing industry [4]. Courtesy of Yole Developpement.

2.3 3D Integration-Focused Activities – The Global IP Landscape

3D integration not only will bring diversification, but will also continue to drive the evolution of packages for several decades to come. Therefore, today 3D integration is considered a new paradigm for the semiconductor industry. There are various ways of vertically packaging devices, but the latest and most advanced technology for 3D stacking is TSV technology. Within wafer-level packaging, the platforms using TSV vertical interconnects are 3D WLCSPs, 2.5D interposers, and 3D ICs (Figure 2.6).

Figure 2.6 Wafer-level packaging technologies using TSV vertical interconnects [4]. Courtesy of Yole Developpement.

3D integration is not a new concept. A recent IP landscape analysis performed by Yole Developpement, focusing on 3D ICs and 2.5D interposers, revealed 1969 as the year when the first 3D patent was applied. That IBM was the first assignee of this patent should not surprise anyone. The majority (82%) of the patents in this area were actually filed starting with 2006 (as shown in Figure 2.7).

Figure 2.7 Trend of patent filing for 3D IC [6]. Courtesy of Yole Developpement.

A total of 1013 patent families were filed between 1969 and 2012. The United States (56%) followed by Korea (18%) were found to be the priority countries with the highest number of patents. The United States, China, Korea, Taiwan, and Japan, as illustrated in Figure 2.8, are the main countries where patents, once filed, are extended.

Figure 2.8 Geographical distribution of patent filing for 3D IC technology [6]. Courtesy of Yole Developpement.

Even though the first patent was filed more than 40 years ago, for 30 years there was almost no activity in this domain. 3D IC is still a relatively young technology, also reflected by the high number of pending patents in this domain. As illustrated in Figure 2.9, by the end of 2012, only 39% of the patents were granted and almost half (45%) are still pending.

Figure 2.9 Legal status of 3D IC patents [6]. Courtesy of Yole Developpement.

There were 260 players found to be involved with 3D IC. The top 10 (Figure 2.10) assignees represent 48% of the patents filed in 3D IC domain. IBM leads with respect to the number of patents filed, followed by Samsung, Micron, Taiwan Semiconductor Manufacturing Company (TSMC), SK Hynix, STATS ChipPac Ltd., Intel, Amkor, Elpida Memory, and Industrial Technology Research Institute (ITRI).

Figure 2.10 Top 10 patent assignees for 3D IC [6]. Courtesy of Yole Developpement.

3D IC IP activities were found across different academic institutions with ITRI being the top institute with 21 patents, followed by CEA-Leti (France), Fraunhofer-Gesellschaft München (Germany), KAIST (Korea), IMEC (Belgium), University of Beijing (China), ASTRI (Hong Kong), University Tsinghua (China), Chinese Academy of Science (China), and ETRI (Korea). The top 10 academic assignees represent over 11% of the total 3D IC filed patents (Figure 2.11).

Figure 2.11 Top academic assignees for 3D IC patents [6]. Courtesy of Yole Developpement.

A more in-depth analysis of the patents with respect to processing showed TSV isolation, filling, bonding and debonding, and barrier and seed deposition to be the processing steps most patented. IBM, for example, initially focusing on using TSV for power amplifiers, has spent a lot of effort in trying to improve the electrical performance, especially at high frequencies; therefore, a large number of its patents (32%) were filed on the TSV isolation step. At IBM alone, there were more than 150 inventors and 200 patents found related to 3D IC technology.

In conclusion, the United States was the early player, increasingly involved in 3D IC since 1969, but new players, such as China and Korea, have entered the industry since 2005. If IBM and Micron (both US companies) are the main assignees and still active, SK Hynix (Korea) and STATS ChipPac Ltd. (Singapore) emerged as new players during the last 5 years.

2.4 Applications, Technology, and Market Trends

Several applications (Figure 2.12) have been identified where 3D TSV integration can be beneficial, in terms of performance, miniaturization, cost, or functionality.

Figure 2.12 Six applications using 3D TSVs [6].

Prior to 2012, we had mainly three applications using 3D IC and TSV technology, most of them processed on 150 mm type wafers:

CMOS image sensors (CISs) with front-side imagers packaged in 3D WLCSP and backside imagers (BSIs) with TSV.

The main drivers for CIS are increased performance and integration:

- The BSI “backside illuminated” image sensor continues to be a very hot product today. BSI is expected to increase image sensor performance (low light sensitivity) while relaxing back-end-of-line (BEOL) design requirements as the photodiodes will be at the top side of the CIS design.

- It will also enable 3D integration with the possibility of having “more intelligence per pixel” for higher sensing performance and management of the information at the pixel level, for recognition capability features, automotive sensors (safety and security applications), and gaming applications (human body/sensor interface with the computer).

High-end BSI sensors are already in production at Sony (Japan), and mostly dedicated to DSC and DSLR video cameras. BSIs are also expected to progressively replace CCDs in high-end applications. Other players include Omnivision, Panasonic, Aptina Imaging Corporation, and Samsung (Figure 2.13). Consumer BSI sensors (driven by cellphone applications) penetrated the market in 2011 on 1.1 μm pixel generation sensors (see Figure 2.20; top track).

Mobile phones and tablets will be driving future innovation in imaging. Of the imaging and optoelectronic 3D devices that will be shipped in 2017, 77% are forecasted to be integrated in mobile phones and tablets.

MEMS applications

: accelerometers and gyroscopes, fingerprint sensors, pressure sensors (TPMS, gas, etc.), RF-MEMS (FBAR, resonators, switches), microfluidics (microvalves, POC, etc.), microprobes, and optical MEMS (micromirrors, IR bolometers).

The driving forces for adopting TSVs in MEMS are form factor, cost, and integration:

- MEMS and sensor package costs are relatively high (often 40–60% of the overall cost) in addition to the large size of the package.

- Some sensor modules are becoming quite complex (TPMS and IMU modules), driving the need for a higher level of integration.

3D integration of TSVs has become a reality in MEMS and sensor applications. Avago is in production for their FBAR filters and VTI and ST Microelectronics are in production for MEMS inertial sensors (accelerometers and gyroscopes). Other applications are entering the market (silicon microphones from Sonion, fingerprint sensors from IDEX Corporation, and more) and a high level of activity is currently running on 150 mm in MEMS foundries such as Silex, Teledyne Dalsa, Touch Microsystems Technology, Innovative Micro Technology (IMT) MEMS, but 200 mm facilities are ramping up. There is also a high interest from giant CMOS foundry players (TSMC, UMC, Chartered, Semiconductor Manufacturing International Corporation (SMIC)); they have the ability to recycle their aging 200 mm fabs, since they are already deeply involved in the MEMS ASIC business. With respect to IDMs, ST, Bosch, TI, Avago, Omron, and others are also very active (Figure 2.14).

RF and power, analog, and mixed signal power applications

: IGBT, MOSFET for medical and automotive electronics, high performance MMIC components, and DC/DC converters. Examples are illustrated in

Figure 2.15

.

The main motivation for TSVs for these applications are cost, form factor, and performance.

-

Power applications

: With 3D integration, the wire bonding can be replaced with “ground” TSVs, preventing arcing effects by placing all the electrical connections on the backside of the device, reducing packaging size, and increasing reliability.

- Integrated SiPs operating at high power often incorporate high-power vertical components such as IGBT and MOSFETs.

- Power “GaN on sapphire” and “GaN on silicon” components benefit from TSV packages in terms of performance because wire bonding is not able to provide the performance requirements for the interconnects. IR, TI, Maxim, ST Microelectronics, and Panasonic are developing such types of components.

-

3D integrated passive devices

(

IPDs

) : IPDs offer a wide range of system architecture and partitioning opportunities as well as cost reduction because the 3D IPDs can be manufactured at wafer level as well. Miniaturization is also enabled through 3D integration because the size of the IPD is no longer constrained by the size of the package substrate. Due to shorter connections between the passive and the active components, and the external interface, the level of parasitics is also significantly reduced.

-

Analog ICs

: The use of TSVs is a performance enabler for high-speed analog devices, reducing the bond length for critical nodes; the length of the connections to the chip's bond pad can be reduced from millimeters to microns.

The mobile phone industry is the primary driver for using RF and analog 3D integrated devices and will continue to drive the growth of such packages in the future. By 2017, it will still be the main application by far, followed by electrical and hybrid vehicles with power devices such as IGBT with TSV (ground via).

Figure 2.13 TSV/WLP reality in high-end, BSI CMOS image sensors from Samsung, Sony, Omnivision, and Toshiba [6]. Courtesy of Omnivision, SystemPlus Consulting, and Chipworks.

Figure 2.14 ST Microelectronics accelerometer with TSV in MEMS IC introduced in 2011 in a Nokia mobile phone. The TSV in this package was isolated from the MEMS with an air gap [6]. Courtesy of SystemPlus Consulting.

Figure 2.15 3D power/RF/analog passive interposers – 3D IPD at Infineon [6]. Courtesy of Infineon Technologies.

Newer activities in the industry are integration of 2.5D interposers and TSV technology in high-end applications. Large-die field-programmable gate array (FPGA) devices and ASICs have been commercialized; Xilinx has taken the lead with their first shipment targeting network applications such as smart TVs and set-top boxes. 2.5D glass/silicon interposers have actually emerged as key substrate elements for connecting the nanometer to millimeter worlds in future semiconductor chip packaging assembly (Figure 2.16).

Figure 2.16 2.5D interposer – key enabler for connecting the nanometer to millimeter worlds [6].

2.5D interposers are viewed as the first generation of 3D ICs. To further reduce costs, many companies are considering alternatives to silicon interposers, such as glass interposers.

A large driver for using 2.5D interposers is system partitioning and ability to integrate at least one logic IC with one or several memory ICs and even mixed signal or analog ICs. It involves “four slices” instead of a single-die 3D SoC repartitioned logic design. This increases CMOS manufacturing yield because of the smaller die size and high-density wiring at the surface of the four-layer copper damascene silicon interposer wafer – leading to a breakthrough in cost versus power consumption versus performance. This type of packaging is expected to progressively replace monolithic SoCs. As illustrated in