Handbook of Wafer Bonding E-Book

• Herausgeber: Wiley-VCH
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 665

Veröffentlichungsjahr: 2011

Beschreibung

The focus behind this book on wafer bonding is the fast paced changes in the research and development in three-dimensional (3D) integration, temporary bonding and micro-electro-mechanical systems (MEMS) with new functional layers. Written by authors and edited by a team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.

Part I sorts the wafer bonding technologies into four categories: Adhesive and Anodic Bonding; Direct Wafer Bonding; Metal Bonding; and Hybrid Metal/Dielectric Bonding. Part II summarizes the key wafer bonding applications developed recently, that is, 3D integration, MEMS, and temporary bonding, to give readers a taste of the significant applications of wafer bonding technologies.

This book is aimed at materials scientists, semiconductor physicists, the semiconductor industry, IT engineers, electrical engineers, and libraries.

Leseprobe

Table of Contents

Cover

Related Titles

Title page

Copyright page

Preface

Obituary

List of Contributors

Introduction

Technologies

Applications

Definitions

Conclusions

Part One: Technologies

A. Adhesive and Anodic Bonding

1 Glass Frit Wafer Bonding

1.1 Principle of Glass Frit Bonding

1.2 Glass Frit Materials

1.3 Screen Printing: Process for Bringing Glass Frit Material onto Wafers

1.4 Thermal Conditioning: Process for Transforming Printed Paste into Glass for Bonding

1.5 Wafer Bond Process: Essential Wafer-to-Wafer Mounting by a Glass Frit Interlayer

1.6 Characterization of Glass Frit Bonds

1.7 Applications of Glass Frit Wafer Bonding

1.8 Conclusions

2 Wafer Bonding Using Spin-On Glass as Bonding Material

2.1 Spin-On Glass Materials

2.2 Wafer Bonding with SOG Layers

3 Polymer Adhesive Wafer Bonding

3.1 Introduction

3.2 Polymer Adhesives

3.3 Polymer Adhesive Wafer Bonding Technology

3.4 Wafer-to-Wafer Alignment in Polymer Adhesive Wafer Bonding

3.5 Examples for Polymer Adhesive Wafer Bonding Processes and Programs

3.6 Summary and Conclusions

4 Anodic Bonding

4.1 Introduction

4.2 Mechanism of Anodic Bonding

4.3 Bonding Current

4.4 Glasses for Anodic Bonding

4.5 Characterization of Bond Quality

4.6 Pressure Inside Vacuum-Sealed Cavities

4.7 Effect of Anodic Bonding on Flexible Structures

4.8 Electrical Degradation of Devices during Anodic Bonding

4.9 Bonding with Thin Films

4.10 Conclusions

B. Direct Wafer Bonding

5 Direct Wafer Bonding

5.1 Introduction

5.2 Surface Chemistry and Physics

5.3 Wafer Bonding Techniques

5.4 Properties of Bonded Interfaces

5.5 Applications of Wafer Bonding

5.6 Conclusions

6 Plasma-Activated Bonding

6.1 Introduction

6.2 Theory

6.3 Classification of PAB

6.4 Procedure of PAB

6.5 Applications for PAB

6.6 Conclusion

C. Metal Bonding

7 Au/Sn Solder

7.1 Introduction

7.2 Au/Sn Solder Alloy

7.3 Reflow Soldering

7.4 Thermode Soldering

7.5 Aspects of Three-Dimensional Integration and Wafer-Level Assembly

7.6 Summary and Conclusions

8 Eutectic Au–In Bonding

8.1 Introduction

8.2 Organic/Metal Hybrid Bonding

8.3 Organic/In–Au Hybrid Bonding

8.4 Three-Dimensional LSI Test Chips Fabricated by Eutectic In–Au Bonding

8.5 High-Density and Narrow-Pitch Mircobump Technology

8.6 Conclusion

Acknowledgment

9 Thermocompression Cu–Cu Bonding of Blanket and Patterned Wafers

9.1 Introduction

9.2 Classification of the Cu Bonding Technique

9.3 Fundamental Properties of Cu Bonding

9.4 Development of Cu Bonding

9.5 Characterization of Cu Bonding Quality

9.6 Alignment Accuracy of Cu–Cu Bonding

9.7 Reliable Cu Bonding and Multilayer Stacking

9.8 Nonblanket Cu–Cu Bonding

9.9 Low-Temperature (<300 °C) Cu–Cu Bonding

9.10 Applications of Cu Wafer Bonding

9.11 Summary

10 Wafer-Level Solid–Liquid Interdiffusion Bonding

10.1 Background

10.2 Cu–Sn SLID Bonding

10.3 Au–Sn SLID Bonding

10.4 Application of SLID Bonding

10.5 Integrity of SLID Bonding

10.6 Summary

D. Hybrid Metal/Dielectric Bonding

11 Hybrid Metal/Polymer Wafer Bonding Platform

11.1 Introduction

11.2 Three-Dimensional Platform Using Hybrid Cu/BCB Bonding

11.3 Baseline Bonding Process for Hybrid Cu/BCB Bonding Platform

11.4 Evaluation of Cu/BCB Hybrid Bonding Processing Issues

11.5 Summary and Conclusions

Acknowledgments

12 Cu/SiO2 Hybrid Bonding

12.1 Introduction

12.2 Blanket Cu/SiO2 Direct Bonding Principle

12.3 Blanket Copper Direct Bonding Principle

12.4 Electrical Characterization

12.5 Die-to-Wafer Bonding

12.6 Conclusion

Acknowledgment

13 Metal/Silicon Oxide Hybrid Bonding

13.1 Introduction

13.2 Metal/Non-adhesive Hybrid Bonding – Metal DBI®

13.3 Metal/Silicon Oxide DBI®

13.4 Metal/Silicon Nitride DBI®

13.5 Metal/Silicon Oxide DBI® Hybrid Bonding Applications

13.6 Summary

Part Two: Applications

14 Microelectromechanical Systems

14.1 Introduction

14.2 Wafer Bonding for Encapsulation of MEMS

14.3 Wafer Bonding to Build Advanced MEMS Structures

14.4 Examples of MEMS and Their Requirements for the Bonding Process

14.5 Integration of Some Common Wafer Bonding Processes

14.6 Summary

15 Three-Dimensional Integration

15.1 Definitions

15.2 Application of Wafer Bonding for 3D Integration Technology

15.3 Motivations for Moving to 3D Integration

15.4 Applications of 3D Integration Technology

15.5 Conclusions

16 Temporary Bonding for Enabling Three-Dimensional Integration and Packaging

16.1 Introduction

16.2 Temporary Bonding Technology Options

16.3 Boundary Conditions for Successful Processing

16.4 Three-Dimensional Integration Processes Demonstrated with Thermomechanical Debonding Approach

16.5 Concluding Remarks

Acknowledgments

17 Temporary Adhesive Bonding with Reconfiguration of Known Good Dies for Three-Dimensional Integrated Systems

17.1 Die Assembly with SLID Bonding

17.2 Reconfiguration

17.3 Wafer-to-Wafer Assembly by SLID Bonding

17.4 Reconfiguration with Ultrathin Chips

17.5 Conclusion

Acknowledgments

18 Thin Wafer Support System for above 250 °C Processing and Cold De-bonding

18.1 Introduction

18.2 Process Flow

18.3 Properties

18.4 Applications

18.5 Conclusions

Acknowledgments

19 Temporary Bonding: Electrostatic

19.1 Basic Principles: Electrostatic Forces between Parallel Plates

19.2 Technological Concept for Manufacture of Mobile Electrostatic Carriers

19.3 Characterization of Electrostatic Carriers

19.4 Electrostatic Carriers for Processing of Thin and Flexible Substrates

19.5 Summary and Outlook

Index

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The Editors

Dr. Peter Ramm

Fraunhofer Research Institution for Modular Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Prof. Dr. James Jian-Qiang Lu

Rensellaer Polytechnic Institute

110 8th Street

Troy, NY 12180-3590

USA

Dr. Maaike M.V. Taklo

SINTEF ICT

Gaustadalléen 23 C

0314 Oslo

Norway

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Preface

One may ask if we need another book on wafer bonding. The answer is a clear yes. The research and development on wafer bonding has truly sped up in the last few years, motivated by the extended use of wafer bonding in new technology areas with a variety of materials. It is very desirable to summarize the recent advances in wafer bonding fundamentals, materials, technologies, and applications in a handbook format, rather than just focusing on scientific fundamentals and/or applications.

So far there have been several books and review articles on wafer bonding, such as

Tong, Q.-Y. and Gösele, U. (1999) Semiconductor Wafer Bonding: Science and Technology, John Wiley & Sons, Inc.;Alexe, M. and Gösele, U. (eds) (2004) Wafer Bonding: Applications and Technology, Springer;Plößl, A. and Kräuter, G. (1999) Wafer direct bonding: tailoring adhesion between brittle materials. Materials Science and Engineering, R25, 1–88.

We do need an update. The change is mainly due to the fast pace of research and development in three-dimensional (3D) integration, temporary bonding, and microelectromechanical systems (MEMS) with new functional layers.

Formerly, wafer bonding was applied for manufacturing silicon-on-insulator wafers, for fabrication of sensors and actuators, and for various fluidic systems. Today, manufacturers of IC wafers have also learnt the terminologies related to wafer bonding. As Moore’s law seems to come to an end, or at least to meet some resistance, memory and logic devices are being stacked in the third dimension to increase the density of transistors and improve performance and functionality. IC manufacturers work on larger wafers and produce wafers in huge quantities, so they have truly challenged lately the vendors of wafer bonding tools. Their interest in wafer stacking has resulted in increased alignment precision, tools for larger wafers, an increased focus on new materials, lower cost and higher throughput, etc.

Based on the tremendous progress in wafer bonding in recent years, we invited world experts to contribute chapters to this wafer bonding handbook, covering a variety of technologies and applications. The wafer bonding technologies are presented in Part One. We have grouped them into (i) adhesive and anodic bonding, (ii) direct wafer bonding, (iii) metal bonding, and (iv) hybrid metal/dielectric bonding. Several other possible ways of sorting the technologies are possible, but the sorting approach taken here distinguishes the materials, the approaches, and their possible applications. In Part Two, some key wafer bonding applications are summarized, that is, 3D integration, MEMS, and temporary bonding, to give readers a flavor for where the wafer bonding technologies are significantly applied.

This handbook focuses on wafer-level bonding technologies including chip-to-wafer bonding. However, some of the technologies can also apply to chip-to-chip bonding, probably with some modifications.

Peter Ramm

James Jian-Qiang Lu

Maaike M.V. Taklo

Obituary

In Honor of Ulrich Gösele (1949–2009)

The editors would like to honor Professor Ulrich Gösele for his great contributions to wafer bonding, and are proud to have his chapter on “Direct Wafer Bonding” – his last authored article – in this book.

Ulrich M. Gösele

25 January 1949–8 November 2009

The photo was taken in July 2009 (source: MPI Halle)

Professor Ulrich Gösele passed away on 8 November 2009. His death was unexpected and is a great loss for his family and his many friends and colleagues all over the world.

His research interests covered different areas and were of impact for the science and technology of wafer bonding, diffusion and defects in semiconductors, semiconductor nanoparticles and nanowires, complex oxide films on semiconductors, silicon photonics, photonic crystals, and self-organized nanoscale structures.

Ulrich M. Gösele was born on 25 January 1949, in southern Germany in the city of Stuttgart. He studied physics at the University of Stuttgart and at the Technical University of Berlin and obtained his diploma in 1973. His PhD work was carried out at the University of Stuttgart and at the Max Planck Institute for Metals Research. In 1975 he completed his PhD thesis and was afterwards a scientific staff member of the Max Planck Institute for Metals Research until 1984. During this time he was also a visiting scientist at the Atomic Energy Board, Pretoria (South Africa) in 1976–77 and at the IBM Watson Research Center, Yorktown Heights (NY, USA) in 1980–81. He finished his Habilitation in 1983 at the University of Stuttgart. From 1984 to 1985 he was with Siemens Corporation, Munich, before he accepted a professorship of materials science in 1985 at Duke University, Durham (NC, USA). In 1991 he was a visiting scientist at the NTT LSI Laboratories, Atsugi (Japan). From 1993 he was a Director and Scientific Member at the Max Planck Institute of Microstructure Physics, Halle (Germany). He was also an Adjunct Professor at the Martin-Luther University, Halle-Wittenberg (from 1994) and at Duke University (from 1998).

He started his career as a theoretician, working on topics like diffusion-controlled reaction kinetics, radiation damage in metals, and transfer of electron excitation energy in liquids and solids. In 1975 he became interested in point defects and diffusion in silicon. His first paper in this area was published together with H. Föll and B.O. Kolbesen on agglomerates of intrinsic point defects, the so-called swirl defects [1]. Especially, his time at the IBM Watson Research Center and the intensive cooperation with T.Y. Tan resulted in numerous publications about point defects and diffusion in silicon.

His theoretical education and an evolving deep understanding and appreciation of experimental work may be a reason that he started research in the field of wafer bonding in the late 1980s at Duke University. Especially, the support by Dr. Takao Abe from Shin-Etsu Handotai Co., Isobe (Japan) enabled such experiments. A first result was the construction and application of a micro-cleanroom setup in 1988 allowing the bonding of wafers in a particle-free ambient under environmental conditions [2]. The principle of the micro-cleanroom setup was the basis of one of his most important patents [3] and was transferred to Karl Süss GmbH, a manufacturer of semiconductor equipment in the city of Garching close to Munich (Germany) resulting in one of the first commercially available wafer bonding tools in the early 1990s.

The increasing number of new students in his group allowed him to study different aspects of wafer bonding. First experiments on the wafer bonding of silicon to glass or to sapphire were carried out. Furthermore, aspects of wafer thinning processes by applying etch stop layers (carbon ion-implantation, etc.) were investigated. One of the most remarkable studies at this time was the analysis of defects formed in the interface of bonded wafer pairs [4]. All these investigations resulted in a first model of (hydrophilic) silicon wafer bonding by him together with Stengl and Tan [5]. In the early 1990s his research was focused on the preparation of silicon-on-insulator wafers by wafer bonding techniques. Besides numerous publications, another important patent concerns hydrogen-induced layer transfer [6].

Gösele continued his research activities after joining the newly founded Max Planck Institute of Microstructure Physics in 1993. Based on the support given by the Max Planck Society additional activities were undertaken in the research of wafer bonding. One example was the installation of an ultrahigh-vacuum tool allowing the wafer bonding under ultrahigh-vacuum conditions. Combined with computer simulations, molecular dynamic models of interface processes during wafer bonding were developed. Furthermore, the installation of various pieces of equipment such as cleanroom facilities resulted in numerous other research activities in the field of wafer bonding. These activities included, for instance, wafer bonding via designed monolayers, the bonding of different III–V compounds, and the development of methods for low-temperature wafer bonding.

His enormous range of research activities resulted in the publication of more than 700 articles in refereed journals, and the granting of numerous patents. He was one of the organizers of the first Symposium on Semiconductor Wafer Bonding: Science, Technology, and Applications held during the Autumn Meeting of the Electrochemical Society in October 1991 in Phoenix, AZ, USA. In addition to C.E. Hunt, H. Baumgart, S.S. Iyer, and T. Abe, he was an organizer of the 3rd Symposium on Semiconductor Wafer Bonding held during the Spring Meeting of the Electrochemical Society in 1995 in Reno, NV, USA. He was coauthor and coeditor, respectively, of the famous monographs Semiconductor Wafer Bonding: Science and Technology [7] and Wafer Bonding: Applications and Technology [8].

Ulrich Gösele’s work and personality were appreciated all over the world and recognized by many honors and awards. For instance, he obtained the Electronics Division Award of the Electrochemical Society (1999), he was on the Board of Directors of the Materials Research Society (USA), and was a Fellow of the American Physical Society and a Fellow of the Institute of Physics (UK).

References

1 Föll, H., Gösele, U., and Kolbesen, B.O. (1977) The formation of swirl defects in silicon by agglomeration of self-interstitials. J. Cryst. Growth, 40, 90.

2 Stengl, R., Ahn, K.-Y., and Gösele, U. (1988) Bubble-free silicon wafer bonding in a non-cleanroom environment. Jpn. J. Appl. Phys., 27, L2364.

3 Gösele, U. and Stengl, R. (1988) Method for bubble-free bonding of silicon wafers. US Patent 4,883,215, filed 19 December 1988, issued 28 November 1989.

4 Mitani, K., Lehmann, V., Stengl, R., Feijoo, D., Gösele, U., and Massoud, H. (1991) Causes and prevention of temperature-dependent bubbles in silicon wafer bonding. Jpn. J. Appl. Phys., 30, 615.

5 Stengl, R., Tan, T., and Gösele, U. (1989) A model for the silicon wafer bonding process. Jpn. J. Appl. Phys., 28, 1735.

6 Gösele, U. and Tong, Q.-Y. (1997) Method for the transfer of thin layers of monocrystalline material to a desirable substrate. US Patent 5,877,070, filed 31 May 1997, issued 2 March 1999.

7 Tong, Q.-Y. and Gösele, U. (1999) Semiconductor Wafer Bonding: Science and Technology, John Wiley & Sons, Inc., New York.

8 Alexe, M. and Gösele, U. (eds) (2004) Wafer Bonding: Applications and Technology, Springer Verlag, Heidelberg.

List of Contributors

Knut Aasmundtveit

Vestfold University College

Department of Micro and Nano Systems Technology

Faculty of Science and Engineering

PO Box 2243

3103 Tønsberg

Norway

Karlheinz Bock

Fraunhofer Research Institution for Modular Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Joerg Braeuer

Fraunhofer ENAS

Department of System Packaging

09126 Chemnitz

Germany

Kuan-Neng Chen

National Chiao Tung University

Department of Electronics Engineering

Hsinchu 300

Taiwan

Léa Di Cioccio

CEA-Leti, MINATEC

Département Intégration Hétérogène Silicium

17 rue des Martyrs

38054 Grenoble Cedex 9

France

Viorel Dragoi

EV Group

E. Thallner Straße 1

4782 St Florian

Austria

Paul Enquist

Ziptronix, Inc.

800 Perimeter Park

Morrisville, NC 27560

USA

Philip Garrou

Microelectronic Consultants of NC

3021 Cornwallis Road

Research Triangle Park

NC 27709-2889

USA

Thomas Gessner

Fraunhofer ENAS

Department of System Packaging

09126 Chemnitz

Germany

and

TU Chemnitz

Center for Microtechnologies

09126 Chemnitz

Germany

Ulrich Gösele

Max Planck Institute of Microstructure Physics

Weinberg 2

06120 Halle

Germany

Ronald J. Gutmann

Rensselaer Polytechnic Institute

Department of Electrical, Computer, and Systems Engineering

CII-6015, 110 8th Street

Troy, NY 12180

USA

Nils Hoivik

Vestfold University College

Department of Micro and Nano Systems Technology

Faculty of Science and Engineering

PO Box 2243

3103 Tønsberg

Norway

Matthias Hutter

Fraunhofer IZM

Gustav-Meyer-Allee 25

13355 Berlin

Germany

Armin Klumpp

Fraunhofer Research Institution for Modular Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Roy Knechtel

X-FAB Semiconductor Foundries AG

Haarbergstraße 67

99097 Erfurt

Germany

Mitsumasa Koyanagi

Tohoku University

Graduate School of Engineering

6-6-04 Aramaki Aza, Aoba Ku

Sendai 808578

Japan

Christof Landesberger

Fraunhofer Research Institution for Modular Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Adriana Cozma Lapadatu

SensoNor Technologies AS

Knudsrødveien 7

3192 Horten

Norway

James Jian-Qiang Lu

Rensselaer Polytechnic Institute

110 8th Street

Troy, NY 12180-3590

USA

Jian-Qiang Lu

Rensselaer Polytechnic Institute

Department of Electrical, Computer, and Systems Engineering

CII-6015, 110 8th Street

Troy, NY 12180

USA

J. Jay McMahon

Rensselaer Polytechnic Institute

Department of Electrical, Computer, and Systems Engineering

CII-6015, 110 8th Street

Troy, NY 12180

USA

Makoto Motoyoshi

ZyCube Co. Ltd

4259-3 Nagatsuta-cho, Midori-ku

Yokohama 226-8510

Japan

Frank Niklaus

KTH – Royal Institute of Technology

Microsystem Technology (MST)

School of Electrical Engineering

100 44 Stockholm

Sweden

Hermann Oppermann

Fraunhofer IZM

Gustav-Meyer-Allee 25

13355 Berlin

Germany

Werner Pamler

Thin Materials AG

Hansastraße 27d

80686 Munich

Germany

Rama Puligadda

Brewer Science Inc.

Brewer Drive

Rolla, MO 65401

USA

Peter Ramm

Fraunhofer Research Institution for Modular Solid State Technologies EMFT

Hansastrasse 27d

80686 Munich

Germany

Manfred Reiche

Max Planck Institute of Microstructure Physics

Weinberg 2

06120 Halle

Germany

Franz Richter

Thin Materials AG

Hansastraße 27d

80686 Munich

Germany

Kari Schjølberg-Henriksen

SINTEF

Department of Microsystems and Nanotechnology

0314 Oslo

Norway

Maaike M.V. Taklo

SINTEF ICT

Instrumentation

PO Box 124 Blindern

0314 Oslo

Norway

Chuan Seng Tan

Nanyang Technological University

50 Nanyang Avenue

Singapore 639798

Singapore

Maik Wiemer

Fraunhofer ENAS

Department of System Packaging

09126 Chemnitz

Germany

Dirk Wuensch

TU Chemnitz

Center for Microtechnologies

09126 Chemnitz

Germany

Introduction

Peter Ramm, James Jian-Qiang Lu, and Maaike M.V. Taklo

As editors of this book, we consider that there is a strong need to update the state of the art on wafer bonding [1–3]. The major reason is that corresponding development has truly sped up in recent years, motivated by the extended use of wafer bonding in new technology areas, such as three-dimensional (3D) integration, temporary bonding, and microelectromechanical systems (MEMS) with new functional layers. With novel areas of application, new objectives for wafer bonding technologies arise. For IC fabrication the traditionally much finer pitch used – compared to MEMS applications – has demanded sophisticated wafer bonding solutions. Metals, such as copper that has been used widely in the IC world, have also received a lot more attention for wafer bonding after wafer bonding became of interest for the IC community. For true 3D vertical integration where the IC wafers contain through-silicon vias (TSVs), electrical interconnects are needed between the wafers at their interfaces and can be realized by metal bonding. The interface interconnects and the TSVs can be formed either before or after bonding. This handbook covers a variety of wafer bonding technologies and applications and is structured according to these two aspects.

Technologies

In Part One, the technologies are sorted into four categories:

A) adhesive and anodic bonding;

B) direct wafer bonding;

C) metal bonding;

D) hybrid metal/dielectric bonding.

Other ways of sorting the technologies are possible, but the sorting taken here distinguishes the materials, approaches, and applications. We have attempted to include all bonding technologies that have received a reasonable level of attention from both the research and commercial communities. We are fully aware that some variants have been left out. These are not forgotten or excluded, but some level of standardization is believed to be beneficial for most of the communities. This being said, it can be a hard decision whether to further optimize existing bonding technologies or to move to a new bonding regime. To move from one bonding technology to another can take years, something companies have painfully learned. Take MEMS as an example: it seems that the MEMS manufacturers are gradually moving from glass-based methods to metal-based methods. A product can benefit from a reduced bond frame width in the case of metal bonding, but the inclusion of metal as a bond frame material may have consequences for the complete process flow of the product. For yet other products in the same manufacturer’s portfolio, the former glass-based solution may still be a better solution. The result is that a manufacturer has to deal with two bonding technologies rather than only one; this normally increases the manufacturing cost since it always takes more engineering effort to keep two processes up and running. Some choices have to be made: whether to always keep changing or upgrading the bonding technology for a given product, or to have one robust and flexible bonding technology and to modify all products accordingly. In this handbook the reader will find an overview of the most commonly used bonding solutions, and the arguments for these choices, as of today.

In Part One (A) we consider adhesive, anodic, glass frit, and spin-on glass (SOG) bonding. A glass material is common for anodic, glass frit, and SOG bonding. Commonly, the bonding material is spun or otherwise coated for adhesive, glass frit, and SOG bonding. Part One (A) focuses on these materials.

Adhesive bonding has in some cases been referred to as “simply” gluing wafers. The associations with glue seem something less advanced than other bonding methods; however, this is not true, and the reader will get a clear understanding from Chapter 3. Even though a finally optimized adhesive bonding process may appear straightforward as the surface topography can be compensated to a large extent and the bonding material appears homogeneous, one should not be fooled; a successful adhesive bonding is typically a result of combined advanced material development and careful bonding process optimization. Applications of adhesive bonding range from bonding of delicate logic wafers to bonding of low-cost wafers with large line widths for fluidic systems. In addition, temporary bonding is to a large extent based on the knowledge of adhesive bonding. However, some new materials have been developed for temporary bonding, in particular as the need for debonding was introduced. Some alternative process modification techniques were presented by SOITEC/LETI some years ago for debonding (the roughness could be tuned with a precision of nanometers), but wax seems to dominate this field at the present time.

The history of anodic bonding is long – normally considered to start with the article of Wallis and Pomerantz back in 1969. The robustness of the process is probably what has kept the technology in use. It is a popular bonding technique especially for MEMS manufacturing, and the technology is described in this book in Chapter 4, the authors of which have decades of experience using anodic bonding for industrial applications. This bonding technology is demanding with regard to surface topography, but to a level acceptable for most MEMS manufacturers. Smart designs of horizontal conductors have allowed cavities to be hermetically sealed using anodic bonding despite the demands of a low surface roughness. The challenge of sealing cavities with crossing conductor lines has come up repeatedly. Glass frit bonding, here described in Chapter 1, has offered a way around this since more surface roughness is tolerable. Since the final bond is glass in both cases, the two technologies have several common issues with regard to reliability (leak rates, fracture mechanics, etc.) and can be considered as competing technologies. However, today we see several glass wafer manufacturers offering wafers with silicon or metal vertical vias. When the conductors are no longer crossing the bond line, there is a possibility that anodic bonding will actually gain some new interest. Spin-on glass is not as widely used as the other techniques mentioned, but there are some advantages with this technique, which justify a separate chapter (Chapter 2).

In Part One (B) we have gathered direct wafer bonding (DWB) methods. We have limited this to techniques where the wafers, either bare or oxidized, are contacted directly. We consider fusion bonding and plasma-activated bonding (PAB) to be subgroups of DWB, and the topics are thoroughly described in this book in Chapters 5 and 6, respectively. In both cases, the wafers are pre-bonded at room temperature and post-bond annealing is performed in a furnace or hot chamber depending on required temperatures. The pretreatment of the wafers differs in the two cases, but typically the surfaces are rendered either extremely hydrophilic or hydrophobic by wet or dry processing. The post-bond treatment temperature ranges from low temperature (or no heating) for PAB to heating above 1000 °C for fusion bonding. Obviously, the temperature treatment sets the limit for how a process sequence can be organized, but also the extreme demands of DWB with regard to surface roughness set strong limitations on how wafers can be treated before bonding. These issues are discussed in both the technology and the application chapters dealing with DWB.

In Part One (C) we have grouped four chapters on metal bonding methods. There is a wide range of metals that have been demonstrated to be applicable for wafer-level bonding within the semiconductor industry. It is certainly a benefit when metals that are already part of the CMOS industry can be used for bonding, but this has not been an absolute limitation for the choice of metals. When bonding is performed as one of the last process steps, compatibility issues with existing materials are less of a concern – as long as a satisfactory diffusion barrier is incorporated. But for bonding as an intermediate process step, the choice of metal is crucial. The application of copper as a bonding material has lately become popular for compatibility issues among other reasons. Copper is a demanding material with regard to wafer bonding; a high bonding pressure and/or extreme surface control may be required. However, these obstacles have been overcome as described, for example, in Chapter 9. Other metals or metal systems that are of interest are combinations of tin, copper, gold, and indium. Important knowledge about the complexity of the corresponding phase diagrams of these systems has, to a large extent, come from the knowledge of researchers working in the field of electronic packaging. Chapters 7, 8, and 10 describe how this knowledge has been applied to “tame” the devils in the detailed diagrams.

The idea of hybrid bonding, as described in Part One (D), is basically to take the best of two worlds and combine them into a wafer bonding method, resulting in mechanical and electrical connection between wafers at one step. The challenge necessarily is to find process parameters that fit the two combined bonding methods at once. As more than one solution to this challenge has been presented, several chapters are dedicated to this topic. Chapters 12 and 13 both describe how metals like copper or nickel can be combined with inorganic dielectrics like oxides; copper combined with a polymer is presented in Chapter 11. A core part of these discussions is how to tune the polishing processes to two materials at the same time to achieve the required surface smoothness for high-quality bonding.

Applications

In Part Two, recent applications of wafer bonding are described.

In general, wafer bonding technologies are applied over a wide range, such as:

silicon-on-insulator wafers or variations for semiconductor applications;MEMS for nonhermetic, hermetic, and extremely hermetic attachment of parts, and combined possibilities;fluidic systems for a variety of applications in thermal management or biomedical devices;handling of thin wafers/chips for further processing in semiconductor processes and packaging;3D ICs for stacking memories or memories/microprocessors for computation and communication systems;3D heterogeneous integration and packaging to integrate a variety of components (such as CMOS image sensors and readout circuits) into one compact system.

This handbook is not intended to give a comprehensive summary of wafer bonding applications because many applications are described in other books and more applications are still emerging. Besides the applications discussed in the chapters in Part One, chapters in Part Two summarize the key wafer bonding applications developed recently, that is, 3D integration, MEMS, and temporary bonding, to give readers a taste of where the wafer bonding technologies are applied significantly.

Definitions

Many terminologies are defined in individual chapters in this handbook. Here we focus only on a few terminologies, which we thought should be further clarified.

Several chapters in this handbook deal with wafer bonding by use of metal systems. Besides direct metal bonding (Chapters 6 and 9), there are two bonding methods using liquid phases: eutectic bonding and solid–liquid interdiffusion (SLID) bonding (Chapters 7 and 10). Both use a combination of low- and high-melting metals, and unfortunately are not always correctly distinguished in the literature. Eutectic soldering is a very well-known technology that has been used for many years in microelectronic packaging, for example in so-called flip-chip bonding. The soldering process of heating to the melting temperature and cooling is, in principle, reversible: by heating again above the eutectic temperature the metal system re-melts. In contrast, SLID bonding is irreversible, utilizing the diffusion of solid material of a high-melting metal into the liquid phase of a low-temperature metal at constant temperature and resulting in a thermomechanically stable intermetallic compound. It may be slightly confusing that in the literature different terms are used for this dedicated soldering principle, as for example “transient liquid-phase bonding.” As the process was described first in 1966 by Bernstein and Bartholomew [4], the editors prefer to use the original term SLID defined there.

Three-dimensional integration is generally defined as the fabrication of stacked and vertically interconnected device layers. Numerous corresponding technology concepts have been introduced since the 1980s (e.g., Siemens and Fraunhofer Institute Munich) and several companies and research organizations have developed full 3D process demonstrations. However, only a few of them have already come to production. One of the reasons is the concern about introduction of sophisticated advanced processes into production lines. Reliable and robust wafer bonding technologies are considered to play a key role in the fabrication of 3D integrated products.

Chapter 15 reports on diverse applications of 3D integration with the need for specific bonding technologies. Categories for a great variety of 3D technologies are defined there. Of particular interest are TSV technologies. A TSV is defined as an electrical interconnection between two sides of a silicon substrate. Besides the TSV process, wafer thinning, thin wafer handling, backside processing, and 3D stacking are the basic technology modules. Wafer bonding technologies are needed here for both thin wafer handling and 3D stacking:

permanent bonding for 3D stacking (Chapters 2–14);temporary bonding for thin wafer handling (Chapters 16, 18, and 19).

The choice of the wafer bonding technologies has to be made by considering full process conditions such as temperature limitations and the sequence of the technology modules, which may vary for different applications. The resulting large variety of process flows is categorized according to ITRS [5] and explicitly corresponds to the order of TSV processing, wafer thinning, and wafer bonding. The order of the TSV process with respect to device fabrication is one of the main criteria, and today commonly characterizes TSV fabrication:

prior silicon front-end-of-line (FEOL) – “via first”;post silicon back-end-of-line (BEOL) – “via last”;post FEOL but prior BEOL – “via middle.”

The choice of the corresponding TSV technology for fabrication of a 3D integrated product has significant consequences for the wafer bonding technology to be applied, as shown in Figure 1. Here, the two bonding approaches on the left-hand side are “via last” 3D integration technologies, where TSVs are formed after wafer bonding and thinning. The two bonding approaches on the right-hand side can form electrical interconnections during the bonding process, while TSVs can be made at any stage of the processing flow, depending on the applications and processing constraints. Detailed materials and bonding conditions are described in the corresponding chapters.

Figure 1 Schematic of four typical wafer bonding schemes for 3D integration with TSVs (not to scale). The thinned device wafer usually has FEOL devices and BEOL interconnects (not shown).

In Chapter 15 the large variety of 3D integration technologies are defined and categorized. The most common wafer bonding technologies for application in 3D integration are there specified and exemplarily described regarding the interaction between bonding processes and 3D processing flows.

Conclusions

This handbook summarizes a variety of wafer bonding technologies and applications. In particular, the fundamental knowledge needed for wafer bonding is highlighted in individual chapters. As polymers are applied more widely in electronics and for sensors to reduce cost, knowledge of chemistry is required in addition to the physics and electronics knowledge that has dominated in some research areas. Eutectic bonding demands a thorough understanding of metallurgy in order to get a good understanding of how various phases are formed during heating and cooling. For adhesive bonding it is rather an understanding of how the molecules crosslink and how the materials soften with heat that is important. For both bonding solutions, wetting of surfaces is critical, so this is another topic that should be well understood. For hybrid metal/dielectric bonding, knowledge of chemistry, physics, and surface planarization and treatment is critical. When it comes to characterization, it is often fracture mechanics that is the subject. It is important to know how the bond strength of interfaces should be characterized in order to ensure a certain reliability of the bonding interface.

For future applications, more knowledge may be needed for a variety of topics, such as larger or thinner wafers and fine-pitch interwafer interconnections (such as TSVs), and hence better alignment, better wafer thinning control, as well as thermomechanical constraints. We expect that more detailed research and development will be conducted by companies for specific products and applications.

References

1 Tong, Q.-Y. and Gösele, U. (1999) Semiconductor Wafer Bonding: Science and Technology, John Wiley & Sons, Inc., New York.

2 Plößl, A. and Kräuter, G. (1999) Wafer direct bonding: tailoring adhesion between brittle materials. Mater. Sci. Eng., R25, 1–88.

3 Alexe, M. and Gösele, U. (eds) (2004) Wafer Bonding: Applications and Technology, Springer, Berlin.

4 Bernstein, L. and Bartholomew, H. (1966) Applications of solid–liquid interdiffusion (SLID) bonding in integrated-circuit fabrication. Trans. Metall. Soc. AIME, 236, 405–412.

5 Semiconductor Industry Association (2009) The International Technology Roadmap for Semiconductors, SEMATECH, Austin, TX (2010 update).

Part One: Technologies

A. Adhesive and Anodic Bonding

1

Glass Frit Wafer Bonding

Roy Knechtel

Glass frit wafer bonding is widely used in industrial microsystems applications where fully processed wafers have to be bonded. This end-of-process-line bonding must fulfill some very specific requirements, such as: process temperature limited to 450 °C to prevent any temperature-related damage to wafers, no aggressive cleaning to avoid metal corrosion, high process yield since wafer processing to this stage is expensive, bonding of wafers with certain surface roughness or even surface steps resulting from metal lines electrically running at the bonding interface to enable electrical connections into the cavity sealed by the wafer bonding, as well as a mechanically strong, hermetically sealed, reliable bond. All of these requirements are fulfilled by the glass frit wafer bonding process, which additionally can be very universally applied since it can be used to bond almost all surfaces common in microelectronics and microsystem technologies.