High-k Gate Dielectrics for CMOS Technology E-Book

• Herausgeber: Wiley-VCH
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 1128

Veröffentlichungsjahr: 2012

Beschreibung

A state-of-the-art overview of high-k dielectric materials for advanced field-effect transistors, from both a fundamental and a technological
viewpoint, summarizing the latest research results and development solutions. As such, the book clearly discusses the advantages of these
materials over conventional materials and also addresses the issues that accompany their integration into existing production technologies.

Aimed at academia and industry alike, this monograph combines introductory parts for newcomers to the field as well as advanced sections
with directly applicable solutions for experienced researchers and developers in materials science, physics and electrical engineering.

Leseprobe

Contents

Cover

Related Titles

Title Page

Copyright

Preface

List of Contributors

Part I: Scaling and Challenge of Si-based CMOS

Chapter 1: Scaling and Limitation of Si-based CMOS

1.1 Introduction

1.2 Scaling and Limitation of CMOS

1.3 Toward Alternative Gate Stacks Technology

1.4 Improvements and Alternative to CMOS Technologies

1.5 Potential Technologies Beyond CMOS

1.6 Conclusions

Acknowledgments

References

Part II: High-k Deposition and Materials Characterization

Chapter 2: Issues in High-k Gate Dielectrics and its Stack Interfaces

2.1 Introduction

2.2 High-k Dielectrics

2.3 Metal Gates

2.4 Integration of High-k Gate Dielectrics with Alternative Channel Materials

2.5 Summary

References

Chapter 3: UV Engineering of High-k Thin Films

3.1 Introduction

3.2 Gas Discharge Generation of UV (Excimer) Radiation

3.3 Excimer Lamp Sources Based on Silent Discharges

3.4 Predeposition Surface Cleaning for High-k Layers

3.5 UV Photon Deposition of Ta2O5 Films

3.6 Photoinduced Deposition of Hf1−xSixOy Layers

3.7 Summary

References

Chapter 4: Atomic Layer Deposition Process of Hf-Based High-k Gate Dielectric Film on Si Substrate

4.1 Introduction

4.2 Precursor Effect on the HfO2 Characteristics

4.3 Doped and Mixed High-k

4.4 Summary

References

Chapter 5: Structural and Electrical Characteristics of Alternative High-κ Dielectrics for CMOS Applications

5.1 Introduction

5.2 Requirement of High-k Oxide Materials

5.3 Rare-Earth Oxide as Alternative Gate Dielectrics

5.4 Structural Characteristics of High-κ RE Oxide Films

5.5 Electrical Characteristics of High-κ RE Oxide Films

5.6 Conclusions and Perspectives

References

Chapter 6: Hygroscopic Tolerance and Permittivity Enhancement of Lanthanum Oxide (La2O3) for High-k Gate Insulators

6.1 Introduction

6.2 Hygroscopic Phenomenon of La2O3 Films

6.3 Low Permittivity Phenomenon of La2O3 Films

6.4 Hygroscopic Tolerance Enhancement of La2O3 Films

6.5 Hygroscopic Tolerance Enhancement of La2O3 Films by Ultraviolet Ozone Treatment

6.6 Thermodynamic Analysis of Moisture Absorption Phenomenon in High-k Gate Dielectrics

6.7 Permittivity Enhancement of La2O3 Films by Phase Control

6.8 Summary

Acknowledgments

References

Chapter 7: Characterization of High-k Dielectric Internal Structure by X-Ray Spectroscopy and Reflectometry: New Approaches to Interlayer Identification and Analysis

7.1 Introduction

7.2 Chemical Bonding and Crystalline Structure of Transition Metal Dielectrics

7.3 NEXAFS Investigation of Internal Structure

7.4 Studying the Internal Structure of High-K Dielectric Films by Hard X-Ray Photoelectron Spectroscopy and TEM

7.5 Studying the Internal Structure of High-K Dielectric Films by X-ray Reflectometry

Acknowledgments

References

Chapter 8: High-k Insulating Films on Semiconductors and Metals: General Trends in Electron Band Alignment

8.1 Introduction

8.2 Band Offsets and IPE Spectroscopy

8.3 Silicon/Insulator Band Offsets

8.4 Band Alignment at Interfaces of High-Mobility Semiconductors

8.5 Metal/Insulator Barriers

8.6 Conclusions

References

Part III: Challenge in Interface Engineering and Electrode

Chapter 9: Interface Engineering in the High-k Dielectric Gate Stacks

9.1 Introduction

9.2 High-k Oxide/Si Interfaces

9.3 Metal Gate/High-k Dielectric Interfaces

9.4 Chemical Tuning of Band Alignments for Metal Gate/High-k Oxide Interfaces

9.5 Summary and Discussion

References

Chapter 10: Interfacial Dipole Effects on High-k Gate Stacks

10.1 Introduction

10.2 Metal Gate Consideration

10.3 Interfacial Dipole Effects in High-k Gate Stacks

10.4 Observation of the Interfacial Dipole in High-k Stacks

10.5 Summary

References

Chapter 11: Metal Gate Electrode for Advanced CMOS Application

11.1 The Scaling and Improved Performance of MOSFET Devices

11.2 Urgent Issues about MOS Gate Materials for Sub-0.1 µm Device Gate Stack

11.3 New Requirements of MOS Gate Materials for Sub-0.1 µm Device Gate Stack

11.4 Summary

References

Part IV: Development in non-Si-based CMOS technology

Chapter 12: Metal Gate/High-κ CMOS Evolution from Si to Ge Platform

12.1 Introduction

12.2 High-κ/Si CMOSFETs

12.3 High-κ/Ge CMOSFETs

12.4 Ge Platform

12.5 Conclusions

Acknowledgments

References

Chapter 13: Theoretical Progress on GaAs (001) Surface and GaAs/high-κ Interface

13.1 Introduction

13.2 Computational Method

13.3 GaAs Surface Oxidation and Passivation [17]

13.4 Origin of Gap States at the High-k/GaAs Interface and Interface Passivation

13.5 Conclusions

Acknowledgments

References

Chapter 14: III–V MOSFETs with ALD High-κ Gate Dielectrics

14.1 Introduction

14.2 Surface Channel InGaAs MOSFETs with ALD Gate Oxides

14.3 Buried Channel InGaAs MOSFETs

14.4 Summary

References

Part V: High-k Application in Novel Devices

Chapter 15: High-k Dielectrics in Ferroelectric Gate Field Effect Transistors for Nonvolatile Memory Applications

15.1 Introduction

15.2 Overview of High-k Dielectric Studies for FeFET Applications

15.3 Developing of HfTaO Buffer Layers for FeFET Applications

15.4 Summary

Acknowledgment

References

Chapter 16: Rare-Earth Oxides as High-k Gate Dielectrics for Advanced Device Architectures

16.1 Introduction

16.2 Key Challenges for High-k Dielectrics

16.3 Rare-Earth Oxides as High-k Dielectrics

16.4 High-k Dielectrics in Advanced Device Architecture

References

Part VI: Challenge and Future Directions

Chapter 17: The Interaction Challenges with Novel Materials in Developing High-Performance and Low-Leakage High-κ/Metal Gate CMOS Transistors

17.1 Introduction

17.2 Traditional CMOS Integration Processes

17.3 High-κ/Metal Gate Integration Processes

17.4 Mobility

17.5 Metal Electrodes and Effective Work Function

17.6 Tinv Scaling and Impacts on Gate Leakage and Effective Work Function

17.7 Ambients and Oxygen Vacancy-Induced Modulation of Threshold Voltage

17.8 Reliability

17.9 Conclusions

References

Index

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Preface

In 1965, Gordon Moore wrote a paper entitled “Cramming more Components onto Integrated Circuits” where he first proposed that transistor density on chips would grow exponentially. This became known as Moore's law. Remarkably, the industry has kept pace with this exponential growth for that past four decades. To keep track with the Roadmap, scaling of the gate stack has been a key to enhancing the performance of complementary metal oxide semiconductor field-effect transistors (CMOSFETs) of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. However, further scaling the FET is eventually going to be impeded by the inability to further reduce the oxide thickness without risking a breakdown of the device. New technology problems, including the dielectric thickness variation, direct tunnel current, penetration of impurities, and the reliability and lifetime of devices, arose, which cause significant concern regarding the operation of CMOS devices, particularly with regard to standby power dissipation, reliability, and lifetime. Intense research during the past decade has led to the development of high dielectric constant (k) gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. This book provides a perspective on the gate dielectric and the approaches in progress to rectify the above noted issues, that is, increasing the physical thickness of the gate dielectric to significantly reduce the power and direct tunneling current issues while enabling the continued reduction in the electrically active gate dielectric thickness by utilizing high-k dielectric constant materials. The high-k materials facilitate both an increased physical thickness and a reduction in the electrical thickness to maintain the requisite scaling methodology. This monograph, however, is envisioned to be more than just a current view of these alternative high-k gate stack technology. Rather, both previous and present directions related to scaling the gate dielectric and their impact, along with the creative directions and future challenges defining the direction of high-k gate dielectric scaling methodology, will be reviewed.

The monograph is introduced by a comprehensive review of scaling and limitation of Si-based CMOS by Gang He. In this part, a detailed discussion of current dielectrics and those proposed for future generations is included. Current beliefs regarding the limitations of silicon dioxide as the gate dielectric are reviewed. Ultrathin oxides, including gate dielectrics below 40 Å, some of which are nitrided silicon oxides are discussed. The benefits and limitations of alternative for new high-k materials for possible high-performance CMOS applications are reviewed. Part 2 addresses the high-k deposition and material characterization with seven chapters. Initially, Hong-Liang Lu discusses the issue of high-k gate stacks and shows the criteria for selecting alternative high-k gate dielectrics. Then, Ian W. Boyd and Cheol Seong Hwang discuss the high-k deposition by UV-photo-CVD and ALD technology. Structure, band alignment, and electrical characteristics have been given by Tung-Ming Pan, Yi-Zhao, Elena O. Filatova1, and V. V. Afanas'ev. The challenge in interface engineering and gate electrode has been described in Part 3 by Shi-Jie Wang, Li-Qiang Zhu, and Wen-Wu Wang.

Part 4 discusses the development of non-Si-based CMOS technology. Initially, Albert Chin gives the description of metal gate/high-k CMOS evolution from Si to Ge platform. Then, Wei-Chao Wang reviews the progress on GaAs/high-k interface. Jack C. Lee continues to discuss the III–V MOSFET with ALD-derived high-k gate dielectrics. In Part 5, high-k application in novel devices has been discussed by Xu-Bin Lu and Pooi See Lee. The last chapter of this book by M. Chudzik addresses the challenges and future directions for advanced technology generations. The vision, experience, and wisdom the authors have summarized will help succeed in ensuring this monograph is a timely, relevant, interesting, and resourceful book focusing on both the fundamentals and the evolving directions to ensure the successful integration of high-k gate dielectrics and metal gate electrodes in future ICs as envisioned in the ITRS.

We thank Wiley-VCH for inviting us to write/edit the book and we hope to stimulate even more the incorporation of high-k gate technology in the near future. Last but not least, we express our thanks to Dr Martin Preuss and Dr. Ernest Kirkwood, who gave us time and resources to edit this book.

Dec. 2011Hefei

Gang HeZhaoqi Sun

List of Contributors

Albert Achin

National Chiao-Tung University

Electronics Engineering Department and College of Photonics

1001 University Road

Hsinchu 300

Taiwan

Valeri V. Afanas'ev

University of Leuven

Department of Physics and Astronomy

Laboratory of Semiconductor Physics

Celestijnenlaan 200D

3001 Leuven

Belgium

Takashi Ando

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Ian W. Boyd

Brunel University

Experimental Techniques Center

Kingston Lane

Uxbridge, Middlesex UB8 3PH

UK

and

Irving Ian LIAW

Melbourne Materials Institute

David Caro Building

University of Melbourne

Parkville 3010, VICAustralia

Huiming Bu

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Ed Cartier

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Mei Yin Chan

Nanyang Technological University

School of Materials Science and Engineering

Block N4.1, 50 Nanyang Avenue

Singapore 639798

Singapore

Fu-Chien Chiu

Ming-Chuan University

Department of Electronic Engineering

Taoyuan 333

Taiwan

Kyeongjae Cho

The University of Texas at Dallas

Department of Materials Science & Engineering

800 W. Campbell Road, RL 10

Richardson, TX 75080

USA

and

The University of Texas at Dallas

Department of Physics

800 W. Campbell Road, RL 10

Richardson, TX 75080

USA

Moonju Cho

Seoul National University

Department of Materials Science and Engineering and Inter-University

Semiconductor Research Center

WCU Hybrid Materials Program

Seoul 151-744

Korea

and

IMEC

75 Kapeldreef

3001 Leuven

Belgium

Michael Chudzik

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Peter Damarwan

Nanyang Technological University

School of Materials Science and Engineering

Block N4.1, 50 Nanyang Avenue

Singapore 639798

Singapore

Yuanping Feng

National University of Singapore

Department of Physics

2 Science Drive 3

Singapore 117542

Singapore

Elena O. Filatova

Petersburg State University

St. Petersburg 198504

Russia

Kai Han

Chinese Academy of Sciences

Institute of Microelectronics

3 # BeiTuCheng West Road

Chaoyang District

Beijing 100029

China

Gang He

Anhui University

School of Physics and Materials Science

Anhui Key Laboratory of Information Materials and Devices

Feixi Road 3

Hefei 230039

China

Michel Houssa

University of Leuven

Department of Physics and Astronomy

Laboratory of Semiconductor Physics

Celestijnenlaan 200D

3001 Leuven

Belgium

Alfred C. H. Huan

Nanyang Technological UniversityDivision of Physics and Applied

Physics School of Physical and Mathematical Sciences

21 Nanyang Link

Singapore 637371

Singapore

Cheol Seong Hwang

Seoul National University

Department of Materials Science and Engineering and Inter-University

Semiconductor Research Center

WCU Hybrid Materials Program

Seoul 151-744

Korea

Hyung-Suk Jung

Seoul National University

Department of Materials Science and Engineering and Inter-University

Semiconductor Research Center

WCU Hybrid Materials Program

Seoul 151-744

Korea

Mukesh Khare

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Igor V. Kozhevnikov

Institute of Crystallography

Moscow 119333

Russia

Siddarth Krishnan

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Unoh Kwon

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Jack C. Lee

The University of Texas at Austin

Microelectronics Research Center

Department of Electrical and Computer Engineering

10100 Burnet Road

Austin, TX 78758-4445

USA

Pooi See Lee

Nanyang Technological University

School of Materials Science and Engineering

Block N4.1, 50 Nanyang Avenue

Singapore 639798

Singapore

Mao Liu

Chinese Academy of Sciences

Institute of Solid State Physics

Anhui Key Laboratory of Nanomaterials and Nanostructure

Key Lab of Materials Physics

Hefei 230031

China

Hong-Liang Lu

Fudan University

Department of Microelectronics

State Key Laboratory of ASIC and System

220 Handan Road

Shanghai 200433

China

Xubing Lu

South China Normal University

Higher Education Mega CenterGuangzhou

School of Physics and Telecommunication Engineering

Institute for Advanced Materials (IAM)

Guangdong 510006

China

Somnath Mondal

Chang Gung University

Department of Electronic Engineering

Taoyuan 333

Taiwan

Vijay Narayanan

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Tung-Ming Pan

Chang Gung University

Department of Electronic Engineering

Taoyuan 333

Taiwan

Tae Joo Park

Seoul National University

Department of Materials Science and Engineering and Inter-University

Semiconductor Research Center

WCU Hybrid Materials Program

Seoul 151-744

Korea

and

Hanyang University

Department of Materials Engineering

Ansan 426-791

Korea

Vamsi Paruchuri

IBM Semiconductor Research and Development Center (SRDC)

IBM Systems and Technology Division

Hopewell Junction, NY 12533

USA

Andrey A. Sokolov

Petersburg State University

St. Petersburg 198504

Russia

Andre Stesmans

University of Leuven

Department of Physics and Astronomy

Laboratory of Semiconductor Physics

Celestijnenlaan 200D

3001 Leuven

Belgium

Zhaoqi Sun

Anhui University

School of Physics and Materials Science

Anhui Key Laboratory of Information Materials and Devices

Feixi Road 3

Hefei 230039

China

Robert M. Wallace

The University of Texas at Dallas

Department of Materials Science & Engineering

800 W. Campbell Road, RL 10

Richardson, TX 75080

USA

and

The University of Texas at Dallas

Department of Physics

800 W. Campbell Rd., RL10

Richardson, TX 75080

USA

Shijie Wang

A*STAR (Agency for Science, Technology and Research)

Institute of Materials Research and Engineering (IMRE)

3 Research Link

Singapore 117602

Singapore

Weichao Wang

The University of Texas at Dallas

Department of Materials Science & Engineering

800 W. Campbell Road, RL10

Richardson, TX 75080

USA

Wenwu Wang

Chinese Academy of Sciences

Institute of Microelectronics

3 # BeiTuCheng West Road

Chaoyang District

Beijing 100029

China

Xiaolei Wang

Chinese Academy of Sciences

Institute of Microelectronics

3 # BeiTuCheng West Road

Chaoyang District

Beijing 100029

China

Ka Xiong

The University of Texas at Dallas

Department of Materials Science & Engineering

800 W. Campbell Road, RL10

Richardson, TX 75080

USA

David Wei Zhang

Fudan University

Department of Microelectronics

State Key Laboratory of ASIC and System

220 Handan Road

Shanghai 200433

China

Lide Zhang

Chinese Academy of Sciences

Institute of Solid State Physics

Anhui Key Laboratory of Nanomaterials and Nanostructure

Key Lab of Materials Physics

Hefei 230031

China

Han Zhao

The University of Texas at Austin

Microelectronics Research Center

Department of Electrical and Computer Engineering

10100 Burnet Road

Austin, TX 78758-4445

USA

Yi Zhao

Nanjing University

School of Electronic Science and Engineering

Hankou Road 22

Nanjing 210093

China

Li Qiang Zhu

Chinese Academy of Sciences

Ningbo Institute of Material Technology and Engineering

519 Zhuangshi Road, Zhenhai

Ningbo 315201

China

Part I

Scaling and Challenge of Si-based CMOS

Chapter 1

Scaling and Limitation of Si-based CMOS

Gang He, Zhaoqi Sun, Mao Liu, and Lide Zhang

1.1 Introduction

Scaling transistor's dimensions has been the main tool to power the development of silicon integrated circuits (ICs). The more an IC is scaled, the higher its packing density and the lower its power dissipation [1]. These have been key in the evolutionary progress leading to today's computers and communication systems that offer superior performance, dramatically reduced cost per function, and much reduced physical size compared to their predecessors. However, the fundamental limits of complementary metal oxide semiconductor (CMOS) technology have been discussed, reviewed, and claimed to be at hand since the first MOS processes were developed [2, 3]. The integration of semiconductor devices has gone through different stages. At each stage of evolution, limits were reached and then subsequently surpassed, and very little has changed in the basic transistor design.

Questions about the end of CMOS scaling have been discussed, but engineering ingenuity has proven the predictions wrong. The most spectacular failures in predicting the end involved the “lithography barrier,” in which it was assumed that spatial resolution smaller than the wavelength used for the lithographic process is not possible [4, 5], and the “oxide scaling barrier,” in which it was claimed that the gate oxide thickness cannot be reduced below 3 nm due to gate leakage [6]. For the present and near future, it appears unlikely that lithography will limit the scaling of silicon devices. The cost of lithography tools, including that required for making masks, may, however, impede future scaling of devices. It is more likely that a fundamental limit will halt further scaling when at least one of physical dimensions of the device, be it a length, width, depth, or thickness, approaches a few silicon atoms. Manufacturing tolerance, and therefore economics, may dictate an end to the scaling of silicon devices before these fundamental limits are reached. Therefore, in this chapter on scaling of SiO2-based gate dielectrics for MOS devices, only present perceived fundamental limits are considered.

The downscaling of an MOSFETS sets demands especially on the properties of the gate oxide, SiO2, which nature has endowed the silicon microelectronics industry with and which has dominated as the favorite and by far most practical choice for FET gate dielectric materials since 1957. SiO2 offers several crucial advantages and industry's acquired knowledge of its properties and processing techniques has allowed its continuous use for the past several decades. However, further scaling the FET is eventually going to be impeded by the inability to further reduce the oxide thickness without risking a breakdown of the device. Recently, however, the thickness of the gate oxide has scaled more slowly compared to its historical pace. An equivalent oxide thickness (EOT) of 1 nm has been used for the past two to three generations because of issues such as process controllability, high leakage current, and reliability limits, signaling an end to the scaling era and the advent of a new era of material and device evolution. As we know, when it is thinned to 1 nm, which corresponds to only 4–5 atom layers, some new technology problems arose [7, 8]. A variation in thickness of only 0.1 nm could result in changes in the device operation condition, making it extremely difficult to maintain device tolerances. As one might imagine, this exponential increase in the gate dielectric leakage current has caused significant concern about the operation of CMOS devices, particularly with regard to standby power dissipation, reliability, and lifetime. This will likely be one if there is no the major contributor leading to the limited extendability of SiO as the gate dielectric in the 1.5–2.0 nm regimes. Therefore, in this chapter, a detailed discussion of current dielectrics and those proposed for future generations is included. Present beliefs regarding the limitations of silicon dioxide as the gate dielectric are reviewed. Ultrathin oxides, with gate dielectrics below 40 Å, some of which are nitrided silicon oxides, are discussed. The benefits and limitations of alternative for new high- materials for possible high-performance CMOS applications are reviewed.