Electrical Overstress (EOS) E-Book

Steven H. Voldman

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 486

Veröffentlichungsjahr: 2013

Beschreibung

Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics.  This bookteaches the fundamentals of electrical overstress  and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design.  It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering the EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today’s modern world.

Look inside for extensive coverage on:

• Fundamentals of  electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA),  to physical models for EOS phenomena
• EOS sources in today’s semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures
• EOS failures in both semiconductor devices, circuits and system
• Discussion of how to distinguish between EOS events, and electrostatic discharge (ESD) events (e.g. such as human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events)
• EOS  protection on-chip design practices and how they differ from ESD protection networks and solutions
• Discussion of EOS system level concerns in printed circuit boards (PCB), and manufacturing equipment
• Examples of EOS issues in state-of-the-art digital, analog and power technologies including CMOS, LDMOS, and BCD
• EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systems
• EOS testing and qualification techniques, and
• Practical off-chip ESD protection and system level solutions to provide more robust systems

Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author’s series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era.

Leseprobe

Contents

Cover

ESD Series

Title Page

Copyright

Dedication

About the Author

Preface

Acknowledgments

Chapter 1: Fundamentals of Electrical Overstress

1.1 Electrical Overstress

1.2 De-Mystifying Electrical Overstress

1.3 Sources of Electrical Overstress

1.4 Misconceptions of Electrical Overstress

1.5 Minimization of Electrical Overstress Sources

1.6 Mitigation of Electrical Overstress

1.7 Signs of Electrical Overstress Damage

1.8 Electrical Overstress and Electrostatic Discharge

1.9 Electromagnetic Interference

1.10 Electromagnetic Compatibility

1.11 Thermal Over-Stress

1.12 Reliability Technology Scaling

1.13 Safe Operating Area

1.14 Summary and Closing Comments

References

Chapter 2: Fundamentals of EOS Models

2.1 Thermal Time Constants

2.2 Pulse Event Time Constants

2.3 Mathematical Methods for EOS

2.4 The Spherical Model – Tasca Derivation

2.5 The One-dimensional Model –Wunsch–Bell Derivation

2.6 The Ash Model

2.7 The Cylindrical Model – The Arkihpov–Astvatsaturyan–Godovosyn–Rudenko Derivation

2.8 The Three-dimensional Parallelepiped Model –Dwyer–Franklin–Campbell Derivation

2.9 The Resistor Model – Smith–Littau Derivation

2.10 Instability

2.11 Electro-migration and Electrical Overstress

2.12 Summary and Closing Comments

References

Chapter 3: EOS, ESD, EMI, EMC and Latchup

3.1 Electrical Overstress Sources

3.2 EOS Failure Mechanisms

3.3 Failure Mechanism – Latchup or EOS?

3.4 Failure Mechanism – Charged Board Model or EOS?

3.5 Summary and Closing Comments

References

Chapter 4: EOS Failure Analysis

4.1 Electrical Overstress Failure Analysis

4.2 EOS Failure Analysis – Choosing the Correct Tool

4.3 Summary and Closing Comments

References

Chapter 5: EOS Testing and Simulation

5.1 Electrostatic Discharge Testing – Component Level

5.2 Transmission Line Pulse Testing

5.3 ESD Testing – System Level

5.4 Electrical Overstress Testing

5.5 EOS Testing – Lightning

5.6 EOS Testing –IEC 61000-4-5

5.7 EOS Testing – Transmission Line Pulse Method and EOS

5.8 EOS Testing –D.C. and Transient Latchup

5.9 EOS Testing – Scanning Methodologies

5.10 Summary and Closing Comments

References

Chapter 6: EOS Robustness – Semiconductor Technologies

6.1 EOS and CMOS Technology

6.2 EOS and RF CMOS and Bipolar Technology

6.3 EOS and LDMOS Power Technology

6.4 Summary and Closing Comments

References

Chapter 7: EOS Design – Chip Level Design and Floor Planning

7.1 EOS and ESD Co-Synthesis – How to Design for Both EOS and ESD

7.2 Product Definition Flow and Technology Evaluation

7.3 EOS Product Definition Flow – Constant Reliability Scaling

7.4 EOS Product Definition Flow – Bottom Up Design

7.5 EOS Product Definition Flow – Top Down Design

7.6 On-Chip EOS Considerations – Bond Pad and Bond Wire Design

7.7 EOS Peripheral I/O Floor Planning

7.8 EOS Chip Power Grid Design –IEC Specification Power Grid and Interconnect Design Considerations

7.9 Printed Circuit Board Design

7.10 Summary and Closing Comments

References

Chapter 8: EOS Design – Chip Level Circuit Design

8.1 EOS Protection Devices

8.2 EOS Protection Device Classification Characteristics

8.3 EOS Protection Device – Directionality

8.4 EOS Protection Device Classification –I-V Characteristic Type

8.5 EOS Protection Device Design Window

8.6 EOS Protection Device – Types of Voltage Suppression Devices

8.7 EOS Protection Device – Types of Current Limiting Devices

8.8 EOS Protection – Across Board Supply and Ground Plane Using a Transient Voltage Suppression Device and Schottky Diodes

8.9 EOS and ESD Protection Co-Synthesis Network

8.10 Co-Synthesis of EOS in Cables and PCBs

8.11 Summary and Closing Comments

References

Chapter 9: EOS Prevention and Control

9.1 Controlling EOS

9.2 EOS Minimization

9.3 EOS Minimization – Preventive Actions in the Design Process

9.4 EOS Prevention –EOS Guidelines and Procedures

9.5 EOS Prevention – Ground Testing

9.6 EOS Prevention – Connectivity

9.7 EOS Prevention – Insertion

9.8 EOS and Electromagnetic Interference Prevention – Printed Circuit Board Design

9.9 EOS Prevention – Desktop Boards

9.10 EOS Prevention – On-Board and On-Chip Design Solutions

9.11 High Performance Serial Buses and EOS

9.12 Summary and Closing Comments

References

Chapter 10: EOS Design – Electronic Design Automation

10.1 EOS and Electronic Design Automation

10.2 EOS and ESD Design Rule Checking

10.3 EOS Electronic Design Automation

10.4 Printed Circuit Board Design Checking and Verification

10.5 EOS and Latchup Design Rule Checking

10.6 Summary and Closing Comments

References

Chapter 11: EOS Program Management

11.1 EOS Audits and Manufacturing Control

11.2 Controlling EOS in the Production Process

11.3 EOS and Assembly Plant Corrective Actions

11.4 EOS Audits – From Manufacturing to Assembly Control

11.5 EOS Program – Weekly, Monthly, Quarterly, to Annual Audits

11.6 EOS and ESD Design Release

11.7 EOS Design, Testing and Qualification

11.8 Summary and Closing Comments

References

Chapter 12: Electrical Overstress in Future Technologies

12.1 EOS Future Implications for Future Technologies

12.2 EOS in Advanced CMOS Technology

12.3 EOS Implications in 2.5-D and 3-D Systems

12.4 EOS and Magnetic Recording

12.5 EOS and Micro-Machines

12.6 EOS and RF MEMs

12.7 EOS Implications for Nano-Structures

12.8 Summary and Closing Comments

References

Appendix A: Glossary of Terms

Appendix B: Standards

Index

ESD SeriesBy Steven H. Voldman

Electrical Overstress (EOS): Devices, Circuits and Systems

ISBN: 9781118511886

September 2013

ESD Basics: From Semiconductor Manufacturing to Product Use

ISBN: 9780470979716

October 2012

ESD: Design and Synthesis

ISBN: 9780470685716

March 2011

ESD: Failure Mechanisms and Models

ISBN: 9780470511374

July 2009

Latchup

ISBN: 9780470016428

December 2007

ESD: RF Technology and Circuits

ISBN: 9780470847558

September 2006

ESD: Circuits and Devices

ISBN: 9780470847541

November 2005

ESD: Physics and Devices

ISBN: 9780470847534

September 2004

Upcoming titles:

ESD: Test and Characterization

The ESD Handbook

ESD: Analog Circuits and Design

This edition first published 2014

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Library of Congress Cataloging-in-Publication Data

Voldman, Steven H.

Electrical overstress (EOS) : devices, circuits, and systems / Steven Voldman.

pages cm

Includes bibliographical references and index.

ISBN 978-1-118-51188-6 (hardback)

1. Semiconductors—Failures. 2. Semiconductors—Protection. 3. Transients (Electricity) 4. Overvoltage. I. Title.

TK7871.852.V648 2013

621.3815—dc23

2013022183

A catalogue record for this book is available from the British Library.

ISBN: 978-1-118-51188-6

To My Mother's Sister

My Aunt

Saundra “Sunny” Braitman

About the Author

Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He received his B.S. in Engineering Science from University of Buffalo (1979), a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT), a second degree EE Degree (Engineer Degree) from MIT, a MS Engineering Physics (1986), and a Ph.D in electrical engineering (EE; 1991) from University of Vermont under IBM's Resident Study Fellow program.

He was a member of the IBM development for 25 years, working on semiconductor device physics, device design, and reliability e.g., soft error rate (SER), hot electrons, leakage mechanisms, latchup, electrostatic discharge (ESD), and electrical overstress (EOS). Voldman has been involved in latchup technology development for 30 years. He worked on both the technology and product development in Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS, Silicon Germanium (SiGe), RF CMOS, RF SOI, smart power, and image processing technologies. In 2007, Voldman was a member of the Qimonda DRAM development team, working on 70, 58, and 48 nm CMOS technology. In 2008, he initiated a limited liability corporation (LLC), and he worked at headquarters in Hsinchu, Taiwan, for Taiwan Semiconductor Manufacturing Corporation (TSMC) as part of the 45 nm ESD and latchup development team. He was a Senior Principal Engineer working for the Intersil Corporation on ESD and latchup development from 2009 to 2011. Since 2011, he is presently independent under Dr. Steven H. Voldman LLC, providing consulting, teaching, and patent litigation expert witness support. He is presently a consultant for Samsung Electronics in Dongtan, South Korea, working on sub-20 nm technology.

Steve Voldman was chairman of the SEMATECH ESD Working Group from 1995 to 2000. In his SEMATECH Working Group, the effort focused on ESD technology benchmarking, the first transmission line pulse (TLP) standard development team, strategic planning, and the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2012, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP. He has been a member of the ESD Association Board of Directors, and Education Committee.

Steve Voldman initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, South Korea, India, and China.

He teaches short courses and tutorials on ESD, latchup, patenting, and invention in the United States, China, Singapore, Malaysia, Taiwan, Sri Lanka and Israel. He is a recipient of over 245 issued US patents, in the area of ESD and CMOS latchup.

Since 2007, he has served as an expert witness in patent litigation in over six litigation cases, associated with CMOS development, DRAM development, silicon-on-insulator, semiconductor devices, ESD, and latchup.

Steve Voldman has written articles for Scientific American and is author of the first book series on ESD, latchup, and EOS: ESD: Physics and Devices, ESD: Circuits and Devices, ESD : RFTechnology and Circuits, Latchup, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, and ESD Basics: From Semiconductor Manufacturing to Product Use and this text, Electrical Overstress (EOS): Devices, Circuits and Systems. He is also a contributor to the books Silicon Germanium: Technology, Modeling and Design and Nanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, the International Chinese editions of the book ESD: Circuits and Devices and ESD : RFTechnology and Circuit are released as well as others in the near future.

Preface

This text, Electrical Overstress(EOS): Devices, Circuits and Systems was initiated based on the need to produce a text that addresses the fundamentals of electrical overstress (EOS) from the manufacturing environment, devices, components and systems. An understanding of the source of EOS, how to identify EOS, and provide EOS robust products are needed in today's electronic industry. As the manufacturing world evolves, semiconductor networks scale, and systems are changing, the needs and requirements for reliability and EOS robust products are changing. A text is required that connects basic EOS phenomena to today's real world environment.

Whereas significant texts are available today to teach experts on electrostatic discharge (ESD) on-chip design, there is a need for a fundamental understanding of EOS. This is necessary for expert, non-expert, non-technical, and layman to understand the problems facing the world today. Today, real world EOS issues surround us; this occurs in manufacturing environment, power sources, machinery, actuators, solenoids, soldering irons, cables, to lightning. When there is switching, poor grounding, ground loops, noise, and transient phenomena, there will be a potential for EOS of devices, components, and printed circuit boards. Hence, there is a need for experts and non-experts to understand what the issues that revolve around us are, and what we do to avoid them.

One of the key problems with this topic is the perception that EOS is difficult to quantify and define. This perception was also true in the early days of ESD development. As a result, there have been no textbooks on EOS at this date, and yet it is understood that a significant percentage of system and product field returns is EOS related.

A second key problem is the belief that it is difficult to distinguish ESD failures from EOS. The reason that this distinction is important is to define the root cause of the device, component, or system failures. As a result, in this text, this will be re-emphasized.

A third key problem is that the techniques and methods to provide both EOS and ESD robust products in the same lecture, tutorial, source, or textbook is never synthesized in one discussion. This is also true that the discussion and training on electromagnetic compatibility (EMC) and ESD are typically taught separately.

This text has multiple goals.

The first goal of the text is to teach the basics and concepts of EOS and relate them to real world processes in semiconductor manufacturing, handling, and assembly.

The second goal of the text is to provide a strong technical base for quantification of EOS, highlighting both mathematical and physical analysis. In this fashion, it is critical to understand the role and relationship of thermal physics.

The third goal of the text is to draw a distinction between EOS and ESD. This will be achieved by focusing on the pulse waveform and time scales. The text will constantly reinforce this distinction through the sources, to the mathematical models.

The fourth goal is to discuss the inter-relationship to other disciplines, such as electromagnetic interference (EMI), electromagnetic compatibility (EMC), and latchup.

The fifth goal is to expose the reader to EOS testing and standards of both semiconductor chips and systems. In this section, we will again distinguish between the EOS and ESD tests and standards.

The fifth goal is to demonstrate how to protect semiconductor chips and systems from EOS.

The sixth goal is to demonstrate how to protect semiconductor chips and systems from both EOS and ESD events.

The seventh goal is to teach EOS issues in different technology types for digital, analog, and power electronics.

The eighth goal is to highlight electrical design automation (EDA) methods to provide EOS robust products. In this section, we will again draw distinctions of EDA solutions for EOS, ESD, and latchup.

The ninth goal is to discuss an EOS program management for manufacturing environments from measurements to audits, to insure an EOS Protected Area.

The tenth goal is to provide a glimpse into the present and future with new nano-structures and nano-systems that lie ahead. This will provide insight in what will be needed in the future, as well as the magnitude of the EOS concern in coming years.

This text, Electrical Overstress(EOS): Devices, Circuits and Systems contains the following:

Chapter 1 introduces the reader to an overview of the language and fundamentals associated with EOS. In Chapter 1, the foundation for a discussion of EOS is established. Chapter 1 opens the dialog of defining EOS and its relationship to other phenomena, such as electrostatic discharge (ESD), electromagnetic interference (EMI), electromagnetic compatibility (EMC), and latchup. EOS is defined as well in terms of electrical over-current, electrical over-power, and other concepts. In our discussion, there is an emphasis on distinguishing EOS from ESD. As a result, I will draw distinctions through the text on difference of failure analysis, time constants, and other means of identification and classification. A plan to define safe operating area (SOA) and its role in EOS is also emphasized.

In Chapter 2, the physical and mathematical basis for understanding EOS is provided. In Chapter 2, the goal is to demonstrate the mathematics and physical models associated with power-to-failure, time constants, and materials. This chapter will provide the tools necessary to understand the equations and physical limits of the electrothermal models derived in the past. A key distinction in this chapter, the ESD time regime from the EOS time regime will be identified to draw attention to the different power-to-failure solutions for these processes. The primary reason for this in-depth discussion is to demonstrate that EOS phenomena can be quantified and understood – which confronts the skeptics that this is not a science which is quantifiable. In the next chapter, we will allow you to recover from the rigor of this chapter, provide practical connection to the real world, and catch your breath.

In Chapter 3, the text's focus returns to a practical discussion on the sources and failure mechanisms associated with EOS. The sources will include machinery, solenoids, actuators, to cables and lightning. EOS failure mechanisms from device component failures, bond pads, bond wires, and packaging are identified. In this chapter, some focus on EOS specific failures from ESD are again be highlighted.

Chapter 4 focuses on EOS failure mechanisms and failure analysis. The chapter highlights failure analysis process, failure analysis techniques, and tools. Failure mechanism examples are shown from the different failure analysis tool results of both EOS and ESD failures.

In Chapter 5, EOS and ESD testing techniques and testing standards are discussed. EOS testing methods discussed include system level tests, such as IEC 61000-4-2, and transient surge standards relevant to EOS (IEC 61000-4-5). The chapter also discusses the ESD tests and standards, such as the human body model (HBM), machine model (MM), charged device model (CDM), transmission line pulse (TLP), very-fast transmission line pulse (VF-TLP), as well as system-like testing. System-like testing begins to transition toward EOS phenomena, (e.g., cable discharge event; CDE) and hence will be part of our discussion on testing.

Chapter 6 discusses EOS in different semiconductor technologies from CMOS, bipolar, LDMOS, to bipolar-CMOS-DMOS (BCD) technologies and the issues that arise in the different application spaces. A focus will be on how the technologies can address power and EOS robustness issues.

The focus in Chapter 7 is EOS design. A key question that arises is, ‘how does EOS design differ from ESD design?’. A second key question is, ‘how do you design for both ESD and EOS in a given chip or system design?’. This chapter includes product definition, specifications, technology identification, to both top-down and bottom-up design methodologies and floor planning. It also shows usage of circuit design to address over-current and over-temperature controls.

In Chapter 8, EOS protection devices are discussed. These include a plethora of elements from snapback devices to voltage triggered devices. EOS protection is achieved using transient voltage suppression (TVS), thyristor surge protection devices (TSPD), metal oxide varistors (MOV), conductive polymers, gas discharge tubes (GDT), fuses, circuit breakers, and other elements. These EOS protection elements are very distinct from those employed for ESD protection.

In Chapter 9, system level problems and solutions are discussed. The focus is on EOS control in the production and manufacturing environment. The chapter addresses preventive actions, controlling the back end process, to product area operations.

In Chapter 10, electronic design automation (EDA) techniques and methods for EOS are discussed. Design rule checking (DRC), layout versus schematic (LVS), to electrical rule checking (ERC) methods are used for both ESD and EOS checking and verification. In this chapter, methods being applied today for EOS environments are shown.

In Chapter 11, an EOS program management process is discussed. The chapter will demonstrate topics on design reviews, checklists, corrective actions, audits, and the design release process to guarantee EOS robust products.

In Chapter 12, EOS in future structures and nano-devices is discussed. The chapter discusses EOS issues in magnetic recording, FinFETs, graphene, carbon nano-tubes, to phase change memory. This concluding chapter takes a look at micro-motors, micro-mirrors, RF MEM switches, and many novel devices. EOS in silicon interposers and through silicon via (TSV) in 2.5-D and 3-D systems is also highlighted.

This introductory text will hopefully open your interest in the field of electrical overstress (EOS), electrostatic discharge (ESD), electromagnetic interference (EMI), and electromagnetic compatibility (EMC) – and teach how it relates to today's world. To establish a stronger knowledge of ESD protection, it is advisable to read the other texts ESD Basics: From Semiconductor Manufacturing to Product Use, ESD: Physics and Devices, ESD: Circuits and Technology, ESD: RF Circuits and Technology, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, and Latchup.

Enjoy the text, and enjoy the subject of EOS – just do not get stressed out over electrical overstress (EOS).

Baruch HaShem

Dr. Steven H. Voldman

IEEE Fellow

Acknowledgments

I would like to thank the years of support from the SEMATECH, the ESD Association, the IEEE, and the JEDEC organizations. I would like to thank the IBM Corporation, Qimonda Corporation, Taiwan Semiconductor Manufacturing Corporation (TSMC), the Intersil Corporation, and the Samsung Corporation. I was fortunate to work in a wide number of technology teams, and with a wide breadth of customers. I was very fortunate to be a member of talented technology and design teams that were both innovative, intelligent, and inventive.

I would like to thank the institutions that allowed me to teach and lecture at conferences, symposiums, industry, and universities; this gave me the motivation to develop the texts. I would like to thank faculty at the following universities: M.I.T., Stanford University, University of Central Florida (UCF), University Illinois Urbana–Champaign (UIUC), University of California Riverside (UCR), University of Buffalo, National Chiao Tung University (NCTU), Tsin Hua University, National Technical University of Science and Technology (NTUST), National University of Singapore (NUS), Nanyang Technical University (NTU), Beijing University, Fudan University, Shanghai Jiao Tung University, Zheijang University, Huazhong University of Science and Technology (HUST), UESTC, Universiti Sains Malaysia (USM), Universiti Putra Malaysia (UPM), Kolej Damansara Utama (KDU), Chulalongkorn University, Mahanakorn University, Kasetsart University, Thammasat University, Korea University, and Mapua Institute of Technology (MIT).

I would like to thank for the years of support and the opportunity to provide lectures, invited talks, and tutorials the Electrical Overstress/Electrostatic Discharge(EOS/ESD) Symposium, the International Reliability Physics Symposium(IRPS), the Taiwan Electrostatic Discharge Conference(T-ESDC), the International Electron Device Meeting(IEDM), the International Conference on Solid-State and Integrated Circuit Technology(ICSICT), the International Physical and Failure Analysis(IPFA), IEEE ASICON, and the IEEEIntelligent Signal Processing And Communication Systems (ISPACS) Conference.

I would like to thank my many friends for 22 years in the ESD profession – Prof. Ming Dou Ker, Prof. J.J. Liou, Prof. Albert Wang, Prof. Elyse Rosenbaum, Timothy J. Maloney, Charvaka Duvvury, Eugene Worley, Robert Ashton, Yehuda Smooha, Vladislav Vashchenko, Ann Concannon, Albert Wallash, Vessilin Vassilev, Warren Anderson, Marie Denison, Alan Righter, Andrew Olney, Bruce Atwood, Jon Barth, Evan Grund, David Bennett, Tom Meuse, Michael Hopkins, Yoon Huh, Jin Min, Jeffrey Dunnihoo, Keichi Hasegawa, Teruo Suzuki, Han Gu Kim, Kitae Lee, Nathan Peachey, Kathy Muhonen, Augusto Tazzoli, Gaudenzio Menneghesso, Marise BaFleur, Jeremy Smith, Nisha Ram, Swee K. Lau, Tom Diep, Lifang Lou, Stephen Beebe, Michael Chaine, Pee Ya Tan, Theo Smedes, Markus Mergens, Christian Russ, Harold Gossner, Wolfgang Stadler, Ming Hsiang Song, J.C. Tseng, J.H. Lee, Michael Wu, Erin Liao, Stephen Gaul, Jean-Michel Tschann, Tze Wee Chen, Shu Qing Cao, Slavica Malobabic, David Ellis, Blerina Aliaj, Lin Lin, David Swenson, Donn Bellmore, Ed Chase, Doug Smith, W. Greason, Stephen Halperin, Tom Albano, Ted Dangelmayer, Terry Welsher, John Kinnear, and Ron Gibson.

I would like to thank the ESD Association office for their support in the area of publications, standards developments, and conference activities. I would also like to thank the publisher and staff of John Wiley & Sons for including this text as part of the ESD book series.

To my children, Aaron Samuel Voldman, and Rachel Pesha Voldman, good luck to both of you in the future.

To my wife Annie Brown Voldman – thank you for the support of years of work.

And to my parents, Carl and Blossom Voldman.

Baruch HaShem

Dr. Steven H. Voldman

IEEE Fellow

1

Fundamentals of Electrical Overstress

FUSE-BLOCK

“To all whom it may concern:

Be it known that I, THOMAS A. EDISON, of Menlo Park, in the county of Middlesex and State of New Jersey, have invented a certain new and useful Improvement in Lightning Arresters (Case No. 644,) of which the following is a specification.

My invention relates to fusible safety-catches or lightning-protections for telephones, telegraph, and similar circuits in which the fusible wire is placed in an inclosing shell or chamber of insulating material; and my object is to prevent or diminish the liability to surface creeping of lightning or other powerful current…”

United States Patent OfficePatent No. 438,30514 October 1890

Electrical overstress (EOS) has been an issue with the coming of the electrical age, when electricity and electrical product were first introduced into the mainstream of society. With the introduction of electrical power systems, the telephone, and electronics, inventions such as circuit breakers and fuses became the first type of electrical overstress protection concepts to avoid over-load of electronic systems.

In this text, electrical overstress (EOS) will be addressed for the modern age of new devices, components, and systems. We will first visit the 1970s where the interest in EOS arose due to a growing interest in the reliability and quality of components and systems. In the end of the text, we will arrive at the future of “Nano-EOS”– EOS in nanotechnologies.

1.1 Electrical Overstress

Electrical overstress (EOS) has been an issue in devices, circuit and systems for electronics for many decades, as early as the 1970s [1–12], and continues to be an issue today [13–83]. Market segments from consumer, industrial, aerospace, military, and medical are all influenced by this issue. The experience of EOS failures occurs at the device manufacturer, supplier, assembly, and the field. In the electronic industry, many products and applications are returned from the field due to “EOS” failure. To make progress in addressing the EOS issue, it is important to provide a framework for the evaluation and analysis of EOS phenomena. As part of this framework, it is important to apply a vocabulary and definitions. It is key to apply both physical and mathematical definitions to quantify the EOS conditions. It is equally important to establish a methodology of failure analysis and testing. It is also critical to establish an awareness of the origins and sources of EOS concerns. In the end, to provide better EOS robust products, it is important to define design practices and procedures, as well as EOS control programs for manufacturing and production areas.

1.1.1 The Cost of Electrical Overstress

One of the key concerns of EOS is the cost. There are different types of costs associated with EOS. In this section, the cost associated with field returns will be discussed. In order to quantify the cost of EOS events on products, it is critical to categorize what percentage of field returns are in fact EOS related.

1.1.2 Product Field Returns – The Percentage that is Electrical Overstress

Product field returns occur in all electronic components independent of the technology generation and period of time of evaluation. One of the key difficulties in the semiconductor industry is the ability to track, record, and maintain a database of these field failures.

A key question in the electronic industry is what is the percentage of the field returns that is due to electrical overstress (EOS)?

In the mid-1980s, the military established an in-house program to track, record, and categorize field failures to answer this question [49]. The United States military and the Reliability Analysis Center (RAC) in Rome, N.Y., jointly established the Field Failure Return Program (FFRP), with the objective of providing feedback to the semiconductor industry, and determine the root cause of failure. With establishing the root cause of failure, the corrective action can be initiated. The FFRP goals were as follows [49]:

Identify high failure rate, or component problems.Identify their root causes of failure from failure analysisFeedback the information to the supplier, industry, or government organization for corrective action.

In this early reliability study, data from 24 different systems was collected and reviewed. In this review, 1650 parts were evaluated, of which the part numbers were from actual field failures that were operational from two to 10 years. Table 1.1 shows the results of the field failure categories [49].

Table 1.1 Field failure categories and percentages.

Field failure categoryField Failures (%)Electrical overstress (EOS)46IC design, fabrication, and assembly25Retested without observed failure17Electrostatic discharge (ESD)6EOS or ESD6

From this study, 46% of the field returns were associated with electrical overstress (EOS). It was regarded from this study that a number of EOS issues were associated with poor system design, improper maintenance procedures, and improper operational procedures. In the second category, it was regarded that these failures were from inherent flaws and latent defects. Of the field returns, only a small percentage was related to electrostatic discharge (ESD). Note that in some cases it was decided that it was not possible to determine if the failures were EOS or ESD (Figure 1.1).

Figure 1.1 Failure categories pie chart

The results of this study are not significantly distinct from other future studies. It is typically quoted that EOS is a high percentage of field failures, and a certain percentage cannot distinguish EOS from ESD.

In more recent studies, C. Thienel's study for the automotive industry called “Avoiding electrical overstress for automotive semiconductors by new connecting concepts,” attributed 6% of the failures to ESD and 94% were associated with EOS [77,79,80]. A large percentage of the fails were “no defect found” and approximately 32% were EOS/ESD failures.

1.1.3 Product Field Returns – No Defect Found versus Electrical Overstress

In practice, product field returns are sent from the customers back to the source of production. These “field returns” come back to the quality organization, where the root cause of the field failure is diagnosed. A large percentage of the field returns are labeled “no defect found” (NDF) when the root cause cannot be observed. It is well known that many of the field returns are electrical overstress (EOS) related.

1.1.4 Product Failures – Failures in Integrated Circuits

Failures occur in the production of integrated circuits (IC) impacting yield. Studies have shown that the impact to IC productions from electrical overstress (EOS) and electrostatic discharge (ESD) can be up to 37% of the product failures (Table 1.2) [49]. In this study, it was found that 25% of the product failures were associated with fabrication. For the assembly process, it was found that the magnitude of yield loss was on the order of 12%, and another 12% was unknown. These percentages are dependent on the technology and controls in the foundry, but provide use with a view of the impacts of the various issues that accompanies yield loss.

Table 1.2 Failures in IC production.

Cause of yield lossPercentage (%)Electrostatic discharge/electrical overstress37Fabrication25Assembly12Unknown12

In this chapter, some fundamental definitions will be introduced and concepts to open the discussion of (EOS). In future chapters, the text will proceed with the aforementioned topics of EOS.

1.1.5 Classification of Electrical Overstress Events

Electrical overstress (EOS) is such a broad spectrum of phenomena, it is important to establish classifications of EOS. The definition of EOS includes electrical response to current, voltage, and power.

Electrical phenomena is categorized into different definitions, which will be discussed in depth in future sections. Common categorization include electrostatic discharge (ESD), electromagnetic interference (EMI), electromagnetic compatibility (EMC), and latchup issues (Figure 1.2) [84–89]. At times, all of these are included in the definition of EOS; yet others separate these categories as separate items to distinguish them for the purpose of determining cause–effect relationships, as well as root cause. For example, although ESD is a form of EOS, it is established in the semiconductor industry to distinguish them. One of the reasons this is done is due to determining the root cause of failure.

Figure 1.2 EOS, ESD, EMI, EMC, and latchup

Electrical overstress (EOS) cause and effect for integrated circuits can be the following [80]:

Electrostatic discharge (ESD)LatchupElectromagnetic interference (EMI)Electromagnetic compatibility (EMC)Misapplication.

For ESD phenomena, there exists event models for the component and system levels. For component-level ESD, failures can be associated with human body model (HBM), machine model (MM), charged device model (CDM), and human metal model (HMM) [84–86,88–91]. For system-level ESD, failures can be associated with charged board model (CBM) and cable discharge event (CDE) [84–86,88–90].

For latchup, there exists causes associated with direct current (d.c.) and transient phenomena [87]. Direct current latchup events can be in the form of “internal latchup” and “external latchup.” Transient latchup is also the initiation of latchup from a transient voltage event.

For electromagnetic interference, EOS events can occur from the following [80]:

NoiseSurge currentsSlow voltage transientsFast voltage transientsRadio frequency (RF) signals.

For the EMI events, there are causes for noise, surge currents, transients, and RF interference. Noise can be a result of lack of proper filters and switching events. Surge currents can occur due to poor electrical isolation and switching of capacitors. Voltage transients can occur due to the power-up and power-down of printed circuit boards and integrated circuits (ICs). Inductive switching is also a transient voltage concern. Radio frequency (RF) interference can be a concern from lack of filters, lack of shielding, shielding openings, and the printed circuit board (PCB) design quality [73,80].

Human error and misapplication is a large cause of EOS events. This can happen in the following forms:

System designImproper testingImproper assemblySpecification violation.

EOS can be a result of poor system design [73,80]. System design can be both hardware or software. Improper or inadequate design of both the electrical and thermal properties can lead to electrical overstress.

EOS events can be the result of improper testing [73,80]. Human error from incomplete tests, hot swapping, switching of components, to over-voltage or over-current application to components, to inadequate margins can lead to overstress. Over-voltage can also occur in the test equipment sources themselves due to noise, transient spikes, and other poor quality test environments.

Improper assembly and human error can also be the cause of EOS issues. In the assembly process, mis-orientation, mis-insertion, reverse insertion, and assembly of powered or un-powered states can lead to electrical overstress.

In addition, electrical specifications can be violated due to defective hardware (e.g., opens and shorts), poor electrical contacts, poor ground connections, and overheating.

Throughout the text, these issues will be re-emphasized, repeated, and addressed in detail. To continue with our discussion, more definitions will be established in this chapter.

1.1.6 Electrical Over-Current

There are different forms of electrical overstress (EOS). In electrical conditions that are in excess of the intended or application current, devices, components, or systems can undergo latent or permanent damage; this condition can be defined as electrical over-current (EOC).

When EOC occurs, electronic components can have excessive Joule heating, material property changes, melting, or fire. Electrical over-current (EOC) is one classification of EOS. Electrical over-current (EOC) can be prevented by electrical fuses, temperature sensing circuitry, and current-limiting EOS protection devices.

1.1.7 Electrical Over-Voltage

In electrical conditions that are in excess of the intended or application voltage, devices, components, or systems can undergo latent or permanent damage; this condition can be defined as electrical over-voltage (EOV). When EOV occurs, electronic components can undergo different conditions. Electrical overvoltage (EOV) can lead to electrical breakdown of dielectrics, semiconductors, and conductors. Electrical over-voltage (EOV) is a second classification of EOS.

Electrical over-voltage (EOV) can be prevented by voltage-limiting EOS protection devices, and electrostatic discharge (ESD) protection circuits.

1.1.8 Electrical Over-Power

In electrical conditions that are in excess of the intended or application current, voltage or power, devices, components, or systems can undergo latent or permanent damage; this condition can be defined as electrical over-power (EOP). Electrical over-power (EOP) is a concern when the power exceeds the power-to-failure, Pf. Electrical over-power (EOP) is a third classification of EOS. Electrical over-power (EOP) can be prevented by utilizing over-voltage voltage-limiting EOS protection circuits, current-limiting EOS protection devices, fuses, and other circuit solutions.

1.2 De-Mystifying Electrical Overstress

Electrical overstress (EOS) is regarded as a difficult issue to define. This belief has led to a slow growth of the EOS discipline definition and quantification. This was also true for the electrostatic discharge (ESD) discipline; in early days, it was regarded as “black magic” and a subject that could not be quantified. After three decades of development and research, the ESD discipline has been quantified and understood. This has led to a number of standards in industry for the qualification of semiconductor components.

Likewise, the EOS field requires “de-mystification” to establish continued understanding, quantification, and establishment. The steps for quantification will require an increased understanding of the following:

Failure mechanisms understanding and categorizationPhysical modelsCircuit and system circuit modelsEOS test methods and standardsEOS protection devicesEOS design proceduresEOS design rule checking (DRC)EOS layout versus schematic (LVS) verificationEOS electrical rule checking (ERC) developmentEOS qualification release processEOS certification of EOS protected areas (EOS-PA)EOS program management and auditing.

1.2.1 Electrical Overstress Events

Electrical overstress (EOS) can occur within manufacturing environments, production areas, and in the field [73]. EOS events can occur internal or external of electronic systems. External sources can be associated with voltage sources, current sources, and phenomena associated with inductive, capacitance, or resistive components. The phenomena can be direct current (d.c.), alternating current (a.c.), or transient phenomena.

Examples of different external sources of EOS events can include the following:

Inductance: Inductive loadsCapacitive: Cable capacitance chargeResistive: Ground resistance.

Electronic noise in different forms is also a key cause of EOS events. Noise events, both internal and external, can create component failures. Example of noise events include the following:

External Switching Noise: Switching noise on antennasExternal Ground Plane Noise: Noise on ground plane or current returnExternal electromagnetic interference (EMI): EMI noise due to poor shieldingInternal Switching I/O Noise: Sequential switching of digital I/O off-chip driver circuitryInternal Switching Clock Noise: Switching of timing clocksInternal I/O Transients: Overshoot and undershoot.

Electrical overstress (EOS) phenomena also comes in different categorizes. For example, CMOS latchup is particular form of an EOS event associated with parasitic devices within a chip leading to thermal runaway and destruction.

1.3 Sources of Electrical Overstress

Electrical overstress (EOS) can occur in many different environments. EOS can occur in manufacturing, production, and assembly environments.

1.3.1 Sources of Electrical Overstress in Manufacturing Environment

Electrical overstress (EOS) is a concern in the manufacturing environment. A key source of electrical overstress is the power line (e.g., also known as grid power, or mains). Power-line EOS from the power grid is due to the following reasons (Figure 1.3) [73]:

Poor wiring schemesLack of adequate groundingGround loops.

Figure 1.3 Power line EOS

Mains-caused alternating current (a.c.) EOS events can occur to both voltage induction and current induction. In addition, there is direct current (d.c.) caused electrical overstress in manufacturing environments [73].

1.3.1.1 Alternating Current Electrical Overstress

For alternating current (a.c.) voltage induction, it has been shown that a.c. signals exists on power lines up to 2.3 V. A strong relationship exists between the ground impedance and in voltage induced a.c. voltage inside the manufacturing tooling. One example of how manufacturing environments can lead to this voltage-induction concern is when the neutral and ground wires are reversed.

For alternating current (a.c.) current induction, motors and high transient currents within a tool generate magnetic fields. The magnetic fields can induce both voltages and currents within adjacent wiring and wiring loops.

1.3.1.2 Direct Current Electrical Overstress

In a manufacturing environment, there are direct current (d.c.) motors in equipment. Low voltage d.c. motors have the negative terminal connected to a chassis, which establishes the return path for the current through the d.c. motor. The resistance drop through the chassis of the tool can lead to a differential voltage between the chassis and the true ground of the motor. This differential voltage between the chassis and the ground can lead to a low voltage EOS event.

1.3.1.3 High Frequency Noise

Switches, solenoids, relays, variable frequency motors, and other tools can generate electromagnetic interference (EMI) [73]. EMI events can induce a voltage on components, leading to EOS. EMI-induced EOS events can occur in the magnetic recording industry and future nano-structures.

1.3.2 Sources of Electrical Overstress in Production Environments

Electrical overstress (EOS) is a concern in the manufacturing area, as well as the production environment. In production environments, sources of EOS events are soldering irons, power tools, and power supply commutation [73].

In soldering irons, EOS events can occur due to the following:

Loss of ground connectionNoise on the ground lineNoise on the power lineTransient switching spikesSolder iron tip oxidation.

In power tools, EOS events can occur due to improper grounding. For example, power tools used in production environment that can cause EOS events are screwdrivers. Screwdrivers tips have both oxidizing films and insulating barriers between the ground line and the screwdriver tip. Lack of good connections to the true ground can lead to EOS events.

A third source of EOS events is power supply commutation. Power supply commutation is the process of transferring current from one connection to another within an electric circuit; this is achieved typically by an electronic “switch.” In power converter circuits, there is a significant number of EOS spikes that occur in the production environment during power commutation.

1.4 Misconceptions of Electrical Overstress

In the field of electrical overstress (EOS), there are many misconceptions [80]. This was also true for the field of electrostatic discharge (ESD) between 1970 to the mid-1990s. In the field of ESD protection, examples of some of the typical misconceptions were as follows:

Current Path Misconception: All the ESD current will flow into the ESD protection device and no current flows into the input/output (I/O) circuitry.ESD Failure: During an ESD event, the failing structure is always the ESD protection circuit.ESD Circuitry Placement: The ESD network must be placed next to the bond pad.Charged Device Model: All CDM failures are on receiver gate structures.

In the field of EOS, equivalently, there are also many similar misconceptions. Here are a few examples of misconceptions about EOS phenomena [80]:

EOS Current Path: The current path for all types of EOS events is the same within a printed circuit board and an integrated circuit component.EOS Failure Location: The failure damage location for all types of EOS events is the same.EOS Equal Response: Specific parts of an integrated circuit responds equally to different types of EOS events.EOS IC Response: EOS response is independent of its operational mode.EOS Response Proportionality: The response of an integrated circuit to an EOS event is linearly proportional to the EOS event magnitude.

1.5 Minimization of Electrical Overstress Sources

A solution to addressing electrical overstress (EOS) is to minimize both the sources of EOS. The EOS cause and effect for integrated circuits can be the following:

Electrostatic discharge (ESD) [84–90]Latchup [87]Electromagnetic interference (EMI) [93–115]Electromagnetic compatibility (EMC) [93–115]Misapplication.

With a focus on the minimizing the impact of ESD, latchup, EMI, EMC, and misapplication, EOS failure can be reduced. This can be achieved through semiconductor technology robustness, circuit design, printed circuit board design, electrical isolation, transient minimization, shielding, filters, test procedures, handling, and auditing controls.

1.6 Mitigation of Electrical Overstress

A solution to mitigate electrical overstress (EOS) failure is to have an EOS Mitigation Strategy [80]. An EOS Mitigation Strategy can include independent design of integrated circuits, or a co-design strategy that plans the printed circuit board design, placement of the components, and integrated circuit design jointly.

An EOS Mitigation Strategy for the system is as follows [80]:

ESD discharge controlCurrent loop reduction for noise minimizationShieldingNoise filtersConnector designEOS on-board voltage-limiting devicesEOS on-board current-limiting devicesDecoupling capacitorsLow effective series resistance (ESR) capacitorsLow effective series inductor (ESL) capacitorsPrinted circuit board (PCB) EMC compliant design.

An EOS Mitigation Strategy for the components are as follows [80]:

Increased voltage toleranceVoltage clampsDecoupling capacitorsDe-coupling of cross-component parasiticEOS on-chip voltage-limiting devicesEOS on-chip current-limiting devicesIntegrated circuit (IC) EMC compliant design.

1.7 Signs of Electrical Overstress Damage

After an electrical overstress (EOS) event, there are different means of verification [92]. One way to determine that there was an EOS event is the electrical signature. A second sign is the visual signature.

1.7.1 Signs of Electrical Overstress Damage – The Electrical Signature

After an electrical overstress (EOS) event, there are different means of verification. One way to determine that there was an EOS event is the electrical signature [92]. Evaluation of the electrical characteristics can be an indicator of an EOS event. Some of the EOS event electrical characteristics are as follows (Figure 1.4):

Electrical open (open connections)Electrical short of signal pin to power rail (VDD)Electrical short of signal pin to ground power rail (VSS)Low resistance between power supply rail (VDD) and ground rail (VSS)High IDD currentExcess supply currentParametric shift of signal or power pinsFunctional failure of circuits.

Figure 1.4 Signs of EOS damage – the electrical signature

All of the above are indications that the product either has an open, short, or degradation that leads to either functional failure, increased leakage, or latent mechanisms.

1.7.2 Signs of Electrical Overstress Damage – The Visual Signature

After an electrical overstress (EOS), a second way to determine that there was an EOS event is the visual signature [92]. In the case of visual EOS damage signature, this can be either external visual damage, or internal visual damage. External visual damage is typically associated with the package, whereas internal visual damage is contained within the package. Some of the EOS event visual external damage characteristics are as follows (Figure 1.5):

External package power or signal pin meltingExternal cracking in the packageExternal displacement of the package (e.g., top removed)Melting of the package materialDiscoloration of the mold compoundPhysical hole in the mold compoundVisible bulge or ablation in the mold compound.

Figure 1.5 Signs of EOS damage – the visual signature

Internal EOS visual damage may be the following:

Carbonized mold compoundBond wire meltingBond wire vaporizationBond wire–bond pad separationBond pad cracking and de-laminationMetal interconnect damage – blistering, agglomeration, or displacementMetal discolorationInter-level dielectric (ILD) crackingDielectric breakdown.

1.8 Electrical Overstress and Electrostatic Discharge

A key issue in determining the root cause is distinguishing between an electrical overstress (EOS) event and an electrostatic discharge (ESD) event [73]. As discussed in the prior sections, ESD events are part of the EOS spectrum, as a sub-classification, but historically there is a desire to distinguish between the two, to hone in on the root cause of the failure. To follow suit with this thinking, let us make a distinction between the two classifications. In the following sections, let us draw a distinction between these classifications in more depth.

1.8.1 Comparison of High and Low Current EOS versus ESD Events

Electrical overstress (EOS) and electrostatic discharge (ESD) can be grouped into three general areas based on the event characteristics. Electrical overstress phenomena into three groups: (1) ESD, (2) Low current EOS, and (3) high current and high power EOS. The first two groups affect consumer products, automotive, military, and medical applications, whereas the third group (e.g., lightning) is associated with automobiles, airplanes, buildings, and electronics. This third group is associated with lightning and power.

1.8.2 Electrical Overstress and Electrostatic Discharge Differences

Although there are similarities between electrical overstress (EOS) and electrostatic discharge (ESD), there are a greater number of differences. The differences can be broken into the following categories [73]:

Nature and source of the charge and currentCharacteristic time responseWaveform definitionPeriodicityRepeatabilityFailure mechanisms.

1.8.2.1 Nature and Source of the Charge and Current

Electrostatic discharge (ESD) events are typically associated with tribo-electric charging and accumulation of charge; this process is followed by a rapid discharge of the event through electrical contact or arc discharge. The ESD current is associated with the discharge process of the accumulated charge.

In contrast, EOS events are associated with voltage or currents associated with power sources, power generating equipment, machinery, and tooling.

1.8.2.2 Characteristic Time Response

The electrostatic discharge (ESD) event characteristic time response is associated with a specific process of charge accumulation and discharge. Hence, the characteristic time response is definable enough to establish an ESD standard associated with the specific process. Second, the time response of ESD events are fast processes. The time constant for ESD events range from sub-nanoseconds to hundreds of nanoseconds.

In contrast, EOS events do not have a characteristic time response. They can have short time response or long (note: today, it is popular to separate the “ESD events” as distinct from “EOS events”, which is what will be followed in this text). EOS processes are typically slower and distinguishable from ESD events by having longer characteristic times. The time constant for EOS events range from sub-microseconds to seconds (Figure 1.6).

Figure 1.6 EOS and ESD event time constant spectrum

1.8.2.3 Waveform Definition

For electrostatic discharge (ESD) events, the waveform is well defined for given events. The ESD pulse waveform is codified within the ESD standards. The different ESD events, such as human body model (HBM), machine model (MM), charged device model (CDM), human metal model (HMM), IEC 61000-4-2, and transmission line pulse (TLP) are well defined waveforms [84–90].

In contrast, for EOS events, the waveforms are not well defined [73]; EOS has no specific waveform. Historically, this has made the quantification of EOS events less tractable and definable; this has limited EOS standard development and a requirement for the shipping of components and systems. Today, the standard IEC 61000-4-5 for transients and surges is gaining interest as a standard for the quantification of EOS phenomena.

1.8.2.4 Periodicity

Electrostatic discharge (ESD) events are typically aperiodic [73]. Charge is accumulated, and current transfer occurs as the result of a switch or electrical breakdown. The events are typically a single pulse. The pulse can be single polarity or bi-directional.

EOS events can be periodic, aperiodic, and can be single polarity or bi-directional. EOS events can be oscillatory signals on the power grid or incoming power source.

1.8.2.5 Repeatability

Electrostatic discharge (ESD) events are not repeatable events, whereas EOS events can be repeatable [73]. EOS events associated with motors, actuators, machinery, and power sources can be repeatable events.

1.8.2.6 Failure Mechanisms

Electrostatic discharge (ESD) event failure damage is typically localized and a small area in one device in a semiconductor chip. ESD events can be larger areas when the current magnitude or voltage is significant.

It is commonly viewed that EOS events cause larger failure sites. One misconception is that if it is large, it must be an EOS event (note: this is not always true). EOS event failure damage can be the same as ESD events, but the key distinction is that there exists additional failures not observed from ESD events. EOS event failure damage can include the following:

Bond padsWirebond delaminationWirebond bendingWirebond meltingPackage seal materialsPackage molding materialsPackage paddlePackage delaminationPackage discolorationPackage pin damagePackage meltingSolder joint failurePrinted circuit board (PCB) trace failureDiscrete component (e.g., capacitors, diodes)EOS protection device failures.

1.8.3 Electrical Overstress and Electrostatic Discharge Similarities

Electrical overstress (EOS) and electrostatic discharge (ESD) events are both processes that can cause semiconductor device failure and system failures. These processes have both differences and similarities. In this section, the similarities between EOS and ESD events will be discussed.

EOS and ESD events lead to electrical over-voltage (EOV), electrical over-current (EOC), and electrical over-power (EOP) failures.

A second similarity is both EOS and ESD events can occur in manufacturing and production environments and in the field.

A third similarity is EOS and ESD can lead to failure of semiconductor component failures. In both events, the current and voltage levels are significant enough to lead to dielectric breakdown, second breakdown (It2), and melting of the semiconductor devices. EOS and ESD events can damage the following components:

Active semiconductor devicesPassive semiconductor devicesWire interconnects (e.g., wiring layers, vias, and contacts)Interconnect power busInterconnect ground busInter-level dielectrics (ILD).

Because both EOS and ESD events can cause damage to semiconductor components, at times, it is hard to distinguish whether the event is EOS or ESD; this interferes with the ability to determine the root cause for some events.

1.8.4 Comparison of EOS versus ESD Waveforms

Figure 1.7 contains examples of both electrostatic discharge (ESD) and electrical overstress (EOS) waveforms. In the plot, ESD waveforms for the human body model (HBM), machine model (MM), and IEC 61000-4-2 are shown. In comparison, an EOS waveform is highlighted. The key point is that the ESD event waveforms are significantly shorter than EOS events.

Figure 1.7 EOS and ESD event waveform comparison

1.8.5 Comparison of EOS versus ESD Event Failure Damage

It is a common practice to judge the root cause based on the signature of electrical overstress (EOS) or electrostatic discharge (ESD).

For the electrical signature, both EOS and ESD events produce the following:

Electrical open (open connections)Electrical short of signal pin to power rail (VDD)Electrical short of signal pin to ground power rail (VSS)Low resistance between power supply rail (VDD) and ground rail (VSS)High IDD currentExcess supply currentParametric shift of signal or power pinsFunctional failure of circuits.

From these items, one cannot distinguish if the event was an EOS or ESD. These electrical signatures can occur due to printed circuit board failures, component package failures, interconnect failures, component signal pin ESD network failures, I/O failures, component ESD power clamp failures, or internal chip failures.

From the visual signature, whereas EOS events cause these type of failures, ESD events do not cause the following failures:

External package power or signal pin meltingExternal cracking in the packageExternal displacement of the package (e.g., top removed)Melting of the package materialDiscoloration of the mold compoundPhysical hole in the mold compoundVisible bulge or ablation in the mold compoundCarbonized mold compoundBond wire meltingBond wire vaporizationBond wire–bond pad separationBond pad cracking and de-laminationElectro-migration.

Both EOS and ESD events lead to the following signatures:

Metal interconnect damage – blistering, agglomeration, or displacementMetal discolorationMetal film crystalline structure changeInter-level dielectric (ILD) crackingMOSFET source–drain silicon melt damageDiode emitter–base metallurgical junction damageSilicide film discolorationSilicide film phase change and crystal structure changeSilicide metallurgical junction spikingTungsten metal contact surface spiking.

It is commonly believed that EOS events are larger damage patterns than ESD events. This can lead to misdiagnosis of the root cause of events. Charged board events (CBE) and even charged device model (CDM) failures can be large areas when involving charge transfer from a substrate or a power grid (e.g., VDD).

What is true is some ESD events may be isolated spatially to one or two devices within a I/O circuit. EOS events can be related to multiple currents, and multiple devices. Typically, in an ESD event, it is related to one current path, and a few devices in that given current path.

1.9 Electromagnetic Interference

Electromagnetic interference (EMI) is interference, or noise, generated from an electromagnetic field [94–115]. Electromagnetic interference is electric and magnetic fields that interfere with electrical components, magnetic components, and electrical or magnetic systems. EMI can lead to both component level or system level failure of electronic systems. EMI can lead to failure of electronic components, without physical contact to the electronic system. In the industry, there are a significant number of standards and tests to address both EMC and EMI concerns [94–115].

1.9.1 Electrical Overstress Induced Electromagnetic Interference

Electromagnetic interference (EMI) is interference, or noise, generated from an electromagnetic field. Electromagnetic interference is electric and magnetic fields that interfere with electrical components, magnetic components, and electrical or magnetic systems. EMI can lead to both component-level and system-level failure of electronic systems. EMI can lead to failure of electronic components, without physical contact to the electronic system. In the industry, there are significant number of standards and tests to address both EMC and EMI concerns [94–115].

1.10 Electromagnetic Compatibility

Electromagnetic compatibility (EMC) is the ability of an electronic system to function properly in its intended electromagnetic environment and not be a source of electronic emissions to that electromagnetic environment [94–115]. EMC has two features. The first feature is a source of emission of an electromagnetic field. A second feature is the collector of electromagnetic energy. The first aspect is the emission of an electromagnetic field which may lead to electromagnetic interference of other components or systems. The second aspect has to do with the susceptibility of a component or system to the undesired electromagnetic field. Today, there are many standards and tests on the subject of EMC [99–111].

1.11 Thermal Over-Stress

When electrical over-current occurs, electronic components can have excessive Joule heating, material property changes, melting, or fire. This state can be referred to as thermal over-stress (TOS). Thermal over-stress can be a result of an electrical over-current, or electrical over-power [118]. TOS can occur when a component undergoes thermal breakdown, thermal instability, or thermal run-away. Failure signatures from thermal overstress can be as follows:

External package power or signal pin meltingExternal cracking in the packageExternal displacement of the package (e.g., top removed)Melting of the package materialDiscoloration of the mold compoundVisible bulge or ablation in the mold compoundCarbonized mold compoundBond wire meltingBond wire vaporizationBond wire–bond pad separationBond pad cracking and de-laminationElectro-migrationDielectric breakdown.

1.11.1 Electrical Overstress and Thermal Overstress

Electrical overstress (EOS) can lead to thermal overstress (TOS). For example, electrical overvoltage of semiconductor bipolar junction transistors, MOSFETs, or LDMOS transistors undergoes electrical breakdown, followed by thermal instability, and then thermal runaway. But, not all forms of EOS lead to thermal failure.