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- Herausgeber: John Wiley & Sons
- Kategorie: Wissenschaft und neue Technologien
- Sprache: Englisch
There is currently no single book that covers the mathematics, circuits, and electromagnetics backgrounds needed for the study of electromagnetic compatibility (EMC). This book aims to redress the balance by focusing on EMC and providing the background in all three disciplines. This background is necessary for many EMC practitioners who have been out of study for some time and who are attempting to follow and confidently utilize more advanced EMC texts.
The book is split into three parts: Part 1 is the refresher course in the underlying mathematics; Part 2 is the foundational chapters in electrical circuit theory; Part 3 is the heart of the book: electric and magnetic fields, waves, transmission lines and antennas. Each part of the book provides an independent area of study, yet each is the logical step to the next area, providing a comprehensive course through each topic. Practical EMC applications at the end of each chapter illustrate the applicability of the chapter topics. The Appendix reviews the fundamentals of EMC testing and measurements.
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Seitenzahl: 462
Veröffentlichungsjahr: 2017
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Table of Contents
Cover
Title Page
Preface
Part I: Math Foundations of EMC
1 Matrix and Vector Algebra
1.1 Basic Concepts and Operations
1.2 Matrix Multiplication
1.3 Special Matrices
1.4 Matrices and Determinants
1.5 Inverse of a Matrix
1.6 Matrices and Systems of Equations
1.7 Solution of Systems of Equations
1.8 Cramer’s Rule
1.9 Vector Operations
1.10 EMC Applications
References
2 Coordinate Systems
2.1 Cartesian Coordinate System
2.2 Cylindrical Coordinate System
2.3 Spherical Coordinate System
2.4 Transformations between Coordinate Systems
2.5 EMC Applications
References
3 Vector Differential Calculus
3.1 Derivatives
3.2 Differential Elements
3.3 Constant‐Coordinate Surfaces
3.4 Differential Operators
3.5 EMC Applications
References
4 Vector Integral Calculus
4.1 Line Integrals
4.2 Surface Integrals
4.3 Volume Integrals
4.4 Divergence Theorem of Gauss
4.5 Stokes’s Theorem
4.6 EMC Applications
References
5 Differential Equations
5.1 First Order Differential Equations – RC and RL Circuits
5.2 Second‐Order Differential Equations – Series and Parallel RLC Circuits
5.3 Helmholtz Wave Equations
5.4 EMC Applications
References
6 Complex Numbers and Phasors
6.1 Definitions and Forms
6.2 Complex Conjugate
6.3 Operations on Complex Numbers
6.4 Properties of Complex Numbers
6.5 Complex Exponential Function
6.6 Sinusoids and Phasors
6.7 EMC Applications
References
Part II: Circuits Foundations of EMC
7 Basic Laws and Methods of Circuit Analysis
7.1 Fundamental Concepts
7.2 Laplace Transform Basics
7.3 Fundamental Laws
7.4 EMC Applications
References
8 Systematic Methods of Circuit Analysis
8.1 Node Voltage Analysis
8.2 Mesh Current Analysis
8.3 EMC Applications
References
9 Circuit Theorems and Techniques
9.1 Superposition
9.2 Source Transformation
9.3 Thévenin Equivalent Circuit
9.4 Norton Equivalent Circuit
9.5 Maximum Power Transfer
9.6 Two‐Port Networks
9.7 EMC Applications
References
10 Magnetically Coupled Circuits
10.1 Self and Mutual Inductance
10.2 Energy in a Coupled Circuit
10.3 Linear (Air‐Core) Transformers
10.4 Ideal (Iron‐Core) Transformers
10.5 EMC Applications
References
11 Frequency‐Domain Analysis
11.1 Transfer Function
11.2 Frequency‐Transfer Function
11.3 Bode Plots
11.4 Passive Filters
11.5 Resonance in RLC Circuits
11.6 EMC Applications
References
12 Frequency Content of Digital Signals
12.1 Fourier Series and Frequency Content of Signals
12.2 EMC Applications
References
Part III: Electromagnetics Foundations of EMC
13 Static and Quasi‐Static Electric Fields
13.1 Charge Distributions
13.2 Coulomb’s Law
13.3 Electric Field Intensity
13.4 Electric Field Due to Charge Distributions
13.5 Electric Flux Density
13.6 Gauss’s Law for the Electric Field
13.7 Applications of Gauss’s Law
13.8 Electric Scalar Potential and Voltage
13.9 Voltage Calculations due to Charge Distributions
13.10 Electric Flux Lines and Equipotential Surfaces
13.11 Maxwell’s Equations for Static Electric Field
13.12 Capacitance Calculations of Structures
13.13 Electric Boundary Conditions
13.14 EMC Applications
References
14 Static and Quasi‐Static Magnetic Fields
14.1 Magnetic Flux Density
14.2 Magnetic Field Intensity
14.3 Biot–Savart Law
14.4 Current Distributions
14.5 Ampere’s Law
14.6 Applications of Ampere’s Law
14.7 Magnetic Flux
14.8 Gauss’s Law for Magnetic Field
14.9 Maxwell’s Equations for Static Fields
14.10 Vector Magnetic Potential
14.11 Faraday’s Law
14.12 Inductance Calculations of Structures
14.13 Magnetic Boundary Conditions
14.14 EMC Applications
References
15 Rapidly Varying Electromagnetic Fields
15.1 Eddy Currents
15.2 Charge‐Current Continuity Equation
15.3 Displacement Current
15.4 EMC Applications
References
16 Electromagnetic Waves
16.1 Uniform Waves – Time Domain Analysis
16.3 Reflection and Transmission of Uniform Waves at Boundaries
16.4 EMC Applications
References
17 Transmission Lines
17.1 Transient Analysis
17.2 Steady‐State Analysis
17.3
s
Parameters
17.4 EMC Applications
References
18 Antennas and Radiation
18.1 Bridge between the Transmission Line and Antenna Theory
18.2 Hertzian Dipole Antenna
18.3 Far Field Criteria
18.4 Half‐Wave Dipole Antenna
18.5 Quarter‐Wave Monopole Antenna
18.6 Image Theory
18.7 Differential‐ and Common‐Mode Currents and Radiation
18.8 Common Mode Current Creation
18.9 Antenna Circuit Model
18.10 EMC Applications
References
Appendix A: EMC Tests and Measurements
A.1 Introduction – FCC Part 15 and CISPR 22 Standards
A.2 Conducted Emissions
A.3 Radiated Emissions
A.4 Conducted Immunity – ISO 11452‐4
A.5 Radiated Immunity
A.6 Electrostatic Discharge (ESD)
References
Index
End User License Agreement
List of Tables
Chapter 11
Table 11.1 First‐order filter descriptions.
Table 11.2 Second‐order filter descriptions.
Chapter 17
Table 17.1 Resistive load values.
Table 17.2 Board topologies.
Appendix A
Table A.1 CISPR 25 voltage method – peak and quasi‐peak limits.
Table A.2 CISPR 25 voltage method – average detector limits.
Table A.3 CISPR 25 current probe method – peak and quasi‐peak limits.
Table A.4 CISPR 25 current probe method – average detector limits.
Table A.5 ISO 11542‐4 test severity levels.
Table A.6 ISO 10605 – ESD generator parameters.
Table A.7 ISO 61000–4‐2 – Test levels and ESD generator parameters.
List of Illustrations
Chapter 01
Figure 1.1 PCB used for creating crosstalk between traces.
Figure 1.2 Three‐conductor transmission line: (a) PCB arrangement; (b) circuit model.
Figure 1.3 Crosstalk induced by the aggressor circuit in the victim circuit.
Figure 1.4 Per‐unit length circuit model of three‐conductor transmission line.
Figure 1.5 Radiating loop fixture.
Figure 1.6 Coupled coils in the frequency domain.
Figure 1.7 Two‐port network and the travelling waves.
Figure 1.8 Incident and reflected waves at port 1 and port 2.
Chapter 02
Figure 2.1 Cartesian coordinate system.
Figure 2.2 Vector decomposition.
Figure 2.3 Cross product using cyclic permutations.
Figure 2.4 Cylindrical coordinate system.
Figure 2.5 Cross product using cyclic permutations in cylindrical system.
Figure 2.6 Spherical coordinate system.
Figure 2.7 Cross product using cyclic permutations in spherical system.
Figure 2.8 Relationship between Cartesian and cylindrical variables.
Figure 2.9 Monopole antenna used in EMC compliance testing.
Figure 2.10 Hertzian dipole.
Chapter 03
Figure 3.1 Differential displacement in the Cartesian system.
Figure 3.2 Differential displacement in cylindrical system.
Figure 3.3 Differential displacement in ϕ direction.
Figure 3.4 Differential displacement in spherical system.
Figure 3.5 Differential surface vector.
Figure 3.6 Differential surface vector decomposition.
Figure 3.7 Constant‐coordinate surfaces in a Cartesian system.
Figure 3.8 Constant‐coordinate surfaces in a cylindrical system.
Figure 3.9 Constant‐coordinate surfaces in a spherical system.
Figure 3.10 Equivalent circuit model of a transmission line.
Chapter 04
Figure 4.1 Illustration of the line integral.
Figure 4.2 Illustration of Eq. (4.22).
Figure 4.3 Line integral example.
Figure 4.4 Subdivision of the region
R
in Eq. (4.28c).
Figure 4.5 Closed surface in Example 4.3.
Figure 4.6 Illustration of Stokes’s Theorem.
Figure 4.7 Magnetic flux as a surface integral.
Figure 4.8 Magnetic flux as a line integral.
Figure 4.9 CMOS inverter logic gate.
Figure 4.10 Cascaded CMOS configuration.
Figure 4.11 Cascaded CMOS inverters.
Figure 4.12 Input signal is Low.
Figure 4.13 Current flow stops when C
GN
is charged to V
CC
.
Figure 4.14 Transition from low‐to‐high.
Figure 4.15 Current flow stops when C
GP
is charged to V
CC
.
Figure 4.16 Transition from high to low.
Figure 4.17 Power distribution system and the current flow.
Figure 4.18 Partial inductance: transition from low to high.
Figure 4.19 Partial inductance: transition from high to low.
Chapter 05
Figure 5.1 RC circuit.
Figure 5.2 RC circuit step response.
Figure 5.3 RL circuit.
Figure 5.4 RL circuit step response.
Figure 5.5 Series RLC circuit.
Figure 5.6 Series RLC circuit with zero initial conditions.
Figure 5.7 Forced responses of a series RLC circuit.
Figure 5.8 Underdamped responses for different values of ζ.
Figure 5.9 Parallel RLC circuit.
Figure 5.10 Current density source located at the origin of the coordinate system.
Figure 5.11 Current density source located away from the origin.
Figure 5.12 Transmission line terminated by an inductive load.
Figure 5.13 HyperLynx circuit model of a transmission line terminated by an inductive load.
Figure 5.14 Driver voltage and the voltage across the inductor.
Figure 5.15 Lumped parameter model of a pulse circuit.
Figure 5.16 Experimental setup for ringing measurements.
Figure 5.17 Circuit model of the experimental setup.
Figure 5.18 Trapezoidal pulse train produced by a function generator.
Figure 5.19 Ringing (a): with the rise time at 2.5 ns and fall time at 10 ns, (b) with both the rise and fall time at 2.5 ns.
Figure 5.20 Ringing waveform on the rising edge.
Figure 5.21 H‐field probe current measurements.
Figure 5.22 Voltage and current waveforms for the 10 ns rise time case.
Figure 5.23 Voltage and current waveforms for the 2.5 ns rise time case.
Chapter 06
Figure 6.1 Complex plane.
Figure 6.2 Solution of Example 6.2.
Figure 6.3 Complex number representation as a directed line segment.
Figure 6.4 Complex number and its complex conjugate.
Figure 6.5 Multiplication by
j
.
Figure 6.6 Division by
j
.
Figure 6.7 Trigonometric relations.
Figure 6.8 Hertzian dipole.
Chapter 07
Figure 7.1 Current designation.
Figure 7.2 Voltage designation.
Figure 7.3 Passive sign convention: (a) satisfied, (b) not satisfied.
Figure 7.4 Unit step function.
Figure 7.5 Resistor symbol and circuit variables.
Figure 7.6 Short circuit.
Figure 7.7 Open circuit.
Figure 7.8 Ideal switch: (a) open (b) closed.
Figure 7.9 Inductor symbol and circuit variables.
Figure 7.10 Capacitor symbol and circuit variables.
Figure 7.11 Resistor symbol and circuit variables in the (a) time domain, (b) phasor domain.
Figure 7.12 Inductor symbol and circuit variables in the (a) time domain, (b) phasor domain.
Figure 7.13 Capacitor symbol and circuit variables in the (a) time domain, (b) phasor domain.
Figure 7.14 Resistor symbol and circuit variables in the (a) time domain, (b) phasor domain, (c)
s
domain.
Figure 7.15 Inductor symbol and circuit variables in the (a) time domain, (b) phasor domain, (c)
s
domain.
Figure 7.16 Capacitor symbol and circuit variables in the (a) time domain, (b) phasor domain, (c)
s
domain.
Figure 7.17 Circuit elements and their impedances.
Figure 7.18 Circuit elements and their impedances.
Figure 7.19 Illustration of the Kirchhoff’s current law.
Figure 7.20 Combining current sources in parallel.
Figure 7.21 Illustration of the Kirchhoff’s voltage law.
Figure 7.22 Combining voltage sources in series.
Figure 7.23 Illustration of the circuit equivalence.
Figure 7.24 Illustration of the voltage divider.
Figure 7.25 Circuit for Example 7.5.
Figure 7.26 Circuit for Example 7.6.
Figure 7.27 Resistors in parallel and circuit equivalence.
Figure 7.28 Equivalent resistance of two resistors in parallel.
Figure 7.29 Equivalent resistance of a resistor in parallel with a short.
Figure 7.30 Illustration of the current divider.
Figure 7.31 Current divider rule for two resistors in parallel.
Figure 7.32 Circuit for Example 7.7.
Figure 7.33 Circuit for Example 7.8.
Figure 7.34 Impedances in series.
Figure 7.35 Voltage divider circuit.
Figure 7.36 Impedances in parallel.
Figure 7.37 Current divider circuit.
Figure 7.38 Circuit for Example 7.8.
Figure 7.39 Circuit for Example 7.9.
Figure 7.40 Circuit for Example 7.10.
Figure 7.41 Circuit for Example 7.10.
Figure 7.42 Circuit for Example 7.12.
Figure 7.43
s
‐domain circuit for Example 7.12.
Figure 7.44 Three‐conductor transmission line: (a) PCB arrangement; (b) circuit model.
Figure 7.45 Inductive coupling between the circuits: (a) field model, (b) circuit model.
Figure 7.46 Capacitive coupling between the circuits: (a) field model, (b) circuit model.
Figure 7.47 Transmission line terminated by a capacitive load.
Figure 7.48
s
domain circuit model.
Figure 7.49 HyperLynx circuit model of a transmission line terminated by a capacitive load.
Figure 7.50 Driver voltage and the voltage across the capacitor.
Chapter 08
Figure 8.1 Node voltage analysis circuit.
Figure 8.2 Node voltage assignments.
Figure 8.3 Current assignments.
Figure 8.4 Mesh current analysis circuit.
Figure 8.5 Mesh current assignments.
Figure 8.6 Current assignments.
Figure 8.7 Generic power supply filter topology.
Figure 8.7 Generic power supply filter topology.
Figure 8.8 Equivalent circuit to that shown in Figure 8.7.
Figure 8.9 Equivalent mesh E‐F‐B‐E.
Figure 8.10 Equivalent circuit to that shown in Figure 8.8.
Figure 8.11 Power supply filter with the differential mode current.
Figure 8.12 Equivalent circuit to that shown in Figure 8.11.
Figure 8.13 Equivalent circuit to that shown in Figure 8.12.
Figure 8.14 Equivalent mesh E‐F‐B‐E.
Figure 8.15 Equivalent circuit to that shown in Figure 8.13.
Chapter 09
Figure 9.1 Linear circuit driven by several independent sources.
Figure 9.2 The principle of superposition.
Figure 9.3 Circuit driven by the voltage source
V
S
1
.
Figure 9.4 Circuit driven by the voltage source
V
S
2
.
Figure 9.5 Circuit driven by the current source I
S
.
Figure 9.6 Circuit for Example 9.1.
Figure 9.7 Circuit with the current source deactivated.
Figure 9.8 Circuit with the voltage source deactivated.
Figure 9.9 Source transformations.
Figure 9.10 Equivalent circuits.
Figure 9.11 Equivalence for
R = 0
.
Figure 9.12 Equivalence for
R = ∞
.
Figure 9.13 Equivalence for any
R
.
Figure 9.14 Circuit for Example 9.2.
Figure 9.15 Source transformations – Example 9.2.
Figure 9.16 Source transformations – Example 9.2.
Figure 9.17 Source transformations – Example 9.2.
Figure 9.18 Source transformations – Example 9.2.
Figure 9.19 Linear circuit driving a load.
Figure 9.20 Driving circuit with the load disconnected.
Figure 9.21 Thévenin equivalent circuit.
Figure 9.22 Thévenin equivalent circuit.
Figure 9.23 Thévenin voltage.
Figure 9.24 Circuit for Example 9.3.
Figure 9.25 Open‐circuit voltage.
Figure 9.26 Circuits for calculation of open‐circuit voltage.
Figure 9.27 Circuit for calculation of Thévenin Resistance.
Figure 9.28 Thévenin equivalent for Example 9.3.
Figure 9.29 Thévenin equivalent resistance.
Figure 9.30 Calculation of Thévenin resistance.
Figure 9.31 Calculation of Thévenin resistance.
Figure 9.32 Calculation of Thévenin resistance.
Figure 9.33 Calculation of Thévenin resistance.
Figure 9.34 Driving circuit with and without the load.
Figure 9.35 Norton equivalent circuit.
Figure 9.36 Short‐circuit current.
Figure 9.37 Thévenin and Norton Equivalence.
Figure 9.38 Circuit for Example 9.4.
Figure 9.39 Short‐circuit current.
Figure 9.40 Thévenin equivalent of the driving circuitry.
Figure 9.41 Source‐load interface in the sinusoidal steady state.
Figure 9.42 Two‐port network.
Figure 9.43 Resistive circuit for Example 9.6.
Figure 9.44 Port 2 open‐circuited.
Figure 9.45 Port 1 open‐circuited.
Figure 9.46 Typical two‐port circuit.
Figure 9.47 Response of a linear system to a basis function.
Figure 9.48 Response of a linear system to the signal
x
(
t
).
Figure 9.49 Trapezoidal clock signal.
Figure 9.50 Physical model of an antenna in a transmitting mode.
Figure 9.51 Circuit model of an antenna in a transmitting mode.
Figure 9.52 Detailed circuit model of an antenna in a transmitting mode.
Figure 9.53 Antenna current.
Figure 9.54
s
Parameters are related to the traveling waves.
Figure 9.55 Incident and reflected waves.
Chapter 10
Figure 10.1 Magnetic flux produced by the current flowing in a loop.
Figure 10.2 Loop self‐inductance.
Figure 10.3 Circuit model of a loop.
Figure 10.4 Flux caused by current in loop 1 intersects loop 2.
Figure 10.5 Mutual inductance between loops 1 and 2.
Figure 10.6 Mutual inductance between loops 2 and 1.
Figure 10.7 Mutual inductance between loops 2 and 1.
Figure 10.8 Mutual inductance with dot convention.
Figure 10.9 Dot convention application.
Figure 10.10 Polarities of the induced voltages.
Figure 10.11 Per‐unit length circuit model of three‐conductor transmission line.
Figure 10.12 Coupled coils.
Figure 10.13 A linear transformer.
Figure 10.14 Circuit symbol of an ideal transformer.
Figure 10.15 Coupled coils in frequency domain.
Figure 10.16 Voltages and currents in an ideal transformer.
Figure 10.17 Circuit with a matching transformer.
Figure 10.18 Common‐mode choke.
Figure 10.19 Total currents flowing in each wire.
Figure 10.20 Circuit model of the CM choke.
Chapter 11
Figure 11.1 Circuit used to define the voltage transfer function.
Figure 11.2 Circuit used to define input impedance.
Figure 11.3 Circuit used to define output impedance.
Figure 11.4 Circuit for Example 11.1.
Figure 11.5 Circuit in the
s
domain.
Figure 11.6 Simplified circuit.
Figure 11.7 Circuit for obtaining the input impedance.
Figure 11.8 Equivalent circuit for obtaining the input impedance.
Figure 11.9 Circuit for obtaining the output impedance.
Figure 11.10 Equivalent circuit for obtaining the output impedance.
Figure 11.11 LTI system driven by a sinusoid (a) time domain representation, (b) frequency domain representation.
Figure 11.12 Circuit for Example 11.4.
Figure 11.13 Magnitude plot for the factor in Eq. (11.37).
Figure 11.14 Magnitude plot for the factor in Eq. (11.38).
Figure 11.15 Magnitude plot for the transfer function in Eq. (11.43).
Figure 11.16 Magnitude plot for the factor in Eq. (11.44).
Figure 11.17 Magnitude plot for the transfer function in Eq. (11.49).
Figure 11.18 Frequency response of the four types of ideal filters.
Figure 11.19
RL
low‐pass filter.
Figure 11.20 RL low‐pass filter.
Figure 11.21
RL
low‐pass filter frequency response.
Figure 11.22 RC low‐pass filter.
Figure 11.23
RC
low‐pass filter frequency response.
Figure 11.24 Bode magnitude plot of the
RL
and
RC
low‐pass filter.
Figure 11.25
RL
high‐pass filter.
Figure 11.26
RL
high‐pass filter frequency response.
Figure 11.27
RC
high‐pass filter.
Figure 11.28
RC
high‐pass filter frequency response.
Figure 11.29 Bode magnitude plot of
RL
and
RC
high‐pass filters.
Figure 11.30 Series RLC bandpass filter.
Figure 11.31 Series RLC bandpass filter frequency response.
Figure 11.32 Series RLC bandpass filter – Bode magnitude plot.
Figure 11.33 Parallel RLC bandpass filter.
Figure 11.34 Series RLC band reject filter.
Figure 11.35 Series RLC band reject filter frequency response.
Figure 11.36 Series RLC band reject filter – Bode magnitude plot.
Figure 11.37 Parallel RLC band reject filter.
Figure 11.38 Series RLC bandpass filter.
Figure 11.39 Magnitude of the input impedance.
Figure 11.40 Magnitude of the input admittance.
Figure 11.41 Magnitude of the current.
Figure 11.42 Voltages across the circuit elements.
Figure 11.43 Magnitudes of the voltages across the circuit elements.
Figure 11.44 Voltages across the capacitor and inductor.
Figure 11.45 Circuit with a new capacitor value.
Figure 11.46 Voltages across the resistor Q = 100.
Figure 11.47 Voltages across the capacitor and inductor Q = 100.
Figure 11.48 Parallel RLC bandpass filter.
Figure 11.49 Parallel RLC circuit.
Figure 11.50 Magnitudes of the currents through the circuit elements.
Figure 11.51 Currents through the capacitor and inductor.
Figure 11.52 Magnitude of the capacitor and inductor currents, Q = 100.
Figure 11.53 Pure (a) series and (b) parallel LC configurations.
Figure 11.54 Another parallel LC configuration.
Figure 11.55 Another series LC configuration.
Figure 11.56 Impedance magnitude of the ideal capacitor.
Figure 11.57 Circuit model of a physical capacitor.
Figure 11.58 Impedance magnitude of a physical capacitor.
Figure 11.59 The effect of the connection leads on the impedance of a capacitor.
Figure 11.60 Impedance magnitude of the ideal inductor.
Figure 11.61 The effect of the connection leads on the impedance of an inductor.
Figure 11.62 Local decoupling capacitor in a CMOS circuitry (a) low‐to‐high transition, (b) high‐to‐low transition.
Figure 11.63 Parasitic circuit inductance.
Figure 11.64 Circuit model – three different capacitors in series with 15 nH of parasitic inductance.
Figure 11.65 Impedance plot – three different capacitors in series with 15 nH of parasitic inductance.
Figure 11.66 Circuit model – multiple capacitors of the same value.
Figure 11.67 Impedance plot – multiple capacitors of the same value.
Figure 11.68 Circuit model – single cap vs multiple capacitors when the total capacitance is the same.
Figure 11.69 Impedance plot – multiple capacitors of the same value.
Figure 11.70 Circuit model – two capacitors one decade apart.
Figure 11.71 Impedance plot – two capacitors one decade apart.
Figure 11.72 Circuit model – three capacitors one decade apart.
Figure 11.73 Impedance plot – three capacitors one decade apart.
Figure 11.74 Circuit model – three capacitors one decade apart vs the same value.
Figure 11.75 Impedance plot – three capacitors one decade apart vs. the same value.
Figure 11.76 Illustration of the insertion loss of a filter.
Figure 11.77 First‐order low‐pass filters.
Figure 11.78 LC low‐pass filters: (a) configuration 1, (b) configuration 2.
Figure 11.79 Cascaded LC filters – configuration 1.
Figure 11.80 Cascaded LC filters – configuration 2.
Figure 11.81 π and T low‐pass filters.
Figure 11.82 Filter configurations when both the source and the load impedances are low.
Figure 11.83 Filter configurations when both the source and the load impedances are high.
Figure 11.84 Filter configurations when the source impedance is low and the load impedance is high.
Figure 11.85 Filter configurations when the source impedance is high and the load impedance is low.
Figure 11.86 Filter configurations when the source impedance is low and the load impedance is high: (a) no filter, (b) inductor on the low impedance side (configuration 1), (c) inductor on the high impedance side (configuration 2).
Figure 11.87 Insertion loss of the two configurations shown in Figure 11.86.
Figure 11.88 Filter configurations when the source impedance is high and the load impedance is low: (a) no filter, (b) inductor on the low impedance side (Configuration 1), (c) inductor on the high impedance side (Configuration 2).
Figure 11.89 Insertion loss of the two configurations shown in Figure 11.86.
Figure 11.90 Filter configurations when both the source impedance and the load impedance are low: (a) no filter, (b) inductors on the low impedance sides (π configuration), (c) capacitors on the low impedance sides (T configuration).
Figure 11.91 Insertion loss of the two configurations shown in Figure 11.90.
Figure 11.92 Filter configurations when both the source impedance and the load impedance are 100 Ω: (a) no filter, (b) T filter configuration, (c) π filter configuration.
Figure 11.93 Insertion loss of the two configurations shown in Figure 11.90.
Figure 11.94 Filter configurations when both the source impedance and the load impedance are high: (a) no filter, (b) T filter configuration, (c) π filter configuration.
Figure 11.95 Insertion loss of the two configurations shown in Figure 11.92.
Chapter 12
Figure 12.1 Periodic waveform for Example 12.1.
Figure 12.2 Periodic waveform for Example 12.2.
Figure 12.3 Waveform for Example 12.3,
n
= 1.
Figure 12.4 Waveform for Example 12.3,
n
= 3.
Figure 12.5 Waveform for Example 12.3,
n
= 7.
Figure 12.6 Waveform for Example 12.3,
n
= 19.
Figure 12.7 Waveform for Example 12.3,
n
= 101.
Figure 12.8 Trapezoidal clock signal.
Figure 12.9 Trapezoidal clock signal and its derivative waveforms.
Figure 12.10 Frequency spectrum of a clock signal with 49% and 50 % duty cycle.
Figure 12.11 Bounds on the one‐sided magnitude spectrum of a trapezoidal clock signal.
Figure 12.12 Frequency spectrum of a clock signal with 20 ns vs 5 ns risetime.
Figure 12.13 Effect of the signal amplitude.
Figure 12.14 Effect of the amplitude reduction.
Figure 12.15 Effect of the fundamental frequency while maintaining the duty cycle.
Figure 12.16 Effect of the fundamental frequency while maintaining the duty cycle.
Figure 12.17 Effect of the duty cycle while maintaining the fundamental frequency.
Figure 12.18 Effect of the duty cycle while maintaining the fundamental frequency.
Chapter 13
Figure 13.1 Charge distributions: (a) line, (b) surface, (c) volume.
Figure 13.2 Forces between two point charges.
Figure 13.3 Electric field around a point charge.
Figure 13.4 Determination of an electric field of a single point.
Figure 13.5 Determination of an electric field of a sphere of charge.
Figure 13.6 Determination of an electric field of plane of charge.
Figure 13.7 Determination of an electric field of an infinite line of charge.
Figure 13.8 Determination of an electric field of a cylinder of charge.
Figure 13.9 Determination of the electric field of coaxial transmission line.
Figure 13.10 Determination of the work required to move a charge.
Figure 13.11 Two points away from a line of charge.
Figure 13.12 Two points away from a plane of charge.
Figure 13.13 Voltage between two concentric cylinders.
Figure 13.14 Voltage between two concentric spheres.
Figure 13.15 Equipotential surfaces around a point charge.
Figure 13.16 Capacitive structure.
Figure 13.17 Parallel‐plate capacitor.
Figure 13.18 Parallel‐plate capacitor.
Figure 13.19 Two‐wire transmission line.
Figure 13.20 Coaxial capacitor.
Figure 13.21 Spherical capacitor.
Figure 13.22 Discontinuity at the boundary between two media.
Figure 13.23 Decomposition into the normal and tangential components.
Figure 13.24 Evaluating boundary conditions.
Figure 13.25 Evaluating boundary conditions.
Figure 13.26 Dielectric–conductor boundary.
Figure 13.27 Two initially neutral insulating materials separated from each other.
Figure 13.28 Two initially neutral insulating materials in contact with each other.
Figure 13.29 Insulators are separated after the contact.
Figure 13.30 Net charge on each insulator after the contact.
Figure 13.31 Creation of a capacitor.
Figure 13.32 Triboelectric list.
Figure 13.33 Charged object approaches a conductor.
Figure 13.34 Charged object in the vicinity of a neutral conductor.
Figure 13.35 Momentary contact with another conductor.
Figure 13.36 Charged conductor.
Figure 13.37 ESD event.
Figure 13.38 Initially uncharged dielectrics come into contact.
Figure 13.39 When separated the dielectrics become charged.
Figure 13.40 Positive charge is induced on the sole of the foot.
Figure 13.41 Negative charge moves to the upper parts of the body.
Figure 13.42 Charge separation in an adjacent conductor.
Figure 13.43 ESD event.
Figure 13.44 Typical shape of the ESD event.
Figure 13.45 Human body capacitance.
Figure 13.46 Human body circuit model.
Figure 13.47 An ESD gun and a cartridge.
Figure 13.48 Model of a capacitive coupling between the circuits.
Figure 13.49 Model of a capacitive coupling between the circuits.
Figure 13.50 Simplified circuit model.
Figure 13.51 Circuit representation.
Figure 13.52 Equivalent circuit.
Figure 13.53 Capacitively coupled noise voltage,
.
Figure 13.54 Capacitive coupling modeled as a current source.
Figure 13.55 Reducing capacitive coupling by moving conductors further apart.
Figure 13.56 Reducing capacitive coupling by shielding the receptor circuit.
Figure 13.57 Capacitive coupling without a shield around the receptor circuit.
Figure 13.58 Capacitive coupling with a shield around the receptor circuit.
Figure 13.59 Circuit model without a shield.
Figure 13.60 Circuit model with a shield.
Chapter 14
Figure 14.1 Magnetic field due to a current element.
Figure 14.2 Various current distributions.
Figure 14.3 Illustration of the Ampere’s law.
Figure 14.4 Magnetic field due to an infinite line of current.
Figure 14.5 Coaxial line carrying a current
I
.
Figure 14.6 Magnetic field lines.
Figure 14.7 Open surface defined by a contour
c
.
Figure 14.8 Induced voltage inserted in the loop.
Figure 14.9 Original magnetic field.
Figure 14.10
B
field pointing up and increasing.
Figure 14.11
B
field pointing up and decreasing.
Figure 14.12
B
field pointing down and increasing.
Figure 14.13
B
field pointing down and decreasing.
Figure 14.14 Induced current direction.
Figure 14.15 Induced voltage polarity.
Figure 14.16 Coaxial cable.
Figure 14.17 Two parallel wires.
Figure 14.18 Discontinuity at the boundary between two media.
Figure 14.19 Decomposition into the normal and tangential components.
Figure 14.20 Evaluating boundary conditions.
Figure 14.21 Evaluating boundary conditions.
Figure 14.22 Dielectric‐conductor boundary.
Figure 14.23 Current probes used in EMC.
Figure 14.24 Direct current measurement.
Figure 14.25 Current measurement using a preamplifier.
Figure 14.26 Current probe is a transformer.
Figure 14.27 Current probe terminated in 50 Ω.
Figure 14.28 Current probe calibration chart.
Figure 14.29 CMOS transition from low‐to‐high.
Figure 14.30 CMOS transition from high‐to‐low.
Figure 14.31 Large current loop on CMOS transitions.
Figure 14.32 Bulk decoupling capacitor effect on the current flow on CMOS transitions.
Figure 14.33 Bulk decoupling capacitor effect on the current loop on CMOS transitions.
Figure 14.34 Local decoupling capacitor effect on the current flow on CMOS transitions.
Figure 14.35 Local decoupling capacitor effect on the current loop on CMOS transitions.
Figure 14.36 Magnetic flux crossing the receptor circuit.
Figure 14.37 Induced voltage in the receptor circuit.
Figure 14.38 Frequency domain circuit model.
Figure 14.39 Reducing inductive coupling by reducing the area of the receptor circuit.
Figure 14.40 Inductive coupling with a shield around the receptor circuit.
Figure 14.41 Equivalent circuit model for inductive coupling.
Figure 14.42 Effect of the shield.
Chapter 15
Figure 15.1 Eddy currents on the surface of a conducting body.
Figure 15.2 Illustration of the Ampere’s law – Maxwell’s equation.
Figure 15.3 “Ground” conductor return current.
Figure 15.4 PCB illustrating the alternative current return paths.
Figure 15.5 Forward current flow.
Figure 15.6 Return current alternative paths.
Figure 15.7 Low‐frequency return current path.
Figure 15.8 Low‐frequency current will take the lowest resistance path.
Figure 15.9 High‐frequency return current path.
Figure 15.10 High‐frequency current will take the lowest inductance path.
Figure 15.11 Experimental setup for the return current measurements.
Figure 15.12 Circuit used for the return current measurements.
Figure 15.13 Circuit diagram of the measurement setup.
Figure 15.14 Coax cable measurement results.
Figure 15.15 Two‐sided PCB simulation results.
Figure 15.16 Current returns to the source through a zero‐impedance ground path.
Figure 15.17 Current returns to the source through non‐zero impedance ground.
Figure 15.18 Two circuits share a zero‐impedance ground path.
Figure 15.19 Common‐impedance coupling circuit
Chapter 16
Figure 16.1 Uniform plane wave.
Figure 16.2 A traveling wave.
Figure 16.3 Reflection and transmission of a uniform wave at the boundary.
Figure 16.4 Shielding to decrease the radiated emissions.
Figure 16.5 Shielding to increase the radiated immunity.
Figure 16.6 Electromagnetic wave shielding.
Figure 16.7 SMPS with no shield.
Figure 16.8 SMPS with a shield.
Figure 16.9 1 – no shield; 2 – phosphorus‐bronze 8 mils; 3 – phosphorus‐bronze 15 mils.
Figure 16.10 1 – nickel‐silver 8 mils; 2 – phosphorus‐bronze 8 mils.
Figure 16.11 1 – phosphorus‐bronze 15 mils; 2 – cold‐rolled‐steel 15 mils.
Figure 16.12 1 – no shield; 2 – copper tape 3 mils.
Figure 16.13 1 – cold‐rolled‐steel w/holes 15 mils; 2 – cold‐rolled‐steel solid 15 mils.
Chapter 17
Figure 17.1 Circuit model of a transmission line.
Figure 17.2 Circuit model of a lossless transmission line.
Figure 17.3 Single segment of a lossless transmission line.
Figure 17.4 Transmission line driven by a constant source and terminated by a resistive load.
Figure 17.5 Voltage and current forward waves originate at the source.
Figure 17.6 Equivalent circuit at
t
= 0.
Figure 17.7 Voltage wave travels towards the load.
Figure 17.8 Voltage and current waves arrive at the load.
Figure 17.9 Reflected wave travels towards the source.
Figure 17.10 Reflected voltage and current waves arrive at the source.
Figure 17.11 Re‐reflected wave travels towards the load.
Figure 17.12 Circuit for the load reflection measurements.
Figure 17.13 Experimental setup for the load reflection measurements.
Figure 17.14 Experimental setup – load resistance.
Figure 17.15 Source and load voltages for
R
L
= ∞
.
Figure 17.16 Measurement result for
R
L
=
22 Ω.
Figure 17.17 Measurement result for
R
L
=
47 Ω.
Figure 17.18 Measurement result for
R
L
=
216 Ω.
Figure 17.19 Circuit used to create bounce diagram.
Figure 17.20 Initial voltage wave at
z =
0.
Figure 17.21 Voltage at the load at
t = T
.
Figure 17.22 Voltage at the source at
t =
2
T
.
Figure 17.23 Bounce diagram: voltages at the source and the load.
Figure 17.24 Voltage at the source during
.
Figure 17.25 Voltage at the load during
.
Figure 17.26 Equivalent circuit in steady state.
Figure 17.27 Inductive termination of a transmission line.
Figure 17.28 Creation of a reflected wave at an inductive load.
Figure 17.29 HyperLynx circuit model of a transmission line terminated by an inductive load.
Figure 17.30 Driver voltage and the voltage across the inductor.
Figure 17.31 Transmission line terminated by a capacitive load.
Figure 17.32 HyperLynx circuit model of a transmission line terminated by a capacitive load.
Figure 17.33 Driver voltage and the voltage across the capacitor.
Figure 17.34 Discontinuity along a transmission line.
Figure 17.35 Incoming wave sees a termination impedance Z
C
2
.
Figure 17.36 Wave incident from the right.
Figure 17.37 Incoming wave sees a termination impedance
Z
C
1
.
Figure 17.38 Circuit for the reflection measurements.
Figure 17.39 Experimental setup for the reflection measurements.
Figure 17.40 Voltages at the source and at the discontinuity at
t = T
and
t =
2
T
.
Figure 17.41 Voltage at the load at
t
= 2
T
.
Figure 17.42 Voltage at the load at
t
= 4
T
.
Figure 17.43 Voltage at the discontinuity at
t
= 3
T
and the source at
t
= 4
T
.
Figure 17.44 The per‐unit‐length model of a lossy transmission line.
Figure 17.45 Transmission line circuit.
Figure 17.46 Transmission line circuit, distance measured from the load to the source.
Figure 17.47 Magnitudes of the voltage and current for a short‐circuited load.
Figure 17.48 Magnitudes of the voltage and current for an open‐circuited load.
Figure 17.49 Magnitudes of the voltage and current for a matched load.
Figure 17.50 Magnitudes of the voltage and current for an arbitrary resistive load.
Figure 17.51
s
parameters are related to the traveling waves.
Figure 17.52 Incident and reflected waves.
Figure 17.53 Typical two port circuit.
Figure 17.54 Port 2 termination.
Figure 17.55 Port 1 termination.
Figure 17.56 PCB used for crosstalk measurements.
Figure 17.57 Cross‐section of a PCB with a microstrip line.
Figure 17.58 Circuit model of a PCB with a microstrip line.
Figure 17.59 Inductive coupling between the circuits (a) field model, (b) circuit model.
Figure 17.60 Capacitive coupling between the circuits (a) field model, (b) circuit model.
Figure 17.61 Inductive and capacitive coupling circuit model.
Figure 17.62 Electrically short generator circuit model.
Figure 17.63 Inductive and capacitive coupling circuit model in the frequency domain.
Figure 17.64 Experimental set‐up for crosstalk verification.
Figure 17.65 Crosstalk induced voltages, Case 1.
Figure 17.66 FE Crosstalk – Measured and simulated frequency‐domain results – Case 1.
Figure 17.67 Crosstalk induced voltages, Case 2.
Figure 17.68 FE Crosstalk – Measured and simulated frequency‐domain results – Case 2.
Figure 17.69 Crosstalk induced voltages, Case 3.
Figure 17.70 FE Crosstalk – Measured and simulated frequency‐domain results – Case 3.
Figure 17.71 CISPR 25 LISN.
Figure 17.72 CISPR 25 LISN measurement setup.
Figure 17.73 Shorting bar for impedance measurement.
Figure 17.74 Calibration kit.
Figure 17.75 Calibration measurements.
Figure 17.76 Test setup for the impedance measurement.
Figure 17.77 Circuit used to define
s
11
.
Figure 17.78 Network analyzer measurement of
s
11
.
Figure 17.79
s
11
measurement – LISN impedance.
Figure 17.80 Test setup for the preamp gain measurement.
Figure 17.81 Preamp gain measurement.
Figure 17.82 Test setup for the attenuator loss measurement.
Figure 17.83
s
11
,
s
22
, and
s
21
(through) calibration.
Figure 17.84 Attenuator loss measurement.
Chapter 18
Figure 18.1 Standing wave pattern in a transmission line terminated with an open.
Figure 18.2 Transmission line with terminal section flared.
Figure 18.3 Transmission line with terminal section flared.
Figure 18.4 Maximum radiation broadside to the antenna.
Figure 18.5 Hertzian dipole.
Figure 18.6 Radiating point source.
Figure 18.7 Radiating point source geometry.
Figure 18.8 Half‐wave dipole.
Figure 18.9 Half‐wave dipole connected to a transmission line.
Figure 18.10 Half‐wave dipole subdivision into infinitesimal dipoles.
Figure 18.11 Radiation pattern of a half‐wave dipole.
Figure 18.12 Quarter‐wave dipole.
Figure 18.13 A practical monopole antenna.
Figure 18.14 Hertzian dipole and its image.
Figure 18.15 Direct waves from the Hertzian dipole and its image.
Figure 18.16 Parallel‐ray approximation.
Figure 18.17 A typical circuit model.
Figure 18.18 A realistic circuit model.
Figure 18.19 Circuit model showing the total currents.
Figure 18.20 Differential‐mode radiation.
Figure 18.21 Common‐mode radiation.
Figure 18.22 Far fields of the two‐wire antennas.
Figure 18.23 Load driven by a source.
Figure 18.24 Finite impedance in the connections and ground path.
Figure 18.25 Common ground‐plane impedance coupling.
Figure 18.26 Common power‐plane impedance coupling.
Figure 18.27 Another example of common impedance coupling.
Figure 18.28 A variation of the previous circuit.
Figure 18.29 No current flows through the ground connections.
Figure 18.30 Capacitive coupling to other conducting paths or metallic objects.
Figure 18.31 Differential signaling circuit.
Figure 18.32 A variation of the previous circuit.
Figure 18.33 Equivalent differential signaling circuit.
Figure 18.34 Coupling to the ground plane.
Figure 18.35 Stray current flow.
Figure 18.36 Common‐mode current flow.
Figure 18.37 Physical model of an antenna in a transmitting mode.
Figure 18.38 Circuit model of an antenna in a transmitting mode.
Figure 18.39 Detailed circuit model of an antenna in transmitting mode.
Figure 18.40 Circuit model of a half‐wave dipole.
Figure 18.41 Circuit model of a quarter‐wave monopole.
Figure 18.42 Physical model of an antenna in a transmitting mode.
Figure 18.43 Circuit model of an antenna in a receiving mode.
Figure 18.44 Half‐wave dipole in a receiving mode.
Figure 18.45 Log‐periodic antenna for 300–1000 MHz frequency range measurements.
Figure 18.46 Log‐periodic antenna connected to a measuring receiver.
Figure 18.47 Simplified radiated emissions setup.
Figure 18.48 Antenna factor for a log‐periodic antenna.
Figure 18.49 Antenna in the receiving mode.
Figure 18.50 Antenna SVWR measurement setup.
Figure 18.51 Log‐periodic antenna measurement setup inside the chamber.
Figure 18.52 Measurement setup outside the chamber.
Figure 18.53 Log‐periodic antenna VSWR measurement results.
Figure 18.54 Log‐periodic antenna impedance measurement results.
Figure 18.55 Comb generator measurement setup.
Figure 18.56 Comb generator measurement results.
Appendix A
Figure A.1 An EMI receiver and its typical screen output.
Figure A.2 Relationship between the detectors.
Figure A.3 Peak detector measurement.
Figure A.4 Average detector measurement.
Figure A.5 Quasi‐peak detector measurement.
Figure A.6 FCC and CISPR 22 Class
A
conducted emissions limits.
Figure A.7 FCC and CISPR 22 Class
B
conducted emissions limits.
Figure A.8 CISPR 22 Class
B
radiated emissions limits.
Figure A.9 FCC Class
A
radiated emissions limits.
Figure A.10 FCC Class
B
radiated emissions limits.
Figure A.11 Comparison of the CISPR 22 and FCC Class
A
radiated emissions limits.
Figure A.12 FCC/CISPR22 ac LISN.
Figure A.13 ac LISN schematic.
Figure A.14 CISPR 25 dc LISN.
Figure A.15 MIL‐STD‐461 dc LISN.
Figure A.16 FCC/CISPR 22 conducted emissions test setup.
Figure A.17 Screen room for CISPR 25 conducted emissions measurements.
Figure A.18 The details of the FCC/CISPR 22 voltage method setup.
Figure A.19 DUT arrangement in a screen room for conducted emissions testing.
Figure A.20 An example of the line conducted emissions.
Figure A.21 An example of the neutral conducted emissions.
Figure A.22 The details of the CISPR 25 voltage method setup.
Figure A.23 More details of the CISPR 25 voltage method setup.
Figure A.24 CISPR 25 conducted emissions voltage method – peak detector results on a battery line for a Class 3 device.
Figure A.25 CISPR 25 conducted emissions voltage method – peak detector results on a ground line for a Class 3 device.
Figure A.26 The details of the CISPR 25 current probe method setup.
Figure A.27 More details of the CISPR 25 current probe method setup.
Figure A.28 CISPR 25 conducted emissions current probe method – peak detector results for a Class 5 device.
Figure A.29 CISPR 25 conducted emissions current probe method – average detector results for a Class 5 device.
Figure A.30 An open area test site (OATS).
Figure A.31 A semi‐anechoic chamber for radiated emissions.
Figure A.32 OATS ground plane boundary.
Figure A.33 OATS ambient measurement.
Figure A.34 OATS DUT emissions measurement.
Figure A.35 Monopole antenna for 0.15‐30 MHz frequency range measurements.
Figure A.36 The details of the CISPR 25 setup with a monopole antenna.
Figure A.37 More details of the CISPR 25 monopole antenna setup.
Figure A.38 CISPR 25 radiated emissions, monopole antenna – peak detector results for a Class 5 device.
Figure A.39 Biconnical antenna for 30–300 MHz frequency range measurements.
Figure A.40 The details of the CISPR 25 setup with a biconical antenna.
Figure A.41 More details of the CISPR 25 biconical antenna setup.
Figure A.42 CISPR 25 radiated emissions, biconical antenna – peak detector results for a Class 5 device.
Figure A.43 Log‐periodic antenna for 300–1000 MHz frequency range measurements.
Figure A.44 The details of the CISPR 25 setup with a log‐periodic antenna.
Figure A.45 More details of the CISPR 25 log‐periodic antenna setup.
Figure A.46 CISPR 25 radiated emissions, log‐periodic antenna – peak detector results for a Class 5 device.
Figure A.47 ISO 11452‐4 BCI test setup.
Figure A.48 BCI external equipment.
Figure A.49 BCI screen room with the external equipment.
Figure A.50 BCI setup inside the screen room.
Figure A.51 The details of the ISO 11542–4 setup using the substitution method.
Figure A.52 More details of the of the ISO 11542‐4 setup using the substitution method.
Figure A.53 ISO11452‐4 BCI test result (fail) using the substitution method.
Figure A.54 ISO11452‐4 BCI test result (pass) using the substitution method.
Figure A.55 The details of the ISO 11542‐4 setup using the closed‐loop method with power limitation.
Figure A.56 More details of the of the ISO 11542‐4 setup using the closed‐loop method with power limitation.
Figure A.57 Reverberation and semi‐anechoic chambers for radiated immunity.
Figure A.58 Reverberation chamber is a highly reflective enclosure.
Figure A.59 External equipment required for the reverberation chamber testing.
Figure A.60 The details of the ISO 11542‐11 setup for radiated immunity testing.
Figure A.61 Mechanical tuner/stirrer.
Figure A.62 ISO 11452‐2 external equipment.
Figure A.63 ISO 11452‐2 setup for radiated immunity testing using biconical antenna.
Figure A.64 ISO 11452‐2 setup for radiated immunity testing using log‐periodic antenna.
Figure A.65 ISO 11452‐2 radiated immunity test result (fail).
Figure A.66 ISO 11452‐2 radiated immunity test result (pass).
Figure A.67 ESD gun and RC cartridge.
Figure A.68 Typical RC cartridge combinations.
Figure A.69 Human body circuit model.
Figure A.70 ESD table‐top test setup.
Figure A.71 ISO 10605 powered DUT, direct ESD test setup.
Figure A.72 ISO 10605 powered DUT, indirect ESD test setup.
Figure A.73 ISO 10605 packaging and handling, ESD test setup.
Figure A.74 ISO 61000‐4‐2 ESD test setup for table‐top equipment.
Guide
Cover
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Foundations of Electromagnetic Compatibility
with Practical Applications
Bogdan Adamczyk
EMC Educational Services LLCwww.emcspectrum.com
This edition first published 2017© 2017 John Wiley and Sons Ltd
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by law.Advice on how to obtain permission to reuse material from this title is available at http://www.wiley.com/go/permissions.
The right of Bogdan Adamczyk to be identified as the author of this work has been asserted in accordance with law.
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Library of Congress Cataloging‐in‐Publication Data
Names: Adamczyk, Bogdan, 1960– author.Title: Foundations of electromagnetic compatibility with practical applications / Bogdan Adamczyk.Description: Hoboken, New Jersey : John Wiley & Sons, Inc., 2017. | Includes index.Identifiers: LCCN 2016047894 | ISBN 9781119120780 (hardback ; cloth) | ISBN 1119120780 (hardback ; cloth) | ISBN 9781119120797 (Adobe PDF) | ISBN 1119120799 (Adobe PDF) | ISBN 9781119120803 (ePub) | ISBN 1119120802 (ePub)Subjects: LCSH: Electromagnetic compatibility.Classification: LCC TK7867.2 .A33 2017 | DDC 621.382/24–dc23LC record available at https://lccn.loc.gov/2016047894
Cover design by WileyFront Cover: The cover shows the EMC Center at GVSU created by Prof. Adamczyk
