Heterojunction Bipolar Transistors for Circuit Design E-Book

Jianjun Gao

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 277

Veröffentlichungsjahr: 2015

Beschreibung

A highly comprehensive summary on circuit related modeling techniques and parameter extraction methods for heterojunction bipolar transistors

• Heterojunction Bipolar Transistor (HBT) is one of the most important devices for microwave applications. The book details the accurate device modeling for HBTs and high level IC design using HBTs
• Provides a valuable reference to basic modeling issues and specific semiconductor device models encountered in circuit simulators, with a thorough reference list at the end of each chapter for onward learning
• Offers an overview on modeling techniques and parameter extraction methods for heterojunction bipolar transistors focusing on circuit simulation and design
• Presents electrical/RF engineering-related theory and tools and include equivalent circuits and their matrix descriptions, noise, small and large signal analysis methods

Leseprobe

CONTENTS

Cover

Title page

About the Author

Preface

Acknowledgments

Nomenclature

1 Introduction

1.1 Overview of Heterojunction Bipolar Transistors

1.2 Modeling and Measurement for HBT

1.3 Organization of This Book

References

2 Basic Concept of Microwave Device Modeling

2.1 Signal Parameters

2.2 Representation of Noisy Two-Port Network

2.3 Basic Circuit Elements

2.4

π

- and

T

-Type Networks

2.5 Deembedding Method

2.6 Basic Methods of Parameter Extraction

2.7 Summary

References

3 Modeling and Parameter Extraction Methods of Bipolar Junction Transistor

3.1 PN Junction

3.2 PN Junction Diode

3.3 BJT Physical Operation

3.4 Equivalent Circuit Model

3.5 Microwave Performance

3.6 Summary

References

4 Basic Principle of HBT

4.1 Semiconductor Heterojunction

4.2 HBT Device

4.3 Summary

References

5 Small-Signal Modeling and Parameter Extraction of HBT

5.1 Small-Signal Circuit Model

5.2 HBT Device Structure

5.3 Extraction Method of PAD Capacitances

5.4 Extraction Method of Extrinsic Inductances

5.5 Extraction Method of Extrinsic Resistance

5.6 Extraction Method of Intrinsic Resistance

5.7 Semianalysis Method

5.8 Summary

References

6 Large-Signal Equivalent Circuit Modeling of HBT

6.1 Linear and Nonlinear

6.2 Large Signal and Small Signal

6.3 Thermal Resistance

6.4 Nonlinear HBT Modeling

6.5 Summary

References

7 Microwave Noise Modeling and Parameter Extraction Technique for HBTs

7.1 Noise Equivalent Circuit Model

7.2 Derivation of Noise Parameters

7.3 Noise Parameter Extraction Methods

7.4 Common Base, Emitter, and Collector Configurations

7.5 Summary

References

8 SiGe HBT Modeling and Parameter Extraction

8.1 Introduction

8.2 Small-Signal Model

8.3 Large-Signal Model

8.4 Summary

References

Index

End User License Agreement

List of Tables

Chapter 01

Table 1.1 Comparison of FET and bipolar transistor

Table 1.2 Epitaxial structure of InP/InGaAs/InP DHBT

Table 1.3 A comparison chart for different device technologies in wireless communication RF transceiver applications

Chapter 02

Table 2.1 Conversion between different network representations

Table 2.2 Conversion between

S

-parameters and

Z

-,

Y

-,

H

-, and

ABCD

-parameters

Table 2.3 Conversion between different network noise representations

C

Y

,

C

Z

, and

C

A

Table 2.4 Noise parameters for two-port network

Chapter 03

Table 3.1 Model parameters of the pn junction diode

Table 3.2 Comparison of three basic configurations

Chapter 04

Table 4.1 Band discontinuities for commonly used HBT material heterostructures

Table 4.2 A comparison chart for different device technologies in wireless communication RF transceiver applications

Table 4.3 GaAs HBT-based LNAs

Table 4.4 GaAs HBT-based PAs

Table 4.5 Comparison of InP HBT-based distributed modulator driver

Chapter 05

Table 5.1 Epitaxial structure of InP/InGaAs/InP DHBT

Table 5.2 The HBT parasitic elements

Table 5.3 Comparison of different methods for determination of extrinsic resistances

Chapter 06

Table 6.1 Comparison of small-signal, large-signal, linear, and nonlinear models

Table 6.2 Thermal constant for Ge, Si, and GaAs

Table 6.3 Comparison of electrical parameters and analogous thermal parameters

Chapter 07

Table 7.1 InP/InGaAs DHBT parasitics

Table 7.2 InP/InGaAs DHBT intrinsic parameters

Table 7.3 InP/InGaAs DHBT parasitic parameters with emitter area 1.6 × 20 µm

2

Table 7.4 InP/InGaAs DHBT parasitic parameters with emitter area 1.6 × 20 µm

2

Table 7.5 Extracted fitting factors of the noise parameters versus

I

C

Table 7.6

Z

-,

ABCD

-, and

S

-parameter relationships between CE and CB configurations

Table 7.7

Z

-,

ABCD

-, and

S

-parameter relationships between CE and CC configurations

List of Illustrations

Chapter 01

Figure 1.1 Cross section of a typical heterojunction bipolar transistor with a single emitter finger, two base contacts, and two collector contacts

Figure 1.2 Cross section of GaAs/AlGaAs HBT

Figure 1.3 Relationship between modeling and measurement

Chapter 02

Figure 2.1 Semiconductor device modeling concept: (a) physical structure and (b) basic circuit elements

Figure 2.2 A block diagram of a two-port network: (a) low frequency and (b) high frequency

Figure 2.3 |

H

21

| versus frequency for a transistor

Figure 2.4 Block diagram for calculation of

S

-parameters

Figure 2.5 Structure of coaxial cable with an air dielectric

Figure 2.6 Impedance noise representation of a noisy two-port network

Figure 2.7 Admittance noise representation of noisy two-port network

Figure 2.8 Chain noise representation of noisy two-port network

Figure 2.9 (a) Series and (b) shunt resistance networks

Figure 2.10 (a) Series and (b) shunt capacitance networks

Figure 2.11 (a) Series and (b) shunt

RC

networks

Figure 2.12 (a) Series and (b) shunt inductance networks

Figure 2.13 (a) Series and (b) shunt

RL

networks

Figure 2.14 Circuit model of voltage-controlled current source

Figure 2.15 Circuit model of voltage-controlled voltage source

Figure 2.16 Circuit model of current-controlled current source

Figure 2.17 Circuit model of current-controlled voltage source

Figure 2.18 Ideal transmission line

Figure 2.19 Shifting reference planes for a two-port network

Figure 2.20

T

-type network as a two-port network

Figure 2.21

π

-type network as a two-port network

Figure 2.22 Simplification procedure of complex

π

-type network: (a) complex

π

-type structure, (b) transformation of

T

-type network to the

π

-type network, and (c) simplified

π

-type network

Figure 2.23 Simplification procedure of complex

T

-type network: (a) complex

T

-type structure (b) transformation of

π

-type network to the

T

-type network, (c) simplified

T

-type network

Figure 2.24 Parasitic elements in parallel with DUT

Figure 2.25 Negative element method for parallel deembedding

Figure 2.26 Series elements in parallel with DUT

Figure 2.27 Negative element method for series deembedding

Figure 2.28 Equivalent circuit for cascading deembedding

Figure 2.29 Monolithic interdigital capacitor: (a) layout and (b) equivalent circuit model

Figure 2.30 Extracted capacitance versus frequency

Figure 2.31 Monolithic spiral inductor: (a) layout and (b) equivalent circuit model

Figure 2.32 Extracted inductance versus frequency

Figure 2.33 Resistances are in series with inductances and capacitances: (a)

RC

network and (b)

RL

network

Figure 2.34 Extracted resistance for

RC

series network

Figure 2.35 Extracted resistance for

RL

series network

Chapter 03

Figure 3.1 The pn junction with charge distribution in the absence of externally applied voltage

Figure 3.2 Built-in voltage of (a) silicon and (b) GaAs

Figure 3.3 The space charge region width of (a) silicon and (b) GaAs

Figure 3.4 Energy band diagram of intrinsic semiconductor

Figure 3.5 Energy band diagram of an n-type semiconductor

Figure 3.6 Energy band diagram of a p-type semiconductor

Figure 3.7 Energy band diagram of a pn junction with the terminals open circuit

Figure 3.8 Energy band diagram of a pn junction with an applied reverse-bias voltage

Figure 3.9 Energy band diagram of a pn junction with an applied forward-bias voltage

Figure 3.10 The space charge region width of (a) silicon-based and (b) GaAs-based pn diodes under different bias conditions

Figure 3.11 The pn diode I–V characteristic

Figure 3.12 Nonlinear equivalent circuit model of the pn junction diode

Figure 3.13 Linear equivalent circuit model of the pn junction diode

Figure 3.14 Behavior of diode capacitance as a function of the bias voltage

Figure 3.15 Noise equivalent circuit model of pn junction diode

Figure 3.16 Equivalent model of a noisy resistor: (a) series model and (b) parallel model

Figure 3.17 1/

f

noise versus frequency

Figure 3.18 The effect of extrinsic resistance on current of diode

Figure 3.19 1/

f

noise versus frequency for different semiconductor devices

Figure 3.20 A simplified structure and circuit symbol of npn BJT: (a) structure and (b) circuit symbol

Figure 3.21 A simplified structure and circuit symbol of PNP BJT: (a) structure and (b) circuit symbol

Figure 3.22 npn BJT structure (a) cross section and (b) cubic diagram

Figure 3.23 Idealized doping profiles of uniform doped (a) npn and (b) PNP BJTs

Figure 3.24 An npn BJT common-emitter configuration (a) and five operating modes (b)

Figure 3.25 The energy band diagram for zero mode of an npn BJT

Figure 3.26 The energy band diagram and electron flow for active mode of an npn BJT

Figure 3.27 The energy band diagram and electron flow for saturation mode of an npn BJT

Figure 3.28 The energy band diagram and electron flow for cutoff mode of an npn BJT

Figure 3.29 The energy band diagram and electron flow for inverse mode of an npn BJT

Figure 3.30 I–V characteristic of an npn BJT

Figure 3.31 The effect of base-width modulation on the Early I–V characteristics

Figure 3.32 Common-emitter current gain versus collector current

Figure 3.33 Cross section of an npn BJT showing the emitter crowding

Figure 3.34 Ebers–Moll model: injection version

Figure 3.35 Large-signal model of BJT operating in (a) active mode and (b) inverse mode

Figure 3.36 Ebers–Moll model: transport version

Figure 3.37 Complete Ebers–Moll large-signal model

Figure 3.38 Small-signal equivalent circuit model of BJT in normal bias condition

Figure 3.39 BJT Gummel–Poon large-signal model

Figure 3.40 Plot of ln(

I

C

) and ln(

I

B

) versus for

Figure 3.41 Forward and reverse measurements to determine BJT model parameters: (a) forward measurement and (b) reverse measurement

Figure 3.42 BJT noise equivalent circuit model

Figure 3.43 The three basic configurations of BJT amplifier: (a) common emitter, (b) common base, and (c) common collector

Figure 3.44 Intrinsic small-signal equivalent circuit model of BJT

Figure 3.45 Forward short-circuit current

H

21

versus frequency

Figure 3.46 Variation of

f

T

with

I

C

Figure 3.47 Equivalent circuit model of common-emitter configuration

Figure 3.48 Equivalent circuit model of common-base configuration

Figure 3.49 Equivalent circuit model of common-collector configuration

Chapter 04

Figure 4.1 Energy band diagrams of an nP heterojunction: (a) before contact and (b) after contact

Figure 4.2 Energy band diagrams of an Np heterojunction: (a) before contact and (b) after contact

Figure 4.3 Bandgap versus lattice constant for III–V semiconductors

Figure 4.4 Steady-state velocity–field characteristics for electrons in GaAs and Si

Figure 4.5 HBT combines the strengths of Si BJT and GaAs FET

Figure 4.6 The energy band diagram of an Npn GaAs/AlGaAs HBT: (a) zero mode and (b) active mode

Figure 4.7 Doping concentration versus position along direction of electron travel in npn bipolar transistors: (a) Si BJT and (b) GaAs/AlGaAs HBT

Figure 4.8 Common emitter current

I

C

versus

V

CE

for BJT and HBT

Figure 4.9 Comparison of Gummel plots for BJT and HBT

Figure 4.10 Comparison of cutoff frequency versus collector current for BJT and HBT

Figure 4.11 Typical topologies of the GaAs HBT-based low-noise amplifiers: (a) multifeedback, (b) Darlington, and (c) cascode

Figure 4.12 Typical topologies of the GaAs HBT-based power amplifiers

Figure 4.13 The velocity–field characteristics of In

0.53

Ga

0.47

As InP, GaAs

Figure 4.14 Device energy band diagrams (a) for a single heterojunction InP/InGaAs Npn HBT and (b) a double heterojunction InP/InGaAs NpN HBT

Figure 4.15 Cross section of a typical InP HBT with a single emitter finger, two base contacts, and two collector contacts

Figure 4.16 Schematic of InP HBT-based 40 Gb/s amplifier

Figure 4.17 Block diagram of the 40 Gb/s distributed modulator driver

Chapter 05

Figure 5.1 GSG coplanar probe

Figure 5.2 (a) Pad structure and (b) equivalent circuit model

Figure 5.3 Intrinsic HBT T-type model

Figure 5.4 Intrinsic HBT

π

-type model: (a)

g

m

mode and (b)

β

mode

Figure 5.5 Conditions for Mason’s gain (embedded within a linear lossless reciprocal four-port)

Figure 5.6 HBT layout

Figure 5.7 Open test structure (a) and equivalent circuit model (b)

Figure 5.8 Frequency dependence of pad capacitances

Figure 5.9 Comparison of modeled and measured

S

parameters for open test structure: (a)

S

11

, (b)

S

22

, and (c)

S

21

Figure 5.10 Small-signal equivalent circuit model of HBT under pinch-off bias condition at low frequencies

Figure 5.11 Plot of versus

V

be

Figure 5.12 The (a) short test structure and (b) equivalent circuit model

Figure 5.13 Frequency dependence of the extrinsic inductances: (a) base inductance, (b) collector inductance, and (c) emitter inductance

Figure 5.14 Frequency dependence of the feed line losses

Figure 5.15 Comparison of modeled and measured

S

parameters for short test structure: (a)

S

11

, (b)

S

22

, and (c)

S

12

Figure 5.16 Schematic of open-collector method

Figure 5.17 Schematic of extrinsic inductance under open-collector bias condition

Figure 5.18 Evolution of the imaginary parts of the

Z

parameters versus

ω

when the device is forward biased

Figure 5.19 Plot of Real(

Z

12

) versus 1/

I

E

,

f

 = 1 GHz

Figure 5.20 Small-signal equivalent circuit for InP HBT under cutoff bias condition

Figure 5.21 Extracted versus frequency under cutoff bias condition

Figure 5.22 Extracted

C

ex

versus frequency under cutoff bias condition

Figure 5.23 Extracted

R

bi

versus frequency under cutoff bias condition

Figure 5.24 Extracted

C

be

versus frequency under cutoff bias condition

Figure 5.25 Extracted

R

bx

versus frequency under cutoff bias condition

Figure 5.26 Extracted

R

c

versus frequency under cutoff bias condition

Figure 5.27 Comparison of modeled and measured

S

parameter for the InP HBT. Bias conditions: (a) and and (b) and

Figure 5.28 Intrinsic HBT equivalent circuit model with extrinsic resistances under open-collector bias condition at low frequencies

Figure 5.29 Plots of real part of ,

Z

21

, and

Z

12

versus 1/

I

B

Figure 5.30 Plot of real part of versus

I

B

Figure 5.31 Extracted |

α

(

ω

)| versus frequency at

Figure 5.32 Extracted

α

o

versus

I

B

and

V

CE

Figure 5.33 Extracted

f

α

versus frequency at

Figure 5.34 Extracted

f

α

versus

I

B

and

V

CE

Figure 5.35 Extracted

τ

versus frequency at

Figure 5.36 Extracted

τ

versus

I

B

and

V

CE

Figure 5.37 Extracted

C

ex

versus frequency at

Figure 5.38 Comparison of modeled and measured

C

ex

versus

V

CB

Figure 5.39 Extracted

C

bc

versus frequency at

Figure 5.40 Extracted

C

bc

versus

I

B

and

V

CE

Figure 5.41 Extracted

R

bi

versus frequency at

Figure 5.42 Comparison of modeled and measured

R

bi

versus

V

BE

Figure 5.43 Extracted

R

be

versus frequency at

Figure 5.44 Extracted

R

be

versus

I

B

and

V

CE

Figure 5.45 Extracted

C

be

versus frequency at

Figure 5.46 Extracted

C

be

versus

I

B

and

V

CE

Figure 5.47 Comparison of modeled and measured

S

parameter for the InP HBT. Bias conditions: (a) and , (b) and , and (c) and

Figure 5.48 Comparison of modeled and measured

H

21

parameters

Figure 5.49 Extracted

τ

π

and

τ

T

versus frequency. Bias condition: and

Figure 5.50 Comparison between

g

mo

and versus frequency. Bias condition: and

Figure 5.51 Extracted

C

be

using T-type circuit topology. Bias condition:

Figure 5.52 Extracted

C

be

using Π-type circuit topology

Figure 5.53 Comparison of modeled and measured

C

be

versus

V

be

Figure 5.54 Intrinsic part extended by

C

pb

,

L

b

,

L

e

,

R

bx

, and

R

e

Figure 5.55 Algorithm

Figure 5.56 Extracted capacitances for InP HBT under cutoff condition

Figure 5.57 Plots of Re(

Z

11

), , and versus frequency for InP HBT under cutoff condition

Figure 5.58 Comparison of modeled and measured

S

parameters for the InP HBT. Bias condition: and . (a)

S

11

, (b)

S

12

, (c)

S

21

, and (d)

S

22

Figure 5.59 Comparison of modeled and measured

S

parameters for the InP HBT. Bias condition: and . (a)

S

11

, (b)

S

12

, (c)

S

21

, and (d)

S

22

Figure 5.60 Comparison of modeled and measured

S

parameters for the InP HBT. Bias condition: and . (a)

S

11

, (b)

S

12

, (c)

S

21

, and (d)

S

22

Chapter 06

Figure 6.1 Comparison of small-signal model and large-signal model

Figure 6.2 The definition of 1-dB gain compression point

Figure 6.3 Input and output power spectrum: (a) linear network and (b) nonlinear network

Figure 6.4 (a) Linear resistance and (b) nonlinear resistance

Figure 6.5 Equivalent circuit model of nonlinear resistance

Figure 6.6 (a) Linear capacitance and (b) nonlinear capacitance

Figure 6.7 Equivalent circuit model of nonlinear capacitance

Figure 6.8 Equivalent circuit model of nonlinear capacitance controlled by two voltages

Figure 6.9 (a) Nonlinear current source and (b) corresponding equivalent circuit model

Figure 6.10 The relationship between nonlinear elements and linear elements

Figure 6.11 The DC operating point under large signal condition. (a) Ideal pulse signal, (b) input signal, and (c) DC operating point

Figure 6.12 Path of heat flow for semiconductor junction

Figure 6.13 Path of heat flow for semiconductor junction with heat sink

Figure 6.14 Schematic diagram of power device heat conduction model in three dimensions: (a) single-finger HBT and (b) multifinger HBT

Figure 6.15 Modeling concept of HBT with self-heating effect

Figure 6.16 Transmission line equivalent circuit model

Figure 6.17 Thermal model based on transmission line equivalent circuit diagram

Figure 6.18 General thermal model for packaging devices

Figure 6.19 The most frequently used series thermal model

Figure 6.20 Effect of thermal resistance on

V

BE

and

I

C

. (a) Base-emitter voltage and (b) collector current

Figure 6.21 Collector current

I

C

versus substrate temperature

T

d

at constant

I

B

Figure 6.22 Collector current

I

C

versus

V

CE

and

P

diss

. (a)

I

C

versus

V

CE

and (b)

I

C

versus

P

diss

Figure 6.23 Base–emitter voltage

V

BE

versus temperature

T

Figure 6.24 Base–emitter voltage

V

BE

versus power dissipation

P

diss

Figure 6.25 Collector current

I

C

versus

V

CE

at a constant

I

B

for three ambient temperatures

Figure 6.26

R

th

versus

P

diss

and

T

d

. (a)

R

th

versus

P

diss

and (b)

R

th

versus

T

d

Figure 6.27 Equivalent schematic of the VBIC model: (a) NPN and (b) PNP

Figure 6.28 VBIC equivalent circuit model for NPN transistor: (a) electrical model and (b) thermal model

Figure 6.29 Large-signal topology of the Agilent HBT model: (a) electrical model and (b) thermal model

Figure 6.30 Equivalent circuit model of intrinsic part

Figure 6.31 Agilent HBT small-signal model

Figure 6.32 HBT macromodel based on SGP model

Figure 6.33 Nonlinear HBT macromodel based on

π

-type model

Chapter 07

Figure 7.1 A flowchart for FET noise modeling

Figure 7.2 HBT noise equivalent circuit model: (a) extrinsic part and (b) intrinsic part

Figure 7.3 HBT small-signal and noise equivalent circuit model

Figure 7.4 Comparison of modeled and measured

S

-parameter for the InP HBT. Bias condition: (a) , , (b) , , and (c) , . The squares indicate the measured values and the lines the modeled ones

Figure 7.5 Comparison of measured and calculated noise parameters. Bias condition: , . (a) Minimum noise figure and normalized noise resistance and (b) optimum source admittance

Figure 7.6 Comparison of measured and calculated noise parameters. Bias condition: , . (a) Minimum noise figure and normalized noise resistance and (b) optimum source admittance

Figure 7.7 Comparison of measured and calculated noise parameters. Bias condition: , . (a) Minimum noise figure and normalized noise resistance and (b) optimum source admittance

Figure 7.8 Comparison of measured and calculated noise parameters versus

V

ce

and

I

b

at 16 GHz. (a) Minimum noise figure, (b) normalized noise resistance, (c) magnitude of optimum source admittance, and (d) angle of optimum source admittance

Figure 7.9 Comparison of measured and calculated noise parameters. Bias condition: . (a) minimum noise figure, (b) normalized noise resistance, (c) magnitude of optimum source admittance, and (d) angle of optimum source admittance

Figure 7.10 Tuner-based noise parameter measurement system

Figure 7.11 Typical source reflection coefficient distributed Smith chart

Figure 7.12 Commercial noise parameter measurement setup

Figure 7.13 Block diagram of input and output network measurement

Figure 7.14 Microwave transistor

S

-parameter and noise measurement setup based on 50 Ω system

Figure 7.15 Measured source reflection coefficient versus frequency

Figure 7.16 Comparison of measured and modeled noise figure

F

50

for InP HBT. Bias condition:

I

b

 = 60 μA,

V

CE

 = 2.0 V (

I

C

 = 3.08 mA)

Figure 7.17 Comparison of measured and computed noise parameters with the new method versus frequency. Bias condition

I

b

 = 60 μA,

V

CE

 = 2.0 V (

I

C

 = 3.1 mA). (a) Minimum noise figure and noise resistance and (b) optimum source admittance

Figure 7.18 Comparison of measured and calculated noise parameters versus

I

c

at

f

 = 12 GHz. (a) minimum noise figure, (b) noise resistance, (c) magnitude of optimum source admittance, and (d) angle of optimum source admittance

Figure 7.19 CE configurations of HBT. (a) CE schematic and (b) equivalent circuit model

Figure 7.20 CB configurations of HBT. (a) CB schematic and (b) equivalent circuit model

Figure 7.21 CC configurations of HBT. (a) CC schematic and (b) equivalent circuit model

Figure 7.22 Comparison of modeled and predicted

S

-parameters for 5 × 5 µm

2

InP HBT in CB configuration, bias condition:

I

b

 = 50 μA,

V

CE

 = 2.0 V;—calculated data from equivalent circuit model, predicted data from CE configuration

Figure 7.23 Comparison of modeled and predicted

S

-parameters for the InP HBT in CC configuration, bias condition:

I

b

 = 50 μA, V

CE

 = 2.0 V;—calculated data from equivalent circuit model, predicted data from CE configuration

Figure 7.24 HBT noise equivalent circuit models of (a) CE, (b) CB, and (c) CC configurations

Figure 7.25 Noise sources transformation between CE and CB configurations

Figure 7.26 Noise sources transformation between CE and CC configurations

Figure 7.27 Comparison of modeled and predicted noise parameters for 5 × 5 µm

2

InP HBT in CB configuration, bias condition:

I

b

 = 50 μA,

V

CE

 = 2.0 V;—calculated data from equivalent circuit model, predicted data from noise measurement of CE configuration

Figure 7.28 Comparison of modeled and predicted noise parameters for 5 × 5 µm

2

InP HBT in CC configuration, bias condition:

I

b

 = 50 μA,

V

CE

 = 2.0 V;—calculated data from equivalent circuit model, predicted data from noise measurement of CE configuration

Figure 7.29 Comparison of modeled and predicted noise parameters for 5 × 5 µm

2

InP HBT in CB configuration at low frequency ranges, bias condition:

I

b

 = 50 μA,

V

CE

 = 2.0 V;—calculated data from equivalent circuit model, predicted data from noise measurement of CE configuration

Figure 7.30 Comparison of modeled and predicted noise parameters for 5 × 5 µm

2

InP HBT in CC configuration at low frequency ranges, bias condition:

I

b

 = 50 μA,

V

CE

 = 2.0 V;—calculated data from equivalent circuit model, predicted data from noise measurement of CE configuration

Chapter 08

Figure 8.1 Energy band diagram of a graded-base SiGe HBT compared to an Si BJT

Figure 8.2 SiGe HBT small-signal model: (a) PAD and feedline model, (b) T-type model, and (c)

π

-type model

Figure 8.3 Equivalent circuit model of open test structure

Figure 8.4 Extracted pad capacitances versus frequency

Figure 8.5 Extracted substrate losses versus frequency

Figure 8.6 Small-signal equivalent circuit model of SiGe HBT under cutoff bias condition (a) at low frequency and (b) at high frequency

Figure 8.7 Extracted collector–substrate capacitance

C

sub

versus frequency

Figure 8.8 Comparison of intrinsic base resistance

R

bi

for InP HBT and SiGe HBT

Figure 8.9 HICUM equivalent circuit model: (a) large-signal model and (b) small signal model

Figure 8.10 MEXTRAM equivalent circuit model

Guide

Cover

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HETEROJUNCTION BIPOLAR TRANSISTORS FOR CIRCUIT DESIGN

MICROWAVE MODELLING AND PARAMETER EXTRACTION

Jianjun Gao

East China Normal UniversityShanghai, P.R. China

This edition first published 2015© 2015 Higher Education Press

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Library of Congress Cataloging-in-Publication Data

Gao, Jianjun, 1968-Heterojunction bipolar transistors for circuit design : microwave modeling and parameter extraction / Jianjun Gao.      pages   cm   Includes bibliographical references and index.

   ISBN 978-1-118-92152-4 (cloth)1. Bipolar transistors.   2. Heterojunctions.   3. Electronic circuit design.   4. Microwave measurements.   I. Title.   TK7871.96.B55G36 2015   621.3815′28--dc23

            2015002782

About the Author

Jianjun Gao was born in Hebei province, P.R. China, in 1968. He received his B.E. and Ph.D. degrees from Tsinghua University, in 1991 and 1999, respectively, and M.E. degree from Hebei Semiconductor Research Institute in 1994.

From 1999 to 2001, he was a postdoctoral research fellow at the Microelectronics R&D Center, Chinese Academy of Sciences, developing PHEMT optical modulator driver. In 2001, he joined the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, as a research fellow in semiconductor device modeling and wafer measurement. In 2003, he joined the Institute of High-Frequency and Semiconductor System Technologies, Berlin University of Technology, Germany, as a research associate working on the InP HBT modeling and circuit design for high-speed optical communication. In 2004, he joined the Electronics Engineering Department, Carleton University, Canada, as a postdoctoral fellow working on the semiconductor neural network modeling technique. From 2004 to 2007, he was a full professor of radio engineering department at the Southeast University, Nanjing, China. Since 2007, he has been a full professor at the School of Information Science and Technology, East China Normal University, Shanghai, China. He authored RF and Microwave Modeling and Measurement Techniques for Field Effect Transistors (SciTech Publishing, 2009) and Optoelectronic Integrated Circuit Design and Device Modeling (Wiley, 2010).

His main areas of research are characterization, modeling, and wafer measurement of microwave semiconductor devices, optoelectronics devices, and high-speed integrated circuit for radio frequency and optical communication.

Readers can refer to http://faculty.ecnu.edu.cn/gaojianjun/Info_eng.html for further details about of the author.

Preface

This textbook is written for beginners learning about the characterization of heterojunction bipolar transistors. My purposes are as follows:

To describe the basic modeling techniques for semiconductor devices

To introduce the basic concepts of heterojunction bipolar transistor

To provide state-of-the-art modeling and equivalent circuit parameter extraction methods for heterojunction bipolar transistor

Appropriate for electrical engineering and computer science, this book starts with an introduction of signal and noise parameters of two-port networks and then covers the basic operation mechanisms and modeling techniques for bipolar junction transistor and heterojunction bipolar transistor; the corresponding equivalent circuit model parameter extraction methods are introduced in detail. Readers can understand this book without a good grounding in microwave theory and concepts. The presentation of this book assumes only a basic course in electronic circuits as a prerequisite.