Microwave Circuit Design Using Linear and Nonlinear Techniques E-Book

George D. Vendelin

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 1670

Veröffentlichungsjahr: 2021

Beschreibung

Four leaders in the field of microwave circuit design share their newest insights into the latest aspects of the technology

The third edition of Microwave Circuit Design Using Linear and Nonlinear Techniques delivers an insightful and complete analysis of microwave circuit design, from their intrinsic and circuit properties to circuit design techniques for maximizing performance in communication and radar systems. This new edition retains what remains relevant from previous editions of this celebrated book and adds brand-new content on CMOS technology, GaN, SiC, frequency range, and feedback power amplifiers in the millimeter range region. The third edition contains over 200 pages of new material.

The distinguished engineers, academics, and authors emphasize the commercial applications in telecommunications and cover all aspects of transistor technology. Software tools for design and microwave circuits are included as an accompaniment to the book. In addition to information about small and large-signal amplifier design and power amplifier design, readers will benefit from the book's treatment of a wide variety of topics, like:

• An in-depth discussion of the foundations of RF and microwave systems, including Maxwell's equations, applications of the technology, analog and digital requirements, and elementary definitions
• A treatment of lumped and distributed elements, including a discussion of the parasitic effects on lumped elements
• Descriptions of active devices, including diodes, microwave transistors, heterojunction bipolar transistors, and microwave FET
• Two-port networks, including S-Parameters from SPICE analysis and the derivation of transducer power gain

Perfect for microwave integrated circuit designers, the third edition of Microwave Circuit Design Using Linear and Nonlinear Techniques also has a place on the bookshelves of electrical engineering researchers and graduate students. It's comprehensive take on all aspects of transistors by world-renowned experts in the field places this book at the vanguard of microwave circuit design research.

Leseprobe

Table of Contents

Cover

Title Page

Copyright

FOREWORD

PREFACE TO THE THIRD EDITION

Chapter 1: RF/MICROWAVE SYSTEMS

1.1 INTRODUCTION

1.2 MAXWELL’S EQUATIONS

1.3 FREQUENCY BANDS, MODES, AND WAVEFORMS OF OPERATION

1.4 ANALOG AND DIGITAL SIGNALS

1.5 ELEMENTARY FUNCTIONS

1.6 BASIC RF TRANSMITTERS AND RECEIVERS

1.7 RF WIRELESS/MICROWAVE/MILLIMETER WAVE APPLICATIONS

1.8 MODERN CAD FOR NONLINEAR CIRCUIT ANALYSIS

1.9 DYNAMIC LOAD LINE

REFERENCES

BIBLIOGRAPHY

PROBLEMS

CHAPTER 2: LUMPED AND DISTRIBUTED ELEMENTS

2.1 INTRODUCTION

2.2 TRANSITION FROM RF TO MICROWAVE CIRCUITS

2.3 PARASITIC EFFECTS ON LUMPED ELEMENTS

2.4 DISTRIBUTED ELEMENTS

2.5 HYBRID ELEMENT: HELICAL COIL

REFERENCES

BIBLIOGRAPHY

PROBLEMS

CHAPTER 3: ACTIVE DEVICES

3.1 INTRODUCTION

3.2 DIODES

1

3.3 MICROWAVE TRANSISTORS

3.4 EXAMPLE: SELECTING TRANSISTOR AND BIAS FOR LOW-NOISE AMPLIFICATION

3.5 EXAMPLE: SELECTING TRANSISTOR AND BIAS FOR OSCILLATOR DESIGN

3.6 EXAMPLE: SELECTING TRANSISTOR AND BIAS FOR POWER AMPLIFICATION

REFERENCES

BIBLIOGRAPHY

PROBLEMS

Notes

CHAPTER 4: TWO-PORT NETWORKS

4.1 INTRODUCTION

4.2 TWO-PORT PARAMETERS

4.3

S

PARAMETERS

4.4

S

PARAMETERS FROM SPICE ANALYSIS

4.5 MASON GRAPHS

4.6 STABILITY

4.7 POWER GAINS, VOLTAGE GAIN, AND CURRENT GAIN

4.8 THREE-PORTS

4.9 DERIVATION OF TRANSDUCER POWER GAIN

4.10 DIFFERENTIAL PARAMETERS

4.11 TWISTED-WIRE PAIR LINES

4.12 LOW-NOISE AND HIGH-POWER AMPLIFIER DESIGN

4.13 LOW-NOISE AMPLIFIER DESIGN EXAMPLES

REFERENCES

BIBLIOGRAPHY

PROBLEMS

CHAPTER 5: IMPEDANCE MATCHING

5.1 INTRODUCTION

5.2 SMITH CHARTS AND MATCHING

5.3 IMPEDANCE MATCHING NETWORKS

5.4 SINGLE-ELEMENT MATCHING

5.5 TWO-ELEMENT MATCHING

5.6 MATCHING NETWORKS USING LUMPED ELEMENTS

5.7 MATCHING NETWORKS USING DISTRIBUTED ELEMENTS

5.8 BANDWIDTH CONSTRAINTS FOR MATCHING NETWORKS

REFERENCES

BIBLIOGRAPHY

PROBLEMS

CHAPTER 6: MICROWAVE FILTERS

6.1 INTRODUCTION

6.2 LOW-PASS PROTOTYPE FILTER DESIGN

6.3 TRANSFORMATIONS

6.4 TRANSMISSION LINE FILTERS

6.5 EXACT DESIGNS AND CAD TOOLS

6.6 REAL-LIFE FILTERS

REFERENCES

BIBLIOGRAPHY

PROBLEMS

CHAPTER 7: NOISE IN LINEAR AND NONLINEAR TWO-PORTS

7.1 INTRODUCTION

7.2 SIGNAL-TO-NOISE RATIO

7.3 NOISE FIGURE MEASUREMENTS

7.4 NOISE PARAMETERS AND NOISE CORRELATION MATRIX

7.5 NOISY TWO-PORT DESCRIPTION

7.6 NOISE FIGURE OF CASCADED NETWORKS

7.7 INFLUENCE OF EXTERNAL PARASITIC ELEMENTS

7.8 NOISE CIRCLES

7.9 NOISE CORRELATION IN LINEAR TWO-PORTS USING CORRELATION MATRICES

7.10 NOISE FIGURE TEST EQUIPMENT

7.11 HOW TO DETERMINE NOISE PARAMETERS

7.12 NOISE IN NONLINEAR CIRCUITS

7.13 TRANSISTOR NOISE MODELING

REFERENCES

BIBLIOGRAPHY

PROBLEMS

Note

CHAPTER 8: SMALL- AND LARGE-SIGNAL AMPLIFIER DESIGN

8.1 INTRODUCTION

8.2 SINGLE-STAGE AMPLIFIER DESIGN

8.3 FREQUENCY MULTIPLIERS

8.4 DESIGN EXAMPLE OF 1.9-GHZ PCS AND 2.1-GHZ W-CDMA AMPLIFIERS

8.5 STABILITY ANALYSIS AND LIMITATIONS

REFERENCES

BIBLIOGRAPHY

PROBLEMS

CHAPTER 9: POWER AMPLIFIER DESIGN

9.1 INTRODUCTION

9.2 CHARACTERIZING TRANSISTORS FOR POWER-AMPLIFIER DESIGN

9.3 SINGLE-STAGE POWER AMPLIFIER DESIGN

9.4 MULTISTAGE DESIGN

9.5 POWER-DISTRIBUTED AMPLIFIERS

9.6 CLASS OF OPERATION

9.7 EFFICIENCY AND LINEARITY ENHANCEMENT PA TOPOLOGIES

9.8 DIGITAL MICROWAVE POWER AMPLIFIERS (CLASS-D/S)

2

9.9 POWER AMPLIFIER STABILITY

REFERENCES

BIBLIOGRAPHY

PROBLEMS

Notes

CHAPTER 10: OSCILLATOR DESIGN

10.1 INTRODUCTION

10.2 COMPRESSED SMITH CHART

10.3 SERIES OR PARALLEL RESONANCE

10.4 RESONATORS

10.5 TWO-PORT OSCILLATOR DESIGN

10.6 NEGATIVE RESISTANCE FROM TRANSISTOR MODEL

10.7 OSCILLATOR AND OUTPUT POWER

10.8 NOISE IN OSCILLATORS: LINEAR APPROACH

10.9 ANALYTIC APPROACH TO OPTIMUM OSCILLATOR DESIGN USING

S

PARAMETERS

10.10 NONLINEAR ACTIVE MODELS FOR OSCILLATORS

10.11 OSCILLATOR DESIGN USING NONLINEAR CAD TOOLS

10.12 MICROWAVE OSCILLATORS PERFORMANCE

10.13 DESIGN OF AN OSCILLATOR USING LARGE-SIGNAL PARAMETERS

10.14 EXAMPLE FOR LARGE-SIGNAL DESIGN BASED ON BESSEL FUNCTIONS

10.15 DESIGN EXAMPLE FOR BEST PHASE NOISE AND GOOD OUTPUT POWER

10.16 A DESIGN EXAMPLE FOR A 350MHZ FIXED FREQUENCY COLPITTS OSCILLATOR

10.17 1/ NOISE

10.18 2400MHZ MOSFET-BASED PUSH–PULL OSCILLATOR

10.19 CAD SOLUTION FOR CALCULATING PHASE NOISE IN OSCILLATORS

10.20 PHASE NOISE MEASUREMENT

10.21 BACK TO CONVENTIONAL PHASE NOISE MEASUREMENT SYSTEM (HEWLETT-PACKARD)

10.22 STATE-OF-THE-ART

10.23 INSTRUMENT PERFORMANCE

10.24 NOISE IN CIRCUITS AND SEMICONDUCTORS [10.74]

10.25 VALIDATION CIRCUITS

10.26 ANALYTICAL APPROACH FOR DESIGNING EFFICIENT MICROWAVE FET AND BIPOLAR OSCILLATORS (OPTIMUM POWER)

10.27 INTRODUCTION

10.28 LARGE SIGNAL NOISE ANALYSIS

10.29 QUANTIFYING PHASE NOISE

10.30 SUMMARY

REFERENCES

BIBLIOGRAPHY

PROBLEMS

CHAPTER 11: FREQUENCY SYNTHESIZER

11.1 INTRODUCTION

11.2 BUILDING BLOCK OF SYNTHESIZER

11.3 IMPORTANT CHARACTERISTICS OF SYNTHESIZERS

11.4 PRACTICAL CIRCUITS

11.5 THE FRACTIONAL-N PRINCIPLE

11.6 SPUR-SUPPRESSION TECHNIQUES

11.7 DIGITAL DIRECT FREQUENCY SYNTHESIZER

REFERENCES

CHAPTER 12: MICROWAVE MIXER DESIGN

12.1 INTRODUCTION

12.2 DIODE MIXER THEORY

12.3 SINGLE-DIODE MIXERS

12.4 SINGLE-BALANCED MIXERS

12.5 DOUBLE-BALANCED MIXERS

12.6 FET MIXER THEORY

12.7 BALANCED FET MIXERS

12.8 RESISTIVE (REFLECTIVE) FET MIXERS

12.9 SPECIAL MIXER CIRCUITS

12.10 MIXER NOISE

REFERENCES

BIBLIOGRAPHY

PROBLEMS

Note

CHAPTER 13: RF SWITCHES AND ATTENUATORS

13.1

Pin

Diodes

13.2

Pin

Diode Switches

13.3

Pin

Diode Attenuators

13.4 FET SWITCHES

REFERENCES

BIBLIOGRAPHY

CHAPTER 14: SIMULATION OF MICROWAVE CIRCUITS

14.1 INTRODUCTION

14.2 DESIGN TYPES

14.3 DESIGN ENTRY

14.4 LINEAR CIRCUIT SIMULATION

14.5 NONLINEAR SIMULATION

14.6 ELECTROMAGNETIC SIMULATION

14.7 DESIGN FOR MANUFACTURING

14.8 OSCILLATOR DESIGN AND SIMULATION EXAMPLE

14.9 CONCLUSION

REFERENCES

NOTES

APPENDIX A: DERIVATIONS FOR UNILATERAL GAIN SECTION

APPENDIX B: VECTOR REPRESENTATION OF TWO-TONE INTERMODULATION PRODUCTS

B.1 INTRODUCTION

B.2 SINGLE-TONE ANALYSIS

B.3 TWO-TONE ANALYSIS

B.4 BIAS-INDUCED DISTORTION

B.5 SUMMARY

B.6 SINGLE-TONE VOLTERRA SERIES EXPANSION

B.7 NONLINEAR PARALLEL RC NETWORK

ACKNOWLEDGMENTS

REFERENCES

BIBLIOGRAPHY

APPENDIX C: PASSIVE MICROWAVE ELEMENTS

C.1 INTRODUCTION

C.2 LUMPED ELEMENTS

RESISTOR (THIN FILM, ETC.)

CAPACITOR (THIN FILM, ETC.)

BOND WIRE

DIODES (BEAM LEAD, ETC)

C.3 DISTRIBUTED ELEMENTS

C.4 DISCONTINUITIES

C.5 MONOLITHIC ELEMENTS

C.6 Special-Purpose Elements

REFERENCES

INDEX

End User License Agreement

List of Tables

Chapter 1

TABLE 1.1 Historical Events in Communications

TABLE 1.2

Wireless Applications [1.27]

TABLE 1.3

Frequency Bands

TABLE 1.4

RF/Wireless Applications

Chapter 2

TABLE 2.1

Chip Resistor Versus Size and Typical Parasitic

and

Chapter 3

TABLE 3.1

Large-Signal Microwave Diode Model Keywords

TABLE 3.2

Diode SPICE Parameters

TABLE 3.3

LO Power and

for Various Applications

TABLE 3.4

X-Band Mixer Diode Data

TABLE 3.5

Linear Diode Model Keywords

TABLE 3.6

PIN Diode Model Keywords

TABLE 3.7

Parameters for 0.6-pF Diode

TABLE 3.8

Versus Bias for 0.6-pF Diode

TABLE 3.9

Capacitance Ratios (

)

TABLE 3.10

Comparative Tuning Diodes

TABLE 3.11

Typical Layer Structure of InGaP/GaAs HBT with

40 GHz at

V, and

V

TABLE 3.12

Typical Layer Structure of InP Transfer-Substrate DHBT with 400 GHz

...

TABLE 3.13

Typical Layer Structure of an mHEMT

Chapter 4

TABLE 4.1

Two-Port Parameters:

with

TABLE 4.2

Normalized Resistors for Tee Attenuator

TABLE 4.3

Avago PHEMTs

TABLE 4.4

Parameters for ATF34143 PHEMT at 4 V, 60 mA

TABLE 4.5

Nine Power Gains

TABLE 4.6

Modified Materka Nonlinear Model for 335-

m MESFET: Keysight ADS Format

...

Chapter 5

TABLE 5.1

Solutions to Impedance Matching Example

TABLE 5.2

Load

Chapter 6

TABLE 6.1

Chebyshev

Values

Chapter 7

TABLE 7.1

Noise Correlation Matrix Transformations

TABLE 7.2

Transformation of Noise Parameters

TABLE 7.3

Transformation of Noise Parameters (

Continued

)

TABLE 7.4

Base and Collector Layer Specification of the Investigated Wafers

Chapter 8

TABLE 8.1 Temperature Properties of Active Bias Circuits

TABLE 8.2

Parameters of MWT-7: Circuits A, B, and C at 18 GHz

TABLE 8.3

Performance of Circuits D and E at 18 GHz

TABLE 8.4

Cascode Amplifier Circuit Parameters

TABLE 8.5

Gummel–Poon Model for Infineon BFP620: Transitor Chip Data

TABLE 8.6

Temperature Response of Cascode Amplifier (1–8 GHz)

TABLE 8.7

ATF-55143 Typical Parameters at

V,

mA

TABLE 8.8

Amplifier Parts List

TABLE 8.9

Performance of 1.9-GHz Amplifier

Chapter 9

TABLE 9.1

Optimum Load Impedance at Fundamental and Harmonic Frequencies

TABLE 9.2

FET Load Impedance with Monolithic Distributed Bandpass Matching Networ

...

TABLE 9.3

Key Performance Variations of a Single-Stage Amplifier as a Function of

...

TABLE 9.4

Performance Goals for Power Dual-Gate FET Distributed-Amplifier Design

...

TABLE 9.5

Basic Amplifier Design Parameters Obtained with FET Model of Figure 9.3

...

TABLE 9.6

Basic Amplifier Design Parameters Obtained by Adding a Series Gate Capa

...

TABLE 9.7

Input and Output Impedances as a Function of Frequency for WCDMA Push-P

...

TABLE 9.8

Theoretical maximum efficiency of class-F PAs.

Source: (Based on Raab [...

TABLE 9.9

Dependence of Class-E circuit elements on loaded

and output power.

TABLE 9.10

Comparison of voltage- and current-mode final-stage topology in a digi

...

Chapter 10

TABLE 10.1

Specifications for Major Types of Oscillators

TABLE 10.2

SPICE Parameters and Package Parameters of NEC Transistor NE68830

TABLE 10.3

Physical Dimensions of DR

TABLE 10.4

Resonator Parameters

TABLE 10.5

HP2001 Bipolar Chip Common Base (

,

)

TABLE 10.6

Supercompact File for DRO Design in Figure 10.37

TABLE 10.7

Calculation of VCO Tuning Range

TABLE 10.8

Parameters for NEC 869177

TABLE 10.9

Design Values for the 5-GHz Oscillator

TABLE 10.10

Large-Signal Microwave Diode Model

TABLE 10.11

Diode SPICE Parameters

TABLE 10.12

Parameter Values of the FET Model

TABLE 10.13

Nonlinear Parameters of NE68830

TABLE 10.14

Package Parameters of NE68830

TABLE 10.15

Large Signal Transconductance as a Function of Drive Level based on B

...

TABLE 10.16

Correction Factor if the Phase Noise of the Reference Oscillator is N

...

Chapter 11

TABLE 11.1

Spur-suppression Methods

Chapter 12

TABLE 12.1

Mixer topology performance considerations.

Chapter 13

TABLE 13.1

Plastic Surface-Mount pin Diode Model Parameters for Forward- and Reve

...

TABLE 13.2

GaAs

pin

Diode Small-Signal Model Parameter Values

Chapter 14

TABLE 14.1

Comparison of EM simulation methods.

TABLE 14.2 With 100 trials, for a given confidence (column 1), the actual standa

...

TABLE 14.3 At 95% confidence, for a given number of trials (column 1), the actua

...

TABLE 14.4

Oscillator simulated and measured output spectrum.

TABLE 14.5

Comparison of simulation methods for different types of circuits and t

...

List of Illustrations

Chapter 1

FIGURE 1.1 First GaAs MESFET amplifiers for 12-GHz satellite application for...

FIGURE 1.2 Crystal radio receiver or foxhole radio. (From Lee [1.13].)

FIGURE 1.3 Frequency spectrum of radio receiver.

FIGURE 1.4 (

a

) Heterodyne receiver, single-conversion superheterodyne receiv...

FIGURE 1.5 Geometry for microwave transmission.

FIGURE 1.6 Lumped-element equivalent circuit of transmission line.

FIGURE 1.7 (

a

) Characteristic impedance for (i) narrow and (ii) wide microst...

FIGURE 1.8 (

a

) Effective dielectric constant for (i) narrow and (ii) wide mi...

FIGURE 1.9 Four antennas illustrating Maxwell’s four equations: (

a

) electric...

FIGURE 1.10 Constellation diagram for (

a

) QAM (

quadrature phase shift keying

FIGURE 1.11 Block diagram of a digital single-carrier modulation system.

FIGURE 1.12 Constellation diagrams drawn in continuous time for a random bit...

FIGURE 1.13 Complex envelope of an MSK-coded signal as a function of time.

FIGURE 1.14 Block diagram of a baseband CDMA modulation and demodulation sys...

FIGURE 1.15

a

Auto- and

b

crosscorrelation functions of pseudo-random signal...

FIGURE 1.16 Block diagram of a baseband OFDM modulation (

a

) and demodulation...

FIGURE 1.17 Time-domain OFDM signal.

FIGURE 1.18 Frequency-domain OFDM signal, showing spectral regrowth due to c...

FIGURE 1.19 Block diagram of a baseband

single-carrier frequency-domain-equa

...

FIGURE 1.20 Simplified wireless communication system. (From Chang [1.33].)

FIGURE 1.21 Attenuation for coaxial and antenna system communications. (Rizz...

FIGURE 1.22 Dynamic range.

FIGURE 1.23 Output power spectrum for two input signals.

FIGURE 1.24 Spurious-free dynamic range.

FIGURE 1.25 ACPR for a MWT-213011-82 amplifier. (Courtesy of Microwave Techn...

FIGURE 1.26 IP3 or TOI of MWT-213011-82 amplifier versus

. (Courtesy of Mic...

FIGURE 1.27 Typical radio receiver. (From Chang [1.38].)

FIGURE 1.28 Transmitter system. (From Chang [1.38].)

FIGURE 1.29 Receiver and its input intercept point.

FIGURE 1.30 Block diagram of a handheld cellular telephone transceiver. (Cou...

FIGURE 1.31 Dynamic load line of 2.4-GHz LP1500 pHEMT amplifier with

W.

FIGURE P1.2 Modern 6-GHz heterodyne receiver.

Chapter 2

FIGURE 2.1 Guide wavelength versus frequency with dielectric constant as a v...

FIGURE 2.2 Examples of (

a

) TEM, (

b

) quasi-TEM, (

c

) TE, and (

d

) TM modes (

i...

FIGURE 2.3 Equivalent circuit for a resistor.

FIGURE 2.4 Equivalent circuit model for chip capacitors.

FIGURE 2.5 (

a

) Effect of series resonance on

. (

b

) Series resonant frequenc...

FIGURE 2.6 Equivalent circuits for a chip inductor (

a

) and capacitor (

b

) wit...

FIGURE 2.7 Frequency response of typical chip inductors and capacitors versu...

FIGURE 2.8 Frequency response of surface-mount chip capacitor versus substra...

FIGURE 2.9 Lumped physical model of a spiral inductor on silicon.

FIGURE 2.10 Electromagnetic fields for a spiral inductor using patterned gro...

FIGURE 2.11 Transmission line discontinuities. (

a

) Step (

b

) T-junction (

c

) c...

FIGURE 2.12 Frequency response of helical coil.

Chapter 3

FIGURE 3.1 The large-signal microwave diode model. This model is temperature...

FIGURE 3.2 DC

–

curves for seven diodes, showing the various barrier volta...

FIGURE 3.3 Schottky diode chip cross-section.

FIGURE 3.4 Schottky diode band diagrams.

FIGURE 3.5 Forward DC characteristic curve range-voltage versus current.

FIGURE 3.6 Junction capacitance range versus voltage.

FIGURE 3.7 RF parameters versus local-oscillator drive level.

FIGURE 3.8 The linear diode model. This model is temperature-dependent.

FIGURE 3.9 The large-signal PIN diode model. This model is temperature-depen...

FIGURE 3.10 Simulated PIN diode resistance as a function of DC at 1, 10, and...

FIGURE 3.11 General outline of PIN diode construction.

FIGURE 3.12 Typical series resistance as a function of bias (1 GHz).

FIGURE 3.13 Voltage versus current for various PIN diodes.

FIGURE 3.14 Equivalent circuit of I region before punchthrough.

FIGURE 3.15 Typical 1-MHz capacitance.

FIGURE 3.16 Simplified equivalent circuit, series.

FIGURE 3.17 Reverse series resistance

.

FIGURE 3.18 Simplified equivalent circuit, shunt.

FIGURE 3.19 Reverse shunt resistance,

.

FIGURE 3.20 Insertion loss versus frequency.

FIGURE 3.21 Forward resistance versus forward current.

FIGURE 3.22 Second-order IMD in a PIN diode.

FIGURE 3.23 Cross-modulation in a PIN diode. Equation (3.60) relates cross-m...

FIGURE 3.24 (

a

) Basic PIN structure; (

b

) cross-section of a reverse-biased p...

FIGURE 3.25

–

abrupt-junction diode.

FIGURE 3.26 Capacitance versus total junction bias for abrupt-junction diode...

FIGURE 3.27

–

linearly graded junction.

FIGURE 3.28 Capacitance versus total junction bias for linearly graded junct...

FIGURE 3.29

–

hyperabrupt junction diode.

FIGURE 3.30 Typical

versus reverse voltage for hyperabrupt junction-diode....

FIGURE 3.31 Capacitance versus junction bias for hyperabrupt junction-diode....

FIGURE 3.32 Cross sections of planar (

a

) and mesa (

b

) devices.

FIGURE 3.33 Capacitance ratio versus breakdown voltage.

FIGURE 3.34 Temperature coefficient of capacitance versus tuning voltage–abr...

FIGURE 3.35 Temperature coefficient of capacitance versus tuning voltage (

...

FIGURE 3.36 Interfering signal (30% amplitude modulated) level versus bias f...

FIGURE 3.37 Signal level versus reverse voltage for 10% harmonic distortion....

FIGURE 3.38 Back-to-back diodes. CP is a fixed parallel capacitance, RB is a...

FIGURE 3.39 Capacitance/voltage characteristic for (a) an alloyed capacitanc...

FIGURE 3.40 Capacitance/voltage characteristic of the BA110 diode.

FIGURE 3.41 Basic current/voltage and capacitance/voltage characteristics.

FIGURE 3.42 Parallel-resonant circuit with tuner diode, and bias resistor pa...

FIGURE 3.43 Parallel-resonant circuit with tuner diode, and bias resistor pa...

FIGURE 3.44 Parallel-resonant circuit with two tuner diodes.

FIGURE 3.45 Diagram for determining the capacitance ratio and minimum capaci...

FIGURE 3.46 Capacitance increase as a function of the ac voltage drop across...

FIGURE 3.47 Current and voltage definitions for a npn bipolar transistor.

FIGURE 3.48 Ebers–Moll injection model of npn transistor.

FIGURE 3.49 Ebers–Moll transport model of npn transistor.

FIGURE 3.50 Ideal

–

curves of npn transistor.

FIGURE 3.51 Ideal large-signal BJT model in forward-active operation, with f...

FIGURE 3.52

–

curves showing forward early voltage VAF of npn transistor....

FIGURE 3.53 Ideal Gummel plot of npn transistor (

a

), and current gain obtain...

FIGURE 3.54 Thermal equivalent circuit.

FIGURE 3.55 Thermally coupled parallel transistors.

FIGURE 3.56 Small-signal equivalent circuit of GaAs HBT.

FIGURE 3.57 (

a

) Measured (symbols) and modeled by FBH-HBT model (lines)

-pa...

FIGURE 3.58 Schematic of InP DHBT structure. (

a

) The traditional mesa transi...

FIGURE 3.60 Focused ion beam cross-section of a transferred substrate DHBT (...

FIGURE 3.59 Photo (Courtesy Ferdinand-Braun-Institut).

FIGURE 3.61 Schematic of integrated module formed by a InP DHBT-chip bonded ...

FIGURE 3.62 Typical band diagram of a InGaP/GaAs HBT.

FIGURE 3.63 Gummel plot of

HBT (

a

) and of

InP DHBT (

b

) (Courtesy Ferdina...

FIGURE 3.64 Output

–

curves of

InGaP/GaAs HBT. (

a

)

and (

b

)

as a func...

FIGURE 3.65 Output

–

curves of

InP DHBT. (

a

)

and (

b

)

as a function o...

FIGURE 3.66 Transit frequency of (a) an InGaP/GaAs HBT, emitter size (b) an In...

FIGURE 3.67 Large-signal equivalent circuit of FBH HBT model.

FIGURE 3.68 (

a

) Base–collector capacitance

and (

b

) effective total transit...

FIGURE 3.69 The current-dependence of

yields a transcapacitance that can b...

FIGURE 3.70 Power-spectral measurement at 6 GHz (symbols) and simulation (li...

FIGURE 3.71 Schematic cross-section of a SiGe HBT (STI:

shallow trench isola

...

FIGURE 3.72 Typical band diagram of a SiGe HBT.

FIGURE 3.73 Typical doping profile and Ge content distribution of a SiGe HBT...

FIGURE 3.74 DC characteristics of a

SiGe HBT from the IHP technology. (

a

) ...

FIGURE 3.75 Published breakdown voltages BV

and BV

as a function of maximu...

FIGURE 3.76 SEM picture of a cross section of a 0.13 µm HBT from the IHP BiC...

FIGURE 3.77 Transit frequency

of a

HBT by IHP (Courtesy IHP Microelectro...

FIGURE 3.78 Schematic cross-section of a MESFET.

FIGURE 3.79 Interpretation of transcapacitances as capacitance using the exa...

FIGURE 3.80 Static and dynamic

–

curves of a

m GaAs power pHEMT. (Courtes...

FIGURE 3.81 Dispersion in GaN HEMTs: output

–

curves (

a

), transfer curve (

FIGURE 3.82 A subcircuit describing the effect of drain lag on the internal ...

FIGURE 3.83 Small-signal equivalent circuit of a FET.

FIGURE 3.84 (

a

) On-wafer measured (dashed lines) and modeled (solid lines)

FIGURE 3.85 Transfer characteristics of a FET,

as a function of

and its ...

FIGURE 3.86 Typical band diagram of a AlGaAs/GaAs HEMT.

FIGURE 3.87 Schematic cross-section of a monolithic integrated GaN-HEMT proc...

FIGURE 3.88 Photograph of a cross-section through a GaN-HEMT of 100 nm gate ...

FIGURE 3.89 Equivalent circuit of the Angelov (Chalmers) HEMT model.

FIGURE 3.90 (

a

) Typical enhancement-mode NMOS structure. (

b

) Enhancement-mod...

FIGURE 3.91 Idealized NMOS device cross-section with positive

applied, sho...

FIGURE 3.92 NMOS device with bias voltages applied.

FIGURE 3.93 NMOS device characteristics.

FIGURE 3.94 Small-signal MOS transistor equivalent circuit.

FIGURE 3.95 Typical measured electron drift velocity

versus tangent electr...

FIGURE 3.96 Model of velocity saturation of a MOSFET by addition of a series...

FIGURE 3.98 Cross-section of a Philips (Now NXP) LDMOS FET [3.55].

FIGURE 3.97 Cross-section of VMOS (

a

) and DMOS (

b

) FETs.

FIGURE 3.99 Photo of the underside of an LDMOS FET.

FIGURE 3.100 Representation of impact ionization in a MOSFET by a drain–subs...

FIGURE 3.102 Packaged high power GaN-HEMT for base station applications, bef...

FIGURE 3.103 Details of the em-simulated package variants. For the em simula...

FIGURE 3.104 Typical microwave noise properties of different transistor tech...

FIGURE 3.105 Output I–V curves of packaged Avago ATF34143 low-noise pseudomo...

FIGURE 3.106 Noise figure of packaged Avago ATF34143 low-noise pseudomorphic...

FIGURE 3.107 Associated gain of packaged Avago ATF34143 low-noise pseudomorp...

FIGURE 3.108 Output IP3 and

of packaged Avago ATF34143 low-noise pseudomor...

FIGURE 3.109 Typical

noise properties of different transistor technologies...

FIGURE 3.110 Phase noise of a 19-GHz InGaP/GaAs HBT MMIC oscillator as a fun...

FIGURE 3.111 Phase noise of a 19-GHz InGaP/GaAs HBT MMIC oscillator as a fun...

FIGURE 3.112 Sketch of an output

–

curve of a transistor (dotted lines), t...

FIGURE 3.113 Self-biasing of an HEMT device biased for low power dissipation...

FIGURE 3.114 Bias and output power of unit cell HBT (emitter area 3

30

m

)...

Chapter 4

FIGURE 4.1 (

a

) Amplifier and (

b

) oscillator diagrams.

FIGURE 4.2

versus

for CE BJT versus frequency.

FIGURE 4.3 Deembedding of pad capacitances. (

a

) The device to be measured is...

FIGURE 4.4 (

a

) Generic

- and (

b

) generic T-topology circuits.

FIGURE 4.5 Measured (solid line) and simulated (dashed line)

parameters of...

FIGURE 4.6 Equivalent circuit of spiral inductor.

FIGURE 4.7 Extraction of spiral inductor

and

. (

a

)

, (

b

) extraction of

FIGURE 4.8 Extraction of spiral inductor

for different frequency ranges.

FIGURE 4.9 Extraction of spiral inductor pad capacitance

(

a

,

b

) and parasi...

FIGURE 4.10 Resistive tee attenuator.

FIGURE 4.11

parameters from SPICE analysis.

FIGURE 4.12 Expressing an

parameter matrix (

a

) by a Mason graph (

b

).

FIGURE 4.13 (

a

) Series connection, (

b

) parallel connection of branches, and ...

FIGURE 4.14 Mason graph for mismatched source connected to (

a

) a matched loa...

FIGURE 4.15 Mason graph for a two-port connected to mismatched source and lo...

FIGURE 4.16 Stability circles at 2–4 GHz for Avago ATF34143 PHEMT. (

a

) Load ...

FIGURE 4.17 A 3-GHz amplifier using ATF34143 PHEMT (

a

) circuit schematic and...

FIGURE 4.18 Stability check for 3-GHz amplifier (

a

) simulation of transistor...

FIGURE 4.19 Cascaded two-ports.

FIGURE 4.20 Lange measurement setup for unilateral amplifier. (Modified from...

FIGURE 4.21 Power gains versus

.

FIGURE 4.22 Transistor with external reference node

. (Carson [4.13].)

FIGURE 4.23 Circuits used to establish properties of indefinite scattering m...

FIGURE 4.24 Three-port power divider.

FIGURE 4.25 Generator representation.

FIGURE 4.26 Concepts of differential drive and (

a

) common-mode output and (

b

FIGURE 4.27 Any signal applied to a composite port (

and

driven as a pair...

FIGURE 4.28 Four of the mixed-mode parameters for a balanced amplifier are s...

FIGURE 4.29 Characteristic impedance for bifilar magnet wire transmission li...

FIGURE 4.30 (

a

) LNAs and (

b

) HPAs.

FIGURE 4.31 Noise sources for a noise-free transistor.

FIGURE 4.32 Redrawn noise sources using

.

FIGURE 4.33 Input noise design for EG8021: (

a

) one-stage noise design and (

b

FIGURE 4.34 Three-stage lumped design.

FIGURE 4.35 Three-stage distributed design using linear CAD approach (

a

) sim...

FIGURE 4.36 ADS-simulated performance of three-stage lumped design.

FIGURE 4.37 Prediction of the three-stage distributed design using nonlinear...

FIGURE 4.38 BJT LNA at 4 GHz: (

) schematic; (

) performance.

Chapter 5

FIGURE 5.1a Smith charts. (

a

)

.

FIGURE 5.2 Lumped-element impedance match.

FIGURE 5.3 Distributed and hybrid impedance match.

FIGURE 5.4 Smith chart

plots.

FIGURE 5.5 Low-impedance broadband match.

FIGURE 5.6 Single-element matching (

a

) impedance transformation drawn into t...

FIGURE 5.7 Analysis of the 4 : 1 transformer.

FIGURE 5.8 (

a

) Physical two-wire transmission line transformer and (

b

) equiv...

FIGURE 5.9 Configuration of 9 : 1 transformer.

FIGURE 5.10 Simple balun transformer (

a

) dipole antenna, (

b

) feed line.

FIGURE 5.11 Push–pull amplifier using quarter-wave baluns.

FIGURE 5.12 Comparison of multisection

(a) quarter-wave matching, (b) tapere

...

FIGURE 5.13 Four matching circuit responses for taper design example (

a

) sch...

FIGURE 5.14 Multisection quarter-wave matching response for design example: ...

FIGURE 5.15 Broadband match to MESFET input (

a

) input matching of MESFET wit...

FIGURE 5.16 Broadband match to MESFET input with microstrip cross included (

Chapter 6

FIGURE 6.1 Butterworth passband response.

FIGURE 6.2 Butterworth stopband response.

FIGURE 6.3 Low-pass filter: (

a

) prototype; (

b

) dual prototype.

FIGURE 6.4 (

) Chebyshev passband response. (

) Chebyshev stopband response....

FIGURE 6.5 Lumped-element low-pass filter: (

a

) example circuit and (

b

) respo...

FIGURE 6.6 Lumped-element high-pass filter: (

a

) example circuit and (

b

) resp...

FIGURE 6.7 Lumped-element bandpass filter: (

a

) example circuit; (

b

) response...

FIGURE 6.8 Lumped-element bandpass filter: (

a

) example circuit and (

b

) respo...

FIGURE 6.9 Band-stop filter: (

a

) schematic and (

b

) response.

FIGURE 6.10 Transmission line element for

ABCD

parameter analysis.

FIGURE 6.11 (

a

) Short high-impedance transmission line. (

b

) Short low-impeda...

FIGURE 6.12 Semilumped low-pass filter: (

a

) example circuit and (

b

) response...

FIGURE 6.13 Circuits for Kuroda’s transform.

FIGURE 6.14 Stub bandpass filter: (

a

) schematic and (

b

) response.

FIGURE 6.15 Coupled-line bandpass filter: (

a

) example circuit and (

b

) respon...

FIGURE 6.16 FBAR basics.

FIGURE 6.17 Size comparison of FBAR filters. (George D. Vendelin).

FIGURE 6.18 FBAR performance.

FIGURE 6.19 Performance of 1.88 GHz FBAR filter.

Chapter 7

FIGURE 7.1 Combination of signal and noise voltages supplied to a complex te...

FIGURE 7.2 Graphical and mathematical explanation of the noise bandwidth fro...

FIGURE 7.3 Test setup to measure signal-to-noise ratio.

FIGURE 7.4 General form of noise two-port: (

a

) noisy two-port; (

b

) noiseless...

FIGURE 7.5 Parallel combination of two-ports using

parameters.

FIGURE 7.6 Noise transformation using the [

ABCD

] matrix.

FIGURE 7.7 Generator current with noise sources.

FIGURE 7.8 (

a

) Series element for the calculation of noise parameters. (

b

) S...

FIGURE 7.9 Two-port [

ABCD

] parameter representation of a noise-free system....

FIGURE 7.10 Two-port [

ABCD

] parameter representation with noise source conne...

FIGURE 7.11 Noise source transformed to the input.

FIGURE 7.12 (

a

) CE configuration of noise-free transistor. (

b

) CE configurat...

FIGURE 7.13 (

a

) CC configuration. (

b

) CC with input noise sources. (

c

) CC no...

FIGURE 7.14 (

a

) CB configuration. (

b

) CB with input noise sources. (

c

) Orien...

FIGURE 7.15 Noisy linear two-ports: (

a

) general form; (

b

) admittance form; (

FIGURE 7.16 Chain matrix form of linear noisy two-port.

FIGURE 7.17

-parameter form of linear noisy two-ports (

a

) noise waves defin...

FIGURE 7.18 Cascaded noisy two-ports with noise figures

and

and gain fig...

FIGURE 7.19 Equivalent circuit of the transistor package.

FIGURE 7.20 Noise parameters versus feedback for AT-41435 silicon bipolar tr...

FIGURE 7.21 Typical noise figure circles and gain circles.

FIGURE 7.22 Parallel combination of two-ports using

parameters.

FIGURE 7.23 Noise figure measurement.

FIGURE 7.24 Single-sideband noise figure measurement using an external mixer...

FIGURE 7.25 Upconversion of low-frequency noise in a nonlinear circuit (

a

) n...

FIGURE 7.26 Implementing a cyclostationary noise source.

FIGURE 7.27 Noise parameters of 3

30 µm

2

HBT from wafers A, B, and C at

1 ...

FIGURE 7.28 Shot-noise models for the intrinsic HBT. Topologies of (

a

) corre...

FIGURE 7.29 Noise parameters of 3

30 µm

2

HBT at

V,

mA. (

): measurement,...

FIGURE 7.30 Intrinsic small-signal HBT equivalent circuit including intrinsi...

FIGURE 7.31 Equivalent circuit of the HBT including extrinsic elements, deco...

FIGURE 7.32 Simplified HBT equivalent circuit including white and flicker no...

FIGURE 7.33 Flicker noise of InGaP/GaAs HBTs. Short-circuit noise-current sp...

FIGURE 7.34 Measured and simulated residual phase noise of

µm

2

HBT with av...

FIGURE 7.35 Intrinsic noise model of the GaN FET according to Pucel.

FIGURE 7.36 Intrinsic noise model of the GaN FET according to Pospieszalski....

FIGURE 7.37 Pucel model parameters

and

as a function of bias for a 0.25 ...

FIGURE 7.38 Pucel model parameter

as a function of bias for a 0.25 µm HEMT...

FIGURE 7.39

(a)–(d)

The four noise parameters of a 0.25 µm HEMT device...

FIGURE 7.40 Measured

of a

µm GaN HEMT at

V,

50 mA. Noise was measured...

Chapter 8

FIGURE 8.1 A dc bias circuit for BJT/HBT: (

a

) four-resistor network; (

b

) act...

FIGURE 8.2 Bias circuits for MESFET/PHEMT: (

a

) simple circuit; (

b

) active bi...

FIGURE 8.3 Cascade circuit of two-ports

and

.

FIGURE 8.4 Typical

amplifier.

FIGURE 8.5 (

a

)RF schematic of circuit A. (

b

) RF schematic of circuit B. (

c

) ...

FIGURE 8.6 Unilateral amplifier using a variable coupler and a variable line...

FIGURE 8.7 RF schematic of circuit D.

FIGURE 8.8 RF schematic of circuit E.

FIGURE 8.9 Low-VSWR amplifiers: (

a

) balanced amplifier using 3-dB Lange coup...

FIGURE 8.10 Analysis of 3-dB directional coupler.

FIGURE 8.11 Large-signal distortion of MWT-17 MESFET. (

a

) Amplitude. (

b

) Pha...

FIGURE 8.12 MODAMP schematic (MSA 07).

FIGURE 8.13 Feedback circuits. (

a

) Shunt feedback. (

b

) Series feedback.

FIGURE 8.14 A 1- to 5-GHz cascode amplifier: (

a

) schematic; (

b

) gain; (

c

) no...

FIGURE 8.15 A 1- to 8-GHz cascode amplifier: (

a

) schematic; (

b

) gain; (

c

) no...

FIGURE 8.16 Bipolar cascode dc bias schematic.

FIGURE 8.17 A 1- to 8-GHz cascode amplifier including temperature effects. (

FIGURE 8.18 Interstage designs (assuming

): (

a

) high-gain interstage; (

b

) l...

FIGURE 8.19 Smith chart impedance of lumped-element transmission lines versu...

FIGURE 8.20 Distributed matrix amplifiers. (

a

) Distributed and (

b

) matrix am...

FIGURE 8.21 Three types of three-stage amplifiers. (

a

) Cascaded amplifier, (

FIGURE 8.22 Frequency multiplier.

FIGURE 8.23 Series diode: classical passive multiplier realizations.

FIGURE 8.24 Shunt diode: classical passive multiplier realizations.

FIGURE 8.25 Active device model.

FIGURE 8.26 Active multiplier realization.

FIGURE 8.27 Photo of frequency doubler. (George D. Vendelin.)

FIGURE 8.28 Doubler-conversion gain (

dBm,

V, and

V).

FIGURE 8.29 A 1.9-GHz PCS amplifier.

FIGURE 8.30 Performance of1.9-GHz amplifier. (

a

) noise figure, (

b

) gain, (

c

)...

FIGURE 8.31 Negative-feedback amplifier.

FIGURE 8.32 Gain and phase margins from Bode plot.

FIGURE 8.33 Nyquist plot.

Chapter 9

FIGURE 9.1 Current and voltage at the transistor (

a

) Class-A, (

b

) Class-AB, ...

FIGURE 9.2 Vectorial load- and source-pull measurement setup.

FIGURE 9.3 Measured load-pull contours for output power (blue curves) and PA...

FIGURE 9.4 Measured output powers of a GaN HEMT at 8 GHz for different load ...

FIGURE 9.5 Idealized loadline to estimate output powers for optimum load res...

FIGURE 9.6 Idealized contour of constant output power (

a

). The contours get ...

FIGURE 9.7 Nonlinear power output performance of typical FET: (

a

) constant-p...

FIGURE 9.8 Lumped-element bandpass output network.

FIGURE 9.9 Distributed bandpass output network with harmonic terminations.

FIGURE 9.10 Desired load impedance as a function of frequency.

FIGURE 9.11 Calculated small-signal gain performance of single-stage amplifi...

FIGURE 9.12 Representative two-stage amplifier. (Courtesy of Texas Instrumen...

FIGURE 9.13 (

–

) Typical amplitude equalization networks. (

) Respective fr...

FIGURE 9.14 Optimum load impedance (actual and target) presented to output F...

FIGURE 9.15 (

) Lumped-element and (

) distributed-element output network eq...

FIGURE 9.16 (

) Lumped-element and (

) distributed-element interstage networ...

FIGURE 9.17 Final distributed-element amplifier circuit model.

FIGURE 9.18 Monolithic two-stage 6- to 18-GHz amplifier.

FIGURE 9.19 Measured gain and power output performance of monolithic two-sta...

FIGURE 9.20 Multistage amplifier examples: (

) three-stage LDMOS MMIC 40-W a...

FIGURE 9.21 Schematic representation of a FET distributed amplifier. (From R...

FIGURE 9.22 Simplified FET model.

FIGURE 9.23 Constant-

lumped-element transmission lines: (

) input circuit ...

FIGURE 9.24 (

) Attenuation on gate line versus normalized frequency. (

) At...

FIGURE 9.25 Normalized frequency response on

FET distributed amplifier for...

FIGURE 9.26 Representative values of

and

that yield the same fractional ...

FIGURE 9.27 Maximum gate line RF voltage swing.

FIGURE 9.28 Optimum ac load impedance for class A operation.

FIGURE 9.29 Current distribution in a correctly tapered drain circuit.

FIGURE 9.30 Current combining for a four-cell distributed amplifier.

FIGURE 9.31 Simplified single-gate equivalent model of dual-gate FET.

FIGURE 9.32 Transmission line model of dual-gate distributed power amplifier...

FIGURE 9.33 Monolithic dual-gate FET distributed power amplifier. (Courtesy ...

FIGURE 9.34 Measured gain and power output performance of monolithic distrib...

FIGURE 9.35 Measured versus predicted (Microwave SPICE) power output perform...

FIGURE 9.36 LTCC PHEMT low-voltage distributed power amplifier. (Courtesy of...

FIGURE 9.37 Low-voltage LTCC distributed amplifier performance: (

) amplifie...

FIGURE 9.38 LTCC 3.3- to 50-

transformer: (

) layer configuration for multi...

FIGURE 9.39 Comparison of class A, B, and C operation: (

a

) current wavefor...

FIGURE 9.40 Generic class A to C circuit.

FIGURE 9.41 Definition of conduction angle

.

FIGURE 9.42 Function values for the fundamental, to fourth harmonic (

,

,

FIGURE 9.43 Values for the DC and fundamental frequency power, and resulting...

FIGURE 9.44 A 200-W push-pull amplifier device: (

a

) four 80-mm die and input...

FIGURE 9.45 Pulsed CW output power versus input power for 200-W push-pull de...

FIGURE 9.46 Two-carrier WCDMA ACPR, IM3, power gain, and drain efficiency ve...

FIGURE 9.47 Typical class AB push-pull power amplifier employing BJTs. (Cour...

FIGURE 9.48 Simplified class-F amplifier.

FIGURE 9.49 Class-F harmonic tuning circuits taking the transistor output ca...

FIGURE 9.50 Output power and PAE as a function of the phase of the second ha...

FIGURE 9.51 Loadline and voltage and current waveforms of a 10-finger HBT at...

FIGURE 9.52 Loadline and voltage and current waveforms of a 10-finger HBT at...

FIGURE 9.53 Class D amplifier: (

a

) ideal circuit; (

b

) ideal switching model....

FIGURE 9.54 Circuit schematic of a first-order class-E amplifier. The curren...

FIGURE 9.55 Currents and voltages of the class-E amplifier shown in Figure 9...

FIGURE 9.56 Loadlines of a class-B amplifier.

FIGURE 9.57 Doherty amplifier.

FIGURE 9.58 Amplitudes of (

a

) output voltage and (

b

) output current, and (

c

)...

FIGURE 9.59 Circuit diagram of Cireix outphasing amplifiers. (

a

) Original ci...

FIGURE 9.60 Ideal efficiency of an outphasing transmitter relative to the pe...

FIGURE 9.61 Schematic of the Kahn EER transmitter.

FIGURE 9.62 (

a

) Comparison of a band-limited white noise signal spectrum com...

FIGURE 9.63 Vector diagrams of band-limited complex noise (I and Q channel n...

FIGURE 9.64 (

a

) Impact of band limitation in the amplitude path at the examp...

FIGURE 9.65 Envelope tracking supply modulated power amplifier.

FIGURE 9.66 Comparison of the drain efficiency of a class A (

a

) and a class ...

FIGURE 9.67 Time domain envelope tracking signals and qualitative power diss...

FIGURE 9.68 Comparison of the normalized power spectral density (without DC ...

FIGURE 9.69 Time domain envelope and discretized supply voltage waveforms fo...

FIGURE 9.70 Transducer power gain (

) for different supply voltage levels, a...

FIGURE 9.71 AM/AM and AM/PM distortion for a three-level class-G supply modu...

FIGURE 9.72 The digital transmitter architecture.

FIGURE 9.73 Output voltage and current waveform of an ideal switch driven wi...

FIGURE 9.74

output characteristic of an ideal switch compared to a class-A...

FIGURE 9.75 Digital power amplifier in voltage-mode final-stage topology (

,...

FIGURE 9.76 Voltage and current waveform at output of digital PA (before fil...

FIGURE 9.77 Lumped element output network for a voltage-mode class-D/S power...

FIGURE 9.78 Digital power amplifier in current-mode final-stage topology (

,...

FIGURE 9.79 Current flow (arrow indication) in a current-mode digital power ...

FIGURE 9.80 Current and voltage waveform in a current-mode digital power amp...

FIGURE 9.81 Current-mode final-stage configuration for odd-mode operation in...

FIGURE 9.82 Current-mode final-stage configuration for even-mode operation i...

FIGURE 9.83 Equivalent circuit of current-mode final-stage topology includin...

FIGURE 9.84 Required output network configuration for a current-mode class-D...

FIGURE 9.86 Cascode push–pull feedback amplifier model.

Chapter 10

FIGURE 10.1 Two-port connected to a generator.

FIGURE 10.2 Compressed Smith chart.

FIGURE 10.3 Oscillator equivalent circuits: (

) series resonant and (

) para...

FIGURE 10.4 Coupling between a microstrip line and a dielectric resonator.

FIGURE 10.5 Equivalent circuit of the dielectric resonator coupled with a mi...

FIGURE 10.6 (a) Simplified equivalent circuit; (b) final equivalent circuit ...

FIGURE 10.7 Recommended methods of frequency stabilization for dielectric re...

FIGURE 10.8 DRO on microstrip as (a) band-stop filter and (b) bandpass filte...

FIGURE 10.9 Typical circuit for a dielectric resonator-based oscillator at a...

FIGURE 10.10 Predicted phase noise of DRO shown Figure 10.9. Note the bend i...

FIGURE 10.11 YIG sphere serves as the resonator in the sweep oscillators use...

FIGURE 10.12 Circuit diagram for YIG-tuned oscillator. depicted in Figure 10...

FIGURE 10.13 Schematic for a 10-GHz YIG oscillator using the YIG model in Se...

FIGURE 10.14 Predicted phase noise at 10 GHz for oscillator shown in Figure ...

FIGURE 10.15 Phase noise comparison of different YIG and varactor-tuned os...

FIGURE 10.16 Phase noise at 10 kHz off the carrier of silicon bipolar transi...

FIGURE 10.17 Dynamic capacitance and dynamic resistance as a function of tun...

FIGURE 10.18 Varactor parameters: capacitance, equivalent resistance, and

,...

FIGURE 10.19 Standard round/square packaging.

FIGURE 10.20 Schematic of ceramic. resonator-based oscillator

FIGURE 10.21 Simulated phase noise of an npn bipolar 1-GHz ceramic resonator...

FIGURE 10.22 Measured phase noise of a ceramic resonator-based oscillator.

FIGURE 10.23 Series capacitive coupled resonator.

FIGURE 10.24a Schematic of the parallel coupled resonator-based oscillator....

FIGURE 10.24b NE68830 with package parasitics (

is the intrinsic bipolar tr...

FIGURE 10.24c Simulated response of real and imaginary currents for oscillat...

FIGURE 10.24d Simulated phase noise plot for the single resonator (1-resonat...

FIGURE 10.24e Measured phase noise plot for the single resonator (1-resonato...

FIGURE 10.25 Small-signal model of the grounded base oscillator.

FIGURE 10.26 Relative phase noise versus the ratio of loaded to unloaded

o...

FIGURE 10.28 Input impedance of a resonant cavity referred to the detuned-sh...

FIGURE 10.29 Identification of the half-power points from the Smith chart:

FIGURE 10.30 Buffered oscillator design.

FIGURE 10.31 Oscillator example at 2 GHz.

FIGURE 10.35 (a) Schematic of a Clapp–Gouriet-based

lumped-resonator oscilla

...

FIGURE 10.36 Transmission line oscillator with dielectric resonator.

FIGURE 10.37 Equivalent circuit for dielectric resonator oscillator (DRO).

FIGURE 10.38 Feedback oscillator using MSA 0835.

FIGURE 10.39 Equivalent circuit for DRO using MSA 0835.

FIGURE 10.40 Feedback amplifier.

FIGURE 10.41 Two oscillator circuits.

FIGURE 10.42 Feedback oscillator using capacitive voltage divider; Colpitts ...

FIGURE 10.43 Feedback oscillator using inductive voltage divider; Hartley os...

FIGURE 10.44 Feedback oscillator using mutual coupling; Armstrong oscillator...

FIGURE 10.45 Feedback oscillator using series resonant circuit; Clapp–Gourie...

FIGURE 10.46 Negative input impedance generated by capacitive feedback.

FIGURE 10.47 VCO using capacitive feedback.

FIGURE 10.48 Practical valued for VCO at 7.5 GHz.

FIGURE 10.49 BJT-based oscillator with noise feedback. The noise sampling is...

FIGURE 10.50 Phase noise improvement caused by the feedback circuit, includi...

FIGURE 10.52 Noise power versus frequency of a transistor amplifier with an ...

FIGURE 10.53 Phase noise added to carrier.

FIGURE 10.54 Phase noise modeled by a noise-free amplifier and a phase modul...

FIGURE 10.55 Equivalent feedback models of oscillator phase noise.

FIGURE 10.56 Oscillator phase noise for high-

and low-

resonator viewed as...

FIGURE 10.57 Survey of published high-frequency oscillator using different t...

FIGURE 10.58 Bias-dependent transition frequency

measured at 2 GHz by moni...

FIGURE 10.59 PM to FM noise conversion in a 4-GHz oscillator.

FIGURE 10.60 Transistor oscillators are sensitive to the bias network and to...

FIGURE 10.61a Predicted phase noise of an 880-MHz oscillator (

not

a VCO) as ...

FIGURE 10.61b Predicted phase noise of an 880-MHz oscillator (

not

a VCO) wit...

FIGURE 10.62 Predicted phase noise of an 880-MHz VCO with tuning sensitivity...

FIGURE 10.63 Comparison of noise sideband performance of a crystal oscillato...

FIGURE 10.64 Single-sideband phase noise for a 4-GHz oscillator using elemen...

FIGURE 10.65 Single-sideband phase noise for a 4-GHz oscillator with a bipol...

FIGURE 10.66 Circuit of a 4-GHz oscillator using Table 10.6.

FIGURE 10.68 A 4–6-GHz cavity-tuned oscillator. (George D. Vendelin.)

FIGURE 10.69 Close-up of Figure 10.68. (George D. Vendelin.)

FIGURE 10.70 Optimum embedding elements for six oscillator structures: (

) t...

FIGURE 10.71 Six oscillator structures at 10 GHz for DXL-3501A GaAs MESFET: ...

FIGURE 10.72 Shunt oscillator topology. The device is represented by large-s...

FIGURE 10.73 Generalized oscillator circuit for the design example given.

FIGURE 10.74 Measured gain–saturation characteristics of the FET chip. (From...

FIGURE 10.75 Optimized oscillator circuit for the topology chosen. (From Gil...

FIGURE 10.76 Photograph of 5.350-GHz oscillator. (From Ref. [10.9]

IEEE 198...

FIGURE 10.77 Oscillator efficiency and output power. (From Gilmore and Rosen...

FIGURE 10.78 Oscillator frequency-pushing characteristics. (From Gilmore and...

FIGURE 10.79 Oscillator frequency–temperature variation. (From Gilmore and R...

FIGURE 10.80 Oscillator FM noise. (From Gilmore and Rosenbaum [10.9]

IEEE 1...

FIGURE 10.81 Oscillator characteristics in self-bias operation. (From Gilmor...

FIGURE 10.82 Oscillator frequency and gate bias in self-bias operation. (Fro...

FIGURE 10.83 Capacitance versus junction bias for a hyperabrupt diode.

FIGURE 10.84 The large-signal microwave diode model. This model is temperatu...

FIGURE 10.85 Schematic of oscillator circuit and equivalent circuit of FET u...

FIGURE 10.86 (

) Measured and (

) simulated

–

characteristic used in nonli...

FIGURE 10.87 Equivalent circuit of FET based on measured

parameters. (From...

FIGURE 10.88 Comparison of measured

parameters and calculated

parameters...

FIGURE 10.89 Domains of load admittance (shaded areas) that support oscillat...

FIGURE 10.90 Calculated constant-frequency and constant-power output contour...

FIGURE 10.91 DRO design example. (Rizzoli et al. [10.38].)

FIGURE 10.92 Oscillator performance versus

. (Rizzoli et al [10.38].)

FIGURE 10.93 Oscillator performance versus tuning plate distance. (Rizzoli e...

FIGURE 10.94 Varactor-tuned DRO. (Rizzoli et al [10.38].)

FIGURE 10.95 Oscillator performance versus varactor tuning voltage. (Rizzoli...

FIGURE 10.96 Large-signal FET model. (From Bandler et al. [10.42]

IEEE 1988...

FIGURE 10.97

-parameter match using simultaneous AC and DC parameter extrac...

FIGURE 10.98

-parameter match using conventional parameter extraction. (Mod...

FIGURE 10.99 Amplifier design at 4 GHz. (From Gilmore et al. [10.37])

FIGURE 10.100 Amplifier load line with

dBm at 4 GHz. (From Gilmore et al. ...

FIGURE 10.101 Oscillator design at 4 GHz. (From Gilmore et al. [10.37]

IEEE...

FIGURE 10.102 Oscillator power output spectrum. (From Gilmore et al. [10.37]

FIGURE 10.103 Oscillator drain current versus time (two cycles). From Gilmor...

FIGURE 10.104 Oscillator load line. From Gilmore et al. [10.37]

IEEE 1988....

FIGURE 10.105 Buffered oscillator design. (From Gilmore et al. [10.37]

IEEE...

FIGURE 10.106 Buffered oscillator load voltage versus time (two cycles). (Fr...

FIGURE 10.107 Buffered oscillator power output spectrum. (From Gilmore et al...

FIGURE 10.108 Gate current for amplifier FET versus time. (From Gilmore et a...

FIGURE 10.109 Survey of narrow-band FET oscillator performance. (From Pucel ...

FIGURE 10.110 Wide-band tuning of an FET oscillator. (From Pucel [10.46].)

FIGURE 10.111 Survey of wide-band FET oscillator performance. (From Pucel [1...

FIGURE 10.112 Survey of FET oscillator noise performance. (From Pucel [10.46...

FIGURE 10.113 Methods of frequency stabilization. (From Pucel [10.46].)

FIGURE 10.114 Circuit for noise degeneration in FET oscillators. (From Galan...

FIGURE 10.115 Noise performance of an FET oscillator with and without noise ...

FIGURE 10.116 Photograph of an ultrafast dielectric resonator oscillator. (C...

FIGURE 10.117 A 3000-MHz oscillator using a BFP520 transistor operating at 2...

FIGURE 10.118 Real and imaginary currents for oscillation. The reactive curr...

FIGURE 10.119 The 1000-MHz oscillator used in the design example.

FIGURE 10.120 Base voltage and collector current of the oscillator in Figure...

FIGURE 10.121 Predicted phase noise of the circuit shown in Figure 10.119 wi...

FIGURE 10.122 Schematic of the oscillator.

FIGURE 10.123 Predicted output power of the oscillator.

FIGURE 10.124 Predicted phase noise of the oscillator.

FIGURE 10.125 Output oscillator circuit configuration showing the current di...

FIGURE 10.126 NE68830 with package parasitics;

is the intrinsic bipolar tr...

FIGURE 10.127 Phase noise contribution of lossy resonator at 10 kHz offset....

FIGURE 10.128 Phase noise contribution due to the base resistance at 10 kHz ...

FIGURE 10.129 Phase noise contribution due to base current and flicker noise...

FIGURE 10.130 Phase noise contribution due to the collector current at 10 kH...

FIGURE 10.131 Total effect of all four-noise sources at 10 kHz offset.

FIGURE 10.132 Design of 350 MHz Colpitts oscillator-optimized for phase nois...

FIGURE 10.133a Oscillator circuit with the passive components

,

, and

.

FIGURE 10.134 Example for the single sideband phase noise as a function of t...

FIGURE 10.135 Shows

as a function of drive level.

.

FIGURE 10.136 Optimization of phase noise for the series tuned circuit.

FIGURE 10.137 Mathcad calculation for phase noise.

FIGURE 10.138 Measured phase noise result for 350 MHz oscillator.

FIGURE 10.139a Simulated phase noise for the 350 MHz parallel tuned Colpitts...

FIGURE 10.140 Showing

large signal condition.

FIGURE 10.141

– to calculate the drive level.

FIGURE 10.142 Optimized phase noise for different values of Inductor

.

FIGURE 10.143 Results of series and parallel tuned circuits for same value o...

FIGURE 10.144 Results of series and parallel tuned circuits for higher value...

FIGURE 10.145 Effect of

factor on phase noise.

FIGURE 10.146 Effect of

factor on phase noise.

FIGURE 10.147 Circuit of the 2400 MHz integrated CMOS oscillator.

FIGURE 10.148 The real and imaginary currents which cause the negative resis...

FIGURE 10.149 Predicted phase noise of the 2400 MHz MOSFET oscillator.

FIGURE 10.150 Predicted output spectmm of the 2400 MOSFET oscillator.

FIGURE 10.151 Determining the transconductance of the differential circuit o...

FIGURE 10.152

The equivalent cross-coupled oscillator resonator circuit an...

FIGURE 10.153 The predicted output spectrum of the CMOS oscillator.

FIGURE 10.154 The predicted phase noise from Ansoft Designer.

FIGURE 10.155 Shows a general noisy nonlinear network.

FIGURE 10.156 Oscillator noise components.

FIGURE 10.157 Direct spectrum measurement technique.

FIGURE 10.158 Basic block diagram of frequency discriminator method (Courtes...

FIGURE 10.159 The ideal phase detector sensitivity in terms of RF power (ass...

FIGURE 10.160 Basic block diagram of heterodyne (digital) discriminator meth...

FIGURE 10.161 Basic concept of Phase detector techniques.

FIGURE 10.162 Shows the basic block diagram Phase Detector Method using refe...

FIGURE 10.163 Shows the response of

as a phase detector varies as

, (V

IF

)...

FIGURE 10.164 Additive noise method set-up (simplified single channel additi...

FIGURE 10.165 Automatic system to measure residual phase noise of two 8662A ...

FIGURE 10.166 Shows the basic block diagram of two-channel cross-correlation...

FIGURE 10.167 Phase noise of the internal local oscillator of the R&S FSWP a...

FIGURE 10.168 Phase noise system with two sources maintaining phase quadratu...

FIGURE 10.169 Shows phase noise plots and noise floor for three-techniques (...

FIGURE 10.170 Synergy Model LNXO0120-014. (RF-Lambda.)

FIGURE 10.171 Overall block diagram of the phase noise analyzer.

FIGURE 10.172 Model of the

mixer impairments and the resulting spectrum.

FIGURE 10.173 Digital signal processing for one receive path.

FIGURE 10.174 AM and FM demodulation of an ideal CW source.

FIGURE 10.175 Pulsed source in time and frequency domains.

FIGURE 10.176 FFT and cross-correlation.

FIGURE 10.177 Typical noise floor with a measurement time of 10 seconds and ...

FIGURE 10.178 Two-minute phase noise measurement of a Wenzel 100 MHz-SC Gold...

FIGURE 10.179 DRO 10.24 GHz-showing AM and FM noise. (RF-Lambda.)

FIGURE 10.180 SPREF Reference –

and

noise 12 GHz. (RF-Lambda.)

FIGURE 10.181 Keysight – Signal generator. (RF-Lambda.)

FIGURE 10.182 Active bias network for a common-emitter RF amplifier stage.

FIGURE 10.183 A 1000-MHz ceramic resonator oscillator.

FIGURE 10.184 Plot of real and imaginary oscillator currents as a function o...

FIGURE 10.185 Measured phase noise of the 1000-MHz ceramic resonator oscilla...

FIGURE 10.186 Predicted phase noise of the CRO at 1 GHz shown in Figure 10.1...

FIGURE 10.187 Photograph of the 1-GHz CRO of the schematic shown in Figure 1...

FIGURE 10.188 Circuit diagram of the 4.1-GHz oscillator.

FIGURE 10.189 Predicted phase noise of the 4.1-GHz oscillator.

FIGURE 10.190 Printed circuit board of the 4.1-GHz oscillator shown in Figur...

FIGURE 10.191 Measured phase noise of the 4.1-GHz oscillator.

FIGURE 10.192 Circuit diagram of the 2-GHz GaAs FET oscillator.

FIGURE 10.193 Predicted phase noise of the oscillator shown in Figure 10.192...

FIGURE 10.194 The DC

–

and the load line for the GaAs FET oscillator.

FIGURE 10.195 Layout of the 2-GHz GaAs FET oscillator.

FIGURE 10.196 Series feedback topology.

FIGURE 10.197 Parallel feedback topology.

FIGURE 10.198 Series feedback topology of the oscillator using bipolar trans...

FIGURE 10.199 Parallel feedback topology of the oscillator using a bipolar t...

FIGURE 10.200 A 950-MHz MESFET oscillator circuit configuration.

FIGURE 10.201 Equivalent circuit of the open model MESFET oscillator.

FIGURE 10.202 A simplified open loop model of the oscillator.

FIGURE 10.203 Circuit model of an oscillator.

FIGURE 10.204 Schematic diagram of the oscillator operating at 950 MHz.

FIGURE 10.205 Schematic of the test oscillator.

FIGURE 10.206 Load line of the oscillator shown in Figure 10.205. Because th...

FIGURE 10.207 Plot of drain current and drain source voltage as a function o...

FIGURE 10.208 The AC drain current simulated for Figure 10.205.

FIGURE 10.209 Simulated noise figure of the circuit shown in Figure 10.205. ...

FIGURE 10.210 Simulated output power of the oscillator shown in Figure 10.20...

FIGURE 10.211 Schematic of the self-oscillating mixer.

FIGURE 10.212 Load line in the oscillator mode of the self-oscillating mixer...

FIGURE 10.213 RF power of the self-oscillating mixer.

FIGURE 10.214 Predicted phase noise of the self-oscillating mixer.

FIGURE 10.215 Test fixture to measure large signal

-parameters. (Synergy Mi...

FIGURE 10.216 Rohde & Schwarz 3 GHz network analyzer to measure the large-si...

FIGURE 10.217 Measured large-signal

of the Infineon BFP520.

FIGURE 10.218 Measured large-signal

of the Infineon BFP520.

FIGURE 10.219 Measured large-signal

of the Infineon BFP520.

FIGURE 10.220 Measured large-signal

of the Infineon BFP520.

FIGURE 10.221 Colpitts oscillator analyzed by Kaertner.

FIGURE 10.222 Circuit schematic of the Kaertner 300 MHz oscillator.

FIGURE 10.223 Simulated phase noise of the Kaertner oscillator (Figure 10.22...

FIGURE 10.224 Simulated output power of the Kaertner circuit.

FIGURE 10.225 Close-In phase-noise behavior due to white noise sources. Lees...

FIGURE 10.226 Conversion process from noise (Sn(

)) to phase-noise (L(

)). N...

FIGURE 10.227 Measurement of a 40 GHz source where the spot noise is larger ...

FIGURE 10.228 Indication of the range of validity of phase noise measurement...

Chapter 11

FIGURE 11.1 Block diagram of an integrated frequency synthesizer. In this ca...

FIGURE 11.2 Abbreviated circuit of a 10-MHz crystal oscillator

FIGURE 11.3 Simulated phase noise plot of 10 MHz crystal oscillator.

FIGURE 11.4 Measured phase noise for this frequency standard by HP.

FIGURE 11.5 System using dual-modulus counter arrangement.

FIGURE 11.6 Block diagram of a linearized model of a PLL.

FIGURE 11.7 Edge-triggered JK master-slave flip-flop.

FIGURE 11.8 Performance of the JK phase/frequency comparator for different i...

FIGURE 11.9 Phase detector output for two input frequencies that are substan...

FIGURE 11.10 Performance of the phase detector for small frequency errors.

FIGURE 11.11 Block diagram of CD4046 phase/frequency comparator. (Courtesy o...

FIGURE 11.12 Schematic diagram of a typical passive RC filter.

FIGURE 11.13 Schematic diagram of an active filter for a second-order loop....

FIGURE 11.14 Schematic diagram of an active filter for a third-order loop.

FIGURE 11.15 External charge pump current source.

FIGURE 11.16 Schematic of the second-order loop filter.

FIGURE 11.17 Third-order loop filter for greater reference-energy suppressio...

FIGURE 11.18 Measured phase noise of an 880-MHz synthesizer using a conventi...

FIGURE 11.19 Block diagram of a digital PLL before lock is acquired.

FIGURE 11.20 Block diagram of a PLL synthesizer driven by a frequency standa...

FIGURE 11.21 Normalized output response of a Type 2, second-order loop with ...

FIGURE 11.22 Loop filter for a Type 1, second-order synthesizer.

FIGURE 11.23 Type 1, second-order loop response.

FIGURE 11.24 Loop filter for a Type 2, second-order synthesizer.

FIGURE 11.25 Response of the Type 2, second-order loop.

FIGURE 11.26 Lock-in function of the Type 2, second-order PLL. It indicates ...

FIGURE 11.27 Example of settling-time measurement.

FIGURE 11.28 Loop filter for a Type 2, third-order synthesizer.

FIGURE 11.29 Open-loop Bode diagram for the Type 2, third-order loop. It ful...

FIGURE 11.30 Lock-in function of the Type 2, third-order loop for an ideal 4...

FIGURE 11.31 Bode plot of the fifth-order PLL system for a microwave synthes...

FIGURE 11.32 Lock-in function of the fifth-order PLL. Note that the phase lo...

FIGURE 11.33 Lock-in function of the fifth-order PLL. Note that the phase ma...

FIGURE 11.34 Lock-in function of another Type 2, fifth-order loop with a 25°...

FIGURE 11.35 Lock-in function of the Type 2, fifth-order loop with a 35° pha...

FIGURE 11.36 Lock-in function of the Type 2, third-order loop with an ideal ...

FIGURE 11.37 Lock-in function of the Type 2, fifth-order loop, for a 55° pha...

FIGURE 11.38 Comparison between open- and closed-loop noise prediction. Note...

FIGURE 11.39 Comparison between open- and closed-loop noise prediction. Note...

FIGURE 11.40 Type 1 high-order loop filter used for passive filter evaluatio...

FIGURE 11.41 A Type 2 high-order filter with a notch to suppress the discret...

FIGURE 11.42 Phase/frequency discriminator including an active loop filter c...

FIGURE 11.43 The filter frequency response/phase noise analysis graph shows ...

FIGURE 11.44 Block diagram of the fractional-

N

synthesizer built using a cus...

FIGURE 11.45 Detailed block diagram of the inner workings of the fractional-

FIGURE 11.46 Composite phase noise of the fractional-

N

synthesizer system, i...

FIGURE 11.47 Direct digital frequency synthesizer.

FIGURE 11.48 Signals generated by a DDS: (

a

) accumulator’s output, (

b

) DAC o...

FIGURE 11.49 Spectrum of the DAC output.

FIGURE 11.50 A multiple loop synthesizer using a DDS for fine resolution.

Chapter 12

FIGURE 12.1 A typical block diagram of heterodyne receiver system.

FIGURE 12.2 A typical block diagram of the Zero-IF receiver system.

FIGURE 12.3 Ideal multiplier model showing both up- and down-converter perfo...

FIGURE 12.4 Single-ended mixer employing diode switching model.

FIGURE 12.5 Typical mixer circuits employing diode switching model depicting...

FIGURE 12.6 LO and mixer spectra. (

a

) LO periodic switching time-domain sign...

FIGURE 12.7 Common mixer topologies: (

a

) single ended; (

b

) single balanced; ...

FIGURE 12.8 Energy levels for a metal and a semiconductor: (

a

) isolated meta...

FIGURE 12.9 Energy-level diagram of Schottky barrier as a function of applie...

FIGURE 12.10 Modulation spectra for a pumped nonlinear element allowing for ...

FIGURE 12.11 (

a

) Large-signal and (

b

) small-signal diode models.

FIGURE 12.12 Equivalent circuit for mixer LO analysis with the large-signal ...

FIGURE 12.13 Multiport model of pumped intrinsic diode.

FIGURE 12.14 Augmented

matrix for complete mixer.

FIGURE 12.15 Mixer diode noise model: (

a

) voltage representation from therma...

FIGURE 12.16 Noise correlation illustration: (

a

) IF output noise for a DC-bi...

FIGURE 12.17 Three main frequency components and filtering requirements for ...

FIGURE 12.18 LO impedance as a function of pump power.

FIGURE 12.19 Measurement setup for determining diode LO impedance.

FIGURE 12.20 Diode RF impedance measurement setup.

FIGURE 12.21 IF impedance measurement setup using a double-stub tuner.

FIGURE 12.22 Matching circuit for single-diode mixer with external ports at ...

FIGURE 12.23 Multiport matching network for single-diode mixer reduced to th...

FIGURE 12.24 Conversion loss degradation due to diode parasitics as a functi...

FIGURE 12.25 Parasitic element values for (

a

) GaAs and (

b

) silicon beam-lead...

FIGURE 12.26 LO, RF, and IF impedances of typical silicon beam-lead diode.

FIGURE 12.27 Element values for silicon beam-lead diode used in mixer exampl...

FIGURE 12.28 Return loss of LO and RF impedances of unmatched diode.

FIGURE 12.29 Single-diode mixer microstrip circuit layout with beam-lead sil...

FIGURE 12.30 LO and RF return loss performance of single-diode and matching ...

FIGURE 12.31 Ideal hybrid performance: (

a

) quadrature coupler (

); (

b

) balun...

FIGURE 12.32 Microstrip Lange coupler configurations: (

a

) four-strip; (

b

) si...

FIGURE 12.33 Microstrip Lange coupler fabricated on an alumina substrate: (

a

FIGURE 12.34 Branch line hybrid for 50-

system.

FIGURE 12.35 Microstrip branch line coupler performance: (

a

) amplitude respo...

FIGURE 12.36 Hybrid ring (“Rat-race”) general circuit model and stripline to...

FIGURE 12.37 Equivalent circuit of ring hybrid with port 1 excited and with ...

FIGURE 12.38 Multilayer stripline topology for a broadband ring hybrid emplo...

FIGURE 12.39 Microstrip ring (rat-race) hybrid performance: (

a

) amplitude re...

FIGURE 12.40 Enhanced bandwidth microstrip ring (rat-race) hybrid performanc...

FIGURE 12.41 Transformer hybrid constructed on a binocular ferrite core with...

FIGURE 12.42 Wire diagram of

transformer hybrid.

FIGURE 12.43 Voltage and current conditions in a transformer hybrid for vari...

FIGURE 12.44 Voltage and current conditions in a transformer hybrid when por...

FIGURE 12.45 Phase relationships between LO, RF, IF, and AM noise voltages i...

FIGURE 12.46 Single-balanced mixer employing

hybrid.

FIGURE 12.47 Phasor diagram illustrating LO, RF, and IF voltages: (

a

) RF and...

FIGURE 12.48 Circuit diagram of double-balanced mixer with transformer hybri...

FIGURE 12.49 Phase relationships between LO, conductance waveform, RF, and I...

FIGURE 12.50 LO and RF equivalent circuits for single-ring mixer: (

a

) model ...

FIGURE 12.51 Circuit diagram of star mixer with multiple secondary transform...

FIGURE 12.52 Low-frequency representation of double–double-balanced mixer.

FIGURE 12.53 Simple balun structures: (

a

) balanced-line quarter-wavelength-l...

FIGURE 12.54 Broadband high-pass balun structures: (

a

) coax to balanced line...

FIGURE 12.55 Double-balanced mixer constructed with microstrip-to-parallel-p...

FIGURE 12.56 Planar-coupled line balun structures.

FIGURE 12.57 Marchand compensated balun: (

a

) coaxial cross section; (

b

) equi...

FIGURE 12.58 Octave bandwidth double-balanced mixer using coaxial compensate...

FIGURE 12.59 Planar compensated balun fabricated on a low-dielectric substra...

FIGURE 12.60 Dual planar compensated balun: (

a

) metallization pattern; (

b

) l...

FIGURE 12.61 Interconnect configuration for planar orthogonal baluns and dio...

FIGURE 12.62 Double-balanced mixer for 20- to 40-GHz operation fabricated on...

FIGURE 12.63 Circuit model for 20- to 40-GHz mixer.

FIGURE 12.64 The 20- to 40-GHz mixer performance: (

a

) conversion loss; (

b

) i...

FIGURE 12.65 Dual-balun circuit arrangement for star mixer.

FIGURE 12.66 Star mixer employing glass packaged diodes.

FIGURE 12.67 Typical dual planar-compensated balun: (

a

) unbalanced port VSWR...

FIGURE 12.68 Dual microstrip-to-parallel-plate line baluns: (

a

) even excitat...

FIGURE 12.69 Double-ring mixer using orthogonal microstrip-to-parallel-plate...

FIGURE 12.70 Planar double-ring mixer with microstrip-to-parallel-plate line...

FIGURE 12.71 Triple-junction diode: (

a

) diode cross section; (

b

) simplified ...

FIGURE 12.72 Typical diode

–

characteristics: type A, conventional high-ba...

FIGURE 12.73 Compression characteristics of high-level up converter.

FIGURE 12.74 Two-tone distortion performance of high-level up converter.

FIGURE 12.75 Small-signal GaAs FET equivalent circuit with voltage source re...

FIGURE 12.76 Transconductance as a function of gate bias for a typical 150-

FIGURE 12.77 Circuit diagram of single-gate FET mixer showing signal, image,...

FIGURE 12.78 Conversion transconductance for a typical 150-

m FET.

FIGURE 12.79 Conversion gain as a function of LO drive voltage.

FIGURE 12.80 Gate-to-source capacitance as a function of bias.

FIGURE 12.81 X-band single-gate FET mixer reported by Pucel. (Pucel et al. [...

FIGURE 12.82 Conversion gain of X-band mixer as a function of LO driver powe...

FIGURE 12.83 Measure versus computed performance of X-band mixer.

FIGURE 12.84 Single-gate FET mixer used in harmonic balance analysis.

FIGURE 12.85 IF output voltage obtained from nonlinear analysis.

FIGURE 12.86 Computed mixer spectral performance.

FIGURE 12.87 Noise equivalent circuit of an FET.

FIGURE 12.88 Equivalent circuit of single-gate FET mixer used for noise anal...

FIGURE 12.89 Measured and calculated noise figure and conversion gain of mix...

FIGURE 12.90 Measured and calculated noise figure and conversion gain of mix...

FIGURE 12.91 Measured and calculated noise figure and conversion gain of mix...

FIGURE 12.92 Circuit diagram of drain-pumped single-gate FET mixer showing s...

FIGURE 12.93 Maximum available conversion gain of drain-pumped mixer as a fu...

FIGURE 12.94 Comparison between drain- and gate-pumped mixers: (

a

) conversio...

FIGURE 12.95 Dual-gate FET

–

characteristics: (

a

) intrinsic FET

–

charac...

FIGURE 12.96 Dual-gate FET drain current as a function of

and

.

FIGURE 12.97 Conversion gain characteristics of dual-gate FET as a function ...

FIGURE 12.98 Drain current and conversion gain performance of a typical MOSF...

FIGURE 12.99 Schematic diagram of distributed dual-gate FET mixer.

FIGURE 12.100 Monolithic distributed mixer chip photograph. (Courtesy of Tex...

FIGURE 12.101 Measured versus modeled conversion loss characteristics of dis...

FIGURE 12.102 Measured and modeled performance of LO saturation characterist...

FIGURE 12.103 Measured versus modeled performance of mixer bias sensitivity....

FIGURE 12.104 Single-balanced VMOSFET mixer. (Rohde et al. [12.35].)

FIGURE 12.105 Double-balanced JFET mixer employing broadband transformers.

FIGURE 12.106 Single-balanced MESFET mixer. (Based on Bura and Dikshit [12.3...

FIGURE 12.107 Measured conversion gain and double-channel noise figure of a ...

FIGURE 12.108 Third-order two-tone modulation curves obtained with balanced ...

FIGURE 12.109 Lumped-element equivalent circuit of center-tapped balun.

FIGURE 12.110 (

a

) Frequency response and amplitude balance of monolithic bal...

FIGURE 12.111 Center-tapped balun performance (distributed splitting balun w...

FIGURE 12.112 (

a

) Down-converter mixer circuit diagram; (

b

) up-converter mix...

FIGURE 12.113 Circuit diagram of double-ring mixer.

FIGURE 12.114 (

a

) Transmission line model of distributed active balun; (

b

) t...

FIGURE 12.115 Monolithic double-balanced mixer and active balun ICs. (Courte...

FIGURE 12.116 Monolithic double-balanced mixer conversion loss performance a...

FIGURE 12.117 Isolation performance of double-balanced mixer.

FIGURE 12.118 Conversion loss as a function of LO power.

FIGURE 12.119 RF compression characteristics.

FIGURE 12.120 (

a

) Monolithic active/passive double-balanced mixer. (Courtesy...

FIGURE 12.121 A typical equivalent circuit representation of a 3-terminal de...

FIGURE 12.122 Balanced nonlinear circuit: (a) without feedback and (b) with ...

FIGURE 12.123 A typical resistive mixer circuit (with RC series feedback).

FIGURE 12.124 A typical quasi-double balanced resistive mixer circuit.

FIGURE 12.125 A typical quasi-double balanced resistive mixer with pulse-sha...

FIGURE 12.126 Block diagram of reconfigurable passive FET mixer.

FIGURE 12.127 Dynamic gate pulse shaping network.

FIGURE 12.128 Conversion loss performance of monolithic double-ring mixer.

FIGURE 12.129 (

a

) Isolation and (

b

) compression performance of monolithic do...

FIGURE 12.130 (

a

) Image rejection and (

b

) single-sideband mixer topology.

FIGURE 12.131 Frequency spectra at various points within the image rejection...

FIGURE 12.132 Image rejection as a function of circuit amplitude and phase e...

FIGURE 12.133 Typical image rejection mixer consisting of a dual double-bala...

FIGURE 12.134 Image rejection mixer circuit configuration.

FIGURE 12.135 Performance of 2- to 10-GHz image rejection mixer: (

a

) image r...

FIGURE 12.136 Single-sideband 8- to 18-GHz modulator fabricated on a quartz ...

FIGURE 12.137 Single-sideband modulator circuit configuration.

FIGURE 12.138 Single-sideband modulator performance: (

a

) carrier suppression...

FIGURE 12.139 Monolithic GaAs FET single-sideband modulator. (Courtesy of Te...

FIGURE 12.140 FET modulator circuit configuration.

FIGURE 12.141 Input and output voltage waveforms for SSB modulator.

FIGURE 12.142 Measured versus computed spectral performance of SSB modulator...

FIGURE 12.143 Simplified circuit configuration of subharmonically pumped dio...

FIGURE 12.144 Typical single-ended subharmonically pumped MMIC mixer.

FIGURE 12.145 Differential CMOS mixer, indicating the origins of noise. (1) ...

FIGURE 12.146 Contributions of the four basic noise sources to the output mi...