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- Herausgeber: John Wiley & Sons
- Kategorie: Wissenschaft und neue Technologien
- Sprache: Englisch
Written for scientists, researchers, and engineers, Non-volatile Memories describes the recent research and implementations in relation to the design of a new generation of non-volatile electronic memories. The objective is to replace existing memories (DRAM, SRAM, EEPROM, Flash, etc.) with a universal memory model likely to reach better performances than the current types of memory: extremely high commutation speeds, high implantation densities and retention time of information of about ten years.
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Veröffentlichungsjahr: 2014
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Contents
Acknowledgements
Preface
PART 1: Information Storage And the State of the Art of Electronic Memories
1 General Issues Related to Data Storage and Analysis Classification of Memories and Related Perspectives
1.1. Issues arising from the flow of digital information
1.2. Current electronic memories and their classification
1.3. Memories of the future
2 State of The Art of DRAM, SRAM, Flash, HDD and MRAM Electronic Memories
2.1. DRAM volatile memories
2.2. SRAM memories
2.3. Non-volatile memories related to CMOS technology
2.4. Non-volatile magnetic memories (hard disk drives – HDDs and MRAMs)
2.5. Conclusion
3 Evolution of SSD Toward FeRAM, FeFET, CTM and STT-RAM Memories
3.1. Evolution of DRAMs toward ferroelectric FeRAMs
3.2. The evolution of Flash memories towards charge trap memories (CTM)
3.3. The evolution of magnetic memories (MRAM) toward spin torque transfer memories (STT-RAM)
3.4. Conclusions
PART 2: The Emergence of New Concepts: The Inorganic NEMS, PCRAM, ReRAM and Organic Memories
4 Volatile and Non-volatile Memories Based on NEMS
4.1. Nanoelectromechanical switches with two electrodes
4.2. NEMS switches with three electrodes
4.3. Conclusion
5 Non-volatile Phase-Change Electronic Memories (PCRAM)
5.1. Operation of an electronic phase-change memory
5.2. Comparison of physicochemical characteristics of a few phase-change materials
5.3. Key factors for optimized performances of PCM memories
5.4. Conclusion
6 Resistive Memory Systems (RRAM)
6.1. Main characteristics of resistive memories
6.2. Electrochemical metallization memories
6.3. Resistive valence change memories (VCM)
6.4. Conclusion
7 Organic and Non-volatile Electronic Memories
7.1. Flash-type organic memories
7.2. Resistive organic memories with two contacts
7.3. Molecular memories
7.4. Conclusion
Conclusion
Bibliography
Index
First published 2014 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.
A part from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:
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John Wiley & Sons, Inc.111 River StreetHoboken, NJ 07030USA
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© ISTE Ltd 2014The rights of Pierre Camille Lacaze and Jean-Christophe Lacroix to be identified as the authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988.
Library of Congress Control Number: 2014953190
British Library Cataloguing-in-Publication DataA CIP record for this book is available from the British LibraryISBN 978-1-84821-623-5
Acknowledgments
Upon completion of this work, we wish to thank all the people who have contributed to it with their valuable advice and suggestions. We greatly thank Robert Baptist, Research Director at the Laboratoire d’Electronique des Technologies de l’Information (CEA-LETI, Grenoble) for having peer-reviewed the French version of the manuscript and providing sound advice. We also thank Damien Deleruyelle, researcher at the Institut Matériaux Microélectronique Nanosciences of Provence (Im2np) with whom we had fruitful discussions. We are grateful to W. Bruch for his translation of this scientific text, and to John S. Lomas, Research Director at the CNRS, for polishing the English translation. We are indebted to Céline Benoit, in charge of scientific documentation in the Physics department at the University Paris Diderot, who helped us greatly in the search for documentation. We also thank our respective wives for their great patience during this long period of research and writing.
Preface
Information storage is a research topic of great importance in the electronic component industry. The constant increase in the quantity of information in circulation on the planet has created an ever more urgent need for more efficient memory systems characterized by shorter execution times (at the nanosecond level), low energy consumption and data retention times that go beyond a decade. Current electronic memories by no means satisfy all these criteria, which explain the enormous amount of research carried out worldwide by companies specialized in the manufacture of electronic components, as well as by academic laboratories.
In addition to improvements to existing systems, great efforts are being made on the development of new concepts likely to lead to the emergence of more efficient memory devices. Three emerging systems are currently the focus of intensive research that could lead to the commercialization of new products: spin-torque transfer magnetic memories (STT-MRAMs), phase-change memories (PCRAMs) and resistive memories (RRAMs).
The electronics industry is also very interested in the elaboration of electronic memories by printing onto many different kinds of flexible supports, such as paper and plastic. It is clear that the objective here is not to replace silicon technology, which remains at the heart of the elaboration of existing transistors and memories. As with photovoltaic technology, the aim is to develop new low-cost devices for domestic applications that do not require high execution speeds or storage capacities. This research, still the focus of several teams, depends on experimentation and the discovery of new molecular components, generally based on organic compounds and soft chemical techniques.
Taking into account the diversity and complexity of physical, chemical and electrochemical phenomena applied in these new emerging memories, this book attempts in the simplest possible way to describe the origin of memory effects. The performances of various existing systems are compared with those of systems currently undergoing development and evaluation; the reasons behind their limitations are discussed.
This book is mainly addressed to researchers in nanosciences, and chemists and physicians involved in the physical chemistry of solids and materials in the form of thin mineral or organic layers. Indeed, their work could lead to promising applications in the domain of information storage.
Pierre-Camille LACAZEJean-Claude LACROIXOctober 2014
PART 1
Information Storage and the State of the Art of Electronic Memories
1
General Issues Related to Data Storage and Analysis Classification of Memories and Related Perspectives
Over the past few years, the massive increase in the volume of information has encouraged the search for ways to resolve issues related to data storage and processing. The technical means for resolving these problems go hand in hand with the improvement of read–write–erase speeds, a reduction in energy consumption of electronic memory devices as well as an increase in their storage capacity. A short description of the characteristics of the different types of memories, volatile or non-volatile, reveals the existence of a technological gap between the performance of extremely rapid volatile memories and non-volatile memories, the latter being used for storage, but too slow for handling large volumes of data. The search for universal memories capable of combining storage and processing capabilities for data-use is a new field of research in the industry. In the years to come, this is expected to lead to the progressive replacement of current systems by new generations of memories with qualification characteristics equivalent to those of “Storage Class Memories” (SCMs).
1.1. Issues arising from the flow of digital information
Information storage and the continuous increase in the volume of information circulating in the world are topics that preoccupy large bodies responsible for political anticipation and decision-making. A recent report by the International Data Corporation (IDC), “The Digital Universe in 2020” [GAN 12], indicates that the volume of digital information in the world decupled between 2006 and 2011, increasing from 180 to 1,800 Exabytes (EBs)1, and should reach an astounding 40,000 EBs by 2020, the equivalent of 5,200 Gigabytes (GBs) per human being.
This trend is not expected to slow down – the authors of the report estimate that the volume of digital information will double every two years from 2012 to 2020 – thus leading de facto to the consideration of issues in energy consumption inherent in the running of large servers that, for obvious reasons, are now preferably located close to centers of electrical energy production and distribution, a tendency emphasized by the recent boom in “Cloud Computing” [MEL 11].
Since the 1990s, digital technologies have taken over from analog technologies. In 2007, 99.9% of telecommunications were carried-out digitally. As of the early 2000s, the majority of information was also stored in digital mode, representing 94% of all stored information in 2007 [HIL 11].
This irreversible and ultra-fast increase in the global flux of information with, in addition to this, a strong demand for increasingly powerful computers, requires an extreme miniaturization of electronic components and memories. The end of the applicability of Moore’s Law2 is considered as imminent, and new solutions must be found to resolve issues related to information storage.
This question has already been considered by many bodies, and a very general prospective has been developed over the years with a view to the possible replacement of current components (transistors and memories), essentially founded on silicon-based technology, by new systems based on materials capable of increasing the integration density of components in the electronic circuits so as to improve energy efficiency while promoting high operational reliability.
1.2. Current electronic memories and their classification
Computers and information storage currently depend on the use of two kinds of memories: volatile and non-volatile (Figure 1.1).
Volatile memories (essentially Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM)), which are used to run computers, have very short execution times but, unfortunately, the conservation of data with time (retention) requires either periodical refreshing (DRAMs) or a constant power supply (SRAMs), both of which are costly in terms of energy.
Non-volatile memories, consisting mainly of hard drives (Hard Disk Drives (HDDs)) and more recently Flash memories (NOR and NAND) have retention times that are convenient for the requirements of information storage. At rest, they do not require a power supply but have read–write and erase times that are too long for logic operations. They are used for storage and are classified as Read Only Memory (ROM) memories. Magnetic memories (MRAM) are also non-volatile and very fast, and can be addressed in random access.
Among volatile memories, DRAMs and SRAMs are the main memories used to run logic operations. DRAMs have very short retention times (at the ms level or less) and therefore require periodical refreshing. SRAMs conserve information when they are connected to a power supply, and lose this information when the power is off. This last type of memory, for which write, read and erase tasks are very rapid (a few nanoseconds), is mostly used in computers as cache memory3.
Non-volatile memories, which have very high retention times, must be considered as peripheral components of the computer that do not take part in logic functions. They are used for reading information that is archived, and hence are referred to as ROM.
Within this first and very general definition, a distinction is made between memories used to store information that is considered as programmed just once, and can be read without any possible modification – One Time Programmable Read Only Memory (OTPROM) or Write One Time Read Many (WORM) – and those where the information can also be indefinitely conserved, but this time, with the possibility of modifying it when required – EPROM memories, i.e. ROM memories that can be erased and reprogrammed.
Figure 1.1.Classification of the main current types of volatile and non-volatile memories. Adapted from Jeong et al. [JEO 12]
The first memories of the latter type, known as UV-EPROM, which appeared on the market in the 1970s, could be erased by exposing the entire device to prolonged UV irradiation. In the 1980s the first memories appeared that could be written and erased electronically (Electrically Erasing PROM (EEPROM)) but that could also conserve the information indefinitely, therefore providing an advantageous replacement for UV-EPROM.
Flash memories, first produced in the 1980s by Toshiba, and a few years later by INTEL (1988), were derived from EEPROM memories. These memories are in fact an assembly of EEPROMs that, depending on their connection mode (parallel or series), lead to NOR Flash and NAND Flash memories. In the past few years, these memories have been the object of considerable industrial development and are considered as future storage memories, capable of competing with magnetic hard drives.
Their common feature is the local appearance or disappearance of an electrical charge trapped in a “floating” electrode, designated as a storage “node”, and corresponding to processes involving “charge storage nodes” [ZHI 12].
The magnetic storage of information is without doubt the oldest procedure4. Magnetic hard drives (HDD) rely on a process in which the memory effect is due to the recognition of magnetic microdomains that can be reversibly created and erased. They constitute exceptional non-volatile memories that have the advantage of allowing periodical and almost indefinite writing and erasure of data, and are able to conserve it for as long as the rotating disk is functional. The most significant event that can lead to the loss of data is a mechanical incident that crashes the read–write head onto the rotating disk, which unfortunately, like any catastrophe, occurs without warning and not infrequently. Contrary to HDDs, for which access to data is sequential, MRAM magnetic memories operate by random access and no longer have any mechanical parts, but require greater space, due to the number of leads necessary for the magnetic field, and have a higher energy consumption, for which reasons they are restricted to specific applications (see Chapter 2, section 2.4.5).
1.3. Memories of the future
For a long time the electronic memory industry was dominated by the production of DRAMs and HDDs, and it is only recently, with the beginning and the intrusion into everyday life of portable devices of all kinds, that the share in the market of Flash memories (Solid State Drives (SSD)) has considerably increased compared to that of HDDs.
It is admitted, however, that the scale reduction of floating gate Flash memories beyond the 16 nm scale will be difficult to achieve without a significant increase in their manufacturing costs [BUR 13].
The ambition to develop ever more powerful yet less power-hungry calculators, while remaining within reasonable costs, implies that either great progress has to be made in the conception of storage hard drives or that new approaches for data storage must be considered.
It is this research effort toward new technologies that has led the industry to select a limited group of systems capable of combining the dynamic characteristics of DRAMs with storage characteristics close to those of HDDs.
The International Technology Roadmap for Semiconductors5 (ITRS) in its 2010 editions (Emerging Research Materials, [HUT 10, ITR 11]) suggests new paths in research for the elaboration of electronic memories so as to reduce energy consumption but also increase the density of chip memories. The evolution toward two-contact memories, which remains compatible with current Complementary Metal Oxide Semiconductor (CMOS) technology, is considered as being the best solution [ITR 11].
In order to better understand the challenges involved in the development of information, with the related problems, the necessity for shorter and shorter access times and for increasingly large storage capacities (in terms of time and quantity), we show in Table 1.1 a few essential properties of the most widely used types of memories that make up the major part of the market.
Table 1.1.Comparative study of operational characteristics of the main commercialized volatile (SRAMs and DRAMs) and non-volatile (NAND Flash and HDD) memories
COMMENTS ON TABLE 1.1.– (a) The energy required to write a bit with an EEPROM cell is of the order of 100 picojoules (pJ). The mode whereby a very large number of cells are addressed simultaneously explains why the energy is significantly reduced in Flash memories. (b) The energy per bit for an HDD is estimated from the power used for a given number of write cycles. The 5 × 103 and 104 pJ values have been calculated for a number of write cycles of 28 and 16 megabytes (MB) per watt for Western Digital (RED WD30EFRX and Black WD4001FAEX) hard drives. (c) This number of cycles (small) indicates the average reliability of the electromechanical system. All other data are extracted from Yang et al. [YAN 13], Jeong et al. [JEO 12] and the ITRS report [ITR 11].
We have selected the space requirement criterion, given by the number of F2 units taken by the memory6, the energy in picojoules (pJ) required to write one bit of information, the time (in nanoseconds) required to write and read a bit, the retention time of the information, and endurance to cycling. Obviously, of all the memories (SRAM, DRAM, Flash (NAND) and HDD), there is not one that combines the two essential qualities: fast write and read operations at the nanosecond scale and data retention over several years.
Table 1.1 presents two groups of memories, that are not only distinct from one another in that some are volatile (DRAMs and SRAMs) and others non-volatile with retention times of several years (Flash and HDDs), but also in that the former have read–write times on the nanosecond scale, whereas those of the second group (Flash and HDDs) are considerably longer (100 µs for NAND Flash and between 5 and 8 ms for HDDs).
From the energy point of view, we note that HDDs are the most power-hungry (between 5 × 103 and 104 pJ, as against 2 × 10-5 pJ for NAND Flash), one of the main reasons being that the disks rotate constantly, thus considerably increasing the energy costs7.
From the point of view of space requirements, it is SRAMs that, due to their complexity (memory consisting of 6 transistors), take up the most space (140F2), followed by DRAMs (between 6 and 10F2). Their high manufacturing costs and their considerable size have limited their use compared to DRAMs, which have a simpler structure and higher integration density.
All the above considerations show that there is a technological gap between the characteristics of DRAM and SRAM memories and those of Flash and HDD memories. This conclusion justifies the search for new memory devices with characteristics approaching those of DRAMs, for their high read–write speeds, and those of NAND Flash and HDDs, for their high data storage and retention capabilities.
This research is therefore directed toward the elaboration of “polyvalent” memories capable of fulfilling the logic functions of DRAMs and SRAMs as well as the archiving functions of Flash and HDD memories. These properties should lead to a group of new generation memories, qualified by Freitas and Wilcke [FRE 08] as SCM.
Hutchby and Garner [HUT 10], in the 2010 ITRS evaluation report concerning emerging materials and devices (Emerging Research Devices and Emerging Research Materials), recommend several new systems that appear compatible with the objectives of future electronic memories, on which they consider research must focus and intensify so as to allow commercial use in five to ten years.
For this, it must be demonstrated that the devices perform well, the way they work will have to be clearly established and, finally, they will have to be compatible with 16 nm8 technologies and beyond, thus allowing a high integration density, with space requirements below 4F2.
As a result, systems considered as potentially viable for future use are as follows:
In conclusion, we can divide the previous list into two memory categories. The first ((1) to (2)) is related to new devices which can be considered as the result of improvements on existing systems; the second concerns systems based on entirely new concepts ((3) to (4)).
In line with this classification, we have structured this work into two parts: the first is dedicated to the description of current memories and their evolution, while the second focuses on new concepts of memory. The execution speed and information storage properties of some of these qualify them as SCMs, according to ITRS estimates.
1 An EB represents 1018 bytes or 1 billion Gigabytes
2 Moore’s Law, laid down during the boom in computing (1965), stipulates that the number of transistors implanted on a “chip” approximately doubles every two years, which means that the width of the printed circuit lines decrease by a factor of 0.7 for each generation of transistors.
3 Cache memory is temporarily saved data that is extracted from the main memory. It is a data and instruction “reserve” used to run repetitive operations, and has the advantage of being very rapidly accessible, the effect of which is to shorten execution times of certain computing operations.
4 The first device at the origin of current hard drives was produced by IBM in 1954 (350-Random Access Method of Accounting and Control (RAMAC)). It weighed over a ton, consisted of 50–60 cm-diameter disks, had a storage capacity of just 5 megabytes. In 1956 it cost more than 50,000 dollars [IBM 57].
5 The ITRS is an international body created by the Semiconductor Industry Association (SIA) that ever since its formation in 1977 has guided the majority of the major American electrical component manufacturers by proposing important R&D directions, the latter discussed and established by a committee of researchers and engineers, which has led to the birth of the National Technology Roadmap for Semiconductors (NTRS). This committee rapidly grew on the international scale and, in 1998, several countries associated themselves with the SIA to found ITRS, a body that is now sponsored by Europe, Japan, South Korea, Taiwan and the USA. Since 1999 this new international body has published an important report every year, the fruit of a widespread consensus between manufacturers, whose goal is to guide the semiconductor industry in its choice of R&D programs with a realistic vision of “emerging” systems for the 15 years to come. It is also at the origin of “More than Moore” (MtM), a concept for the development of new technologies, implying the creation of devices that combine different functionalities on the same electronic chip.
7 In large data archiving centers relying on HDDs the data may be split over two types of servers, those for which the reading demand is frequent and others where the data is considered as archived and rarely accessed. In the second case this distinction allows the magnetic hard drives to be switched off and therefore power consumption to be reduced.
8 In its 2011 edition (Executive Summary, p. 78), the ITRS expects 16 nm technology to emerge by 2015 and to be applicable for the manufacture of Flash memories.
2
State of the Art of DRAM, SRAM, Flash, HDD and MRAM Electronic Memories
In this chapter we describe the main characteristics of currently commercialized volatile (dynamic random access memories (DRAMs) and static random access memories (SRAMs)) and non-volatile (solid state drives (SSDs or Flash), hard disk drives (HDDs) and magnetic random access memories (MRAMs)) memories.
2.1. DRAM1volatile memories
DRAMs are memories that conserve the information over a very short period of time (over an ms, or less) and consequently must be periodically refreshed without fault. A 1T/1C DRAM generally consists of a metal oxide semiconductor field effect transistor-type (MOSFET-type) and a capacitor.
2.1.1. The operating principle of a MOSFET (metal oxide semiconductor field effect transistor)
Though very old in its principle, the thin film MOSFET structure was first developed in the 1960s at the Bell Labs. The transistor includes an n- or p-doped (generally silicon) semiconductor (SC) and three or four electrodes used as electrical contacts. Two contacts, source (S) and drain (D), implanted into the SC, define a conduction channel (length (L) and width (W)). This channel is located below the insulating layer (SiO2) at the extreme surface of the semiconductor, and is connected to S and D (Figure 2.1).
Figure 2.1.a) Cross-section of an n-type MOSFET. The body of the semiconductor is p-silicon; b) symbolic representation of n- and p-type MOSFETs; (c) view from above the MOSFET. The parts colored in dark gray represent the metal contacts
COMMENTS ON FIGURE 2.1. – In (a) the semiconductor (SC) body is made of silicon. Two very high n-doped regions (n+) are created through ionic implantation at the surface of the SC. These two regions, of quasi-metallic conductivity, constitute the source (S) and drain (D) electrodes. The gate (G), designated as the control gate (CG) is obtained by depositing a metal or poly-Si onto a thin insulating layer (SiO2), resulting from a superficial oxidation of the Si. The dotted lines represent the electrons in the channel (length (L) and width (W)).
A small current IDS flows into the channel when a small voltage VSD is applied between S and D. The third contact (metallic) separated from the SC by a thin SiO2 insulating layer is the control gate CG, to which is applied a voltage VSG relative to the source S.
The source-drain current IDS due to minor charge carriers of the SC (electrons for a p-SC, or holes for an n-SC) is modulated by the gate potential (VSG).
In the case of a p-SC, the current IDS resulting from the injection of electrons by the source is located in a very narrow conduction channel at the SC–insulator interface, and corresponds to a layer of inversion of the charge carriers of the SC. A positive polarization of the gate attracts the electrons at the interface and repels the positive charges toward the inside of the SC. The current is therefore stronger for a higher gate voltage.
Though the body of the SC is p-type, the MOSFET is considered as n-type due to the nature of the charge carriers in the channel. Conversely, an n-type semiconductor will have a p-type channel and will consequently be considered as a p-type MOSFET. In this latter case, the S and D electrodes are formed by implantation zones corresponding to p+ doping [ZEG 11].
The use of this technology rapidly grew in popularity in the microelectronics industry for two essential reasons:
MOSFET characteristics are described by two types of curves:
In Figure 2.2(a) and for a given VGS, two regions of the drain current IDS are distinguished depending on VDS:
where µlin is the electron mobility in the linear regime, Ci the capacitance of the insulating layer located between the gate and the SC, and VTh the threshold gate voltage (defined later);
where µsat represents the charge carrier mobility in the saturation region.
Figure 2.2.Electrical characteristics of an n-type MOSFET (current and voltage in arbitrary units); a) output curves for different VGS gate potentials (VGS increasing). For each curve corresponding to a single VGS value we observe a region where the current increases linearly with VSD (linear regime) and a region where it remains constant (saturation regime); b) transfer curves, log(IDS) vs. VGS and (IDS)1/2 vs. VGS, at constant VDS. Adapted from [ZAU 07]
As we will see later, this quantity is particularly important in the definition of the operation of electronic memories based on floating gate MOSFETs.
2.1.2. Operating characteristics of DRAM memories
They consist of a MOSFET and a capacitor, linked to two conducting command lines, orthogonal to each other (word line and bit line). The device includes three contacts; it is generally referred to as a 1T/1C memory (Figure 2.3).
Figure 2.3.Scheme of a DRAM memory made of an n-type MOSFET and a capacitor, linked to the word and bit lines, respectively, driving the gate and drain voltages. Adapted from [SCO 07]
Each DRAM memory can store a ‘1’ or ‘0’ bit corresponding to the capacitor charge or lack of charge, respectively.
Programming and erasing the capacitor charge are carried out by the transistor, the latter acting as a switch for the capacitor (considered as a storage node). The closing and opening of the channel, controlled by the gate voltage, is therefore dictated by the word line that defines the access or non-access to the capacitor. The bit line, directly linked to the transistor channel, is then able to charge (bit ‘1’) or discharge (bit ‘0’) the capacitor.
The charge is read with the bit line after the opening of the channel through the word line. The drawback of this process is that reading implies the destruction of the capacitor charge, this requiring immediate restoration.
The simplicity of the manufacturing process which de facto implies a low cost and, moreover, a high integration density at the 6F2 scale, allowing several billion transistors on the same chip, is obviously an advantage.
Other advantages include their high endurance to cycling (greater than 1016), which make them almost indestructible, as well as their very high programming and erasing speeds, with switching times less than 10 ns, that fully justify their use to carry out logic operations of computers at very high speed [JEO 12].
The main drawback of this type of memory is its very high volatility due to the fact that the electrical charge stored by the capacitor is rapidly dissipated, therefore requiring refreshing approximately every millisecond. Another drawback is that the charge stored in the capacitor is destroyed during reading, this also requires a new charge operation immediately after reading, as well as a greater complexity of the connectics.
2.2. SRAM memories
SRAMs are also volatile memories but, in contrast to DRAMs, the information is stored as long as the device is connected to a power supply, and loses it as soon as its connection to the latter is removed.
The device, which is more complex than a DRAM, is made of several transistors, six generally, and is therefore referred to as 6T memory (Figure 2.4).
The memory comprises a 4-transistor storage cell or latch (shown in dark gray in Figure 2.4), formed by two crossed voltage inverters M1-M2 and M3-M4 (see Box 2.1). This set-up, typical of CMOS technology, and equivalent to a “flip-flop” circuit, has the ability to store information ‘0’ or ‘1’ (the logic equivalent of low or high voltage) in a stable state as long as the system is powered.
Figure 2.4.Functional diagram of a 6-transistor SRAM memory, consisting of a latch (crossed inverters M1-M2 and M3-M4) and of two access transistors M5 and M6. The input signal Q of the M1-M2 inverter is linked to the output of the M3-M4 inverter, and inversely the input signal of the M3-M4 inverter is linked to the output of the M1-M2 inverter. M5 and M6 transistors are comparable to two switches driven by the word line WL that simultaneously polarizes the gates of these transistors and allows the two bit lines BL to read the stored information
Box 2.1.CMOS inverter characteristics
The two binary signals Q and (‘0’ and ‘1’ or ‘1’ and ‘0’) stored in the latch are transmitted to the two bit lines (BL and ) by two access transistors, M5 and M6 (light gray regions), which are opened or closed by a word line connected to each of the gates of the M5 and M6 transistors.
The operation of the memory can be summarized by three functions: stand-by, read, and write or erase.
The stand-by function, corresponding to the conservation of information ‘0’ or ‘1’ in the latch, is imposed by the word line by applying a negative or low voltage at the gates of the two n-type MOSFETs M5 and M6, making them non-conductive, and is equivalent to isolating the latch from the two BLs.
Read, on the other hand, is obtained by putting the latch in communication with the two BLs. A sense amplifier (not represented here), connected to the two BLs, identifies which line has the stronger signal, and thus reads the initial information carried by the BL3.
Writing and erasing are carried out by opening the channels of the transistors M5 and M6 and by imposing the values ‘0’ and ‘1’ on the two BLs.
From a practical point of view, SRAM memories are extremely rapid and have commutation times of a few tenths of a nanosecond, which makes them 10 times faster than DRAMs. The number of cycles (write – erase) is, as for DRAMs, almost unlimited (>1016). Though they are volatile when the power supply is cut, they do not require periodical refreshing, making them more advantageous than DRAMs in terms of energy consumption.
Unfortunately, their complexity makes them expensive to manufacture, and their large size (area > 140F2) does not allow high integration densities.
As a result, their use in computers is limited to low-capacity cache memory, which is used to carry out repetitive operations at high speed, thus considerably shortening the execution times of complex operations.
2.3. Non-volatile memories related to CMOS technology
This refers mainly to devices derived from the MOSFET technology that initially led to electrically erasable programmable read only memory (EEPROM) memories, and later to Flash memories.
The introduction into a MOSFET of a metallic floating gate, separated from the control gate and from the SC by two very thin insulating layers, gives rise to a memory effect, discovered in the 1960s by Kahng and Sze, at the Bell Labs [KAH 67]. Charging the floating gate at different levels induces a shift in the operating threshold VTh of the MOSFET, thus opening a read window between the ‘1’ and ‘0’ states, corresponding to the charge or lack of charge in the floating gate.
A considerable advantage compared to DRAMs is that the charge stored in the floating gate can be preserved over very long times (10 years approximately), and also, in contrast to DRAMs, the read process does not destroy the charge stored in the gate.
2.3.1. Operational characteristics of a floating gate MOSFET
The structure constitutes a charge storage node and differs from a MOSFET in the additional introduction of a metallic floating gate FG, surrounded by an insulating material (Figure 2.5).
Figure 2.5.MOSFET with a floating gate (FG). Metallic deposits are in dark gray and insulating layers (metal oxide) that surround FG are in white
The charge stored in the floating gate acts as an electrostatic screen for the control gate CG and, consequently, shifts the operating threshold VTh of the transistor.
The transfer curves of the transistor are shifted parallel to the VGS axis (Figure 2.6). This shift, which increases with the charge, occurs toward positive or negative voltages depending on whether SC is n- or p-type.
In the absence of charge in the floating gate, the transfer curve indicating the drain current IDS variation with the control gate voltage VGS is characterized by a threshold operating voltage equal to VTh(1). This threshold voltage is shifted toward positive voltages and is equal to VTh(0) when the floating gate acquires a negative charge.
When a VGS between VTh(1) and VTh(0) is applied to the control gate, the two memory states are read by measuring IDS: a high current IDS corresponding to the absence of a charge in the floating gate, defines the ‘1’ state whereas a low current intensity, resulting from a negative charge, defines the ‘0’ state. It is easier to read both ‘0’ and ‘1’ states for greater Δ(VTh(1) – VTh(0)) values.
Programming is therefore equivalent to injecting an electrical charge into FG. In contrast to this, erase corresponds to the discharge of FG and the return to the initial value VTh(1) of the gate potential.
Figure 2.6.Operational characteristics of an n-type floating gate MOSFET
2.3.1.1. How to charge and discharge the floating gate?
In the case of an n-type MOSFET, the injection of electrons into the floating gate is carried out by applying a positive and significant potential to the control gate CG (10–15 V) and by maintaining a small current between the source and the drain (requiring the application of a difference VDS of a few volts) (Figure 2.7(a)).
This charge carrier injection occurs through the oxide layer next to the channel and can only take place if the electrons in the channel have sufficient kinetic energy to jump over the insulating barrier, a mechanism known as “hot electron injection” [CON 67].
Figure 2.7.Diagrams of charge a) and discharge b) of an n-type floating gate MOSFET
COMMENTS ON FIGURE 2.7.– For both charge and discharge, the electrons are made to move from the channel to the floating gate through the oxide layer 1. The floating gate FG is charged by briefly polarizing the control gate at a potential VGC VTh; it is discharged by applying a potential VGC VTh. Generally, to discharge FG, the source and the drain (n+ regions corresponding to an n-type over-doping) are grounded, whereas a small positive voltage is applied to the drain to charge FG, the source remaining earthed.
The discharge reaction occurs through a different mechanism and corresponds to tunnel effect injection of the electrons in an intense electrical field, of Fowler–Nordheim type [FOW 28]. This is achieved by applying a very negative voltage to the control gate CG and by keeping the drain and the source connected to ground. Electrons are re-injected into the MOSFET channel, thus restoring its initial ‘1’ state (Figure 2.7(b)).
All these operations are performed with voltage pulses that require a minimum of duration for write (charge of FG) as well as erase (discharge of FG). These potential pulses and their duration are obviously a function of the dimensions of the transistor and the size of FG. With current technology, write and erase for this type of memory takes between 0.1 and 10 ms, which is very long and is approximately one million times greater than that for SRAMs or DRAMs [JEO 12].
Write and erase are addressed separately for each memory cell, allowing to treat them individually. This requires, however, two additional transistors per cell: one for read and another for erase, also contributing to the increase in the general size of the memory to the 12F2 scale [YAN 13].
Their resistance to cycling is closely related to the physical characteristics of the memory and the way the floating gate is charged and discharged through the insulating layer. As a result, depending on the write and erase modes, the endurance, one of the weaknesses of this type of memory, varies from 104 to 105 cycles.
2.3.1.2. Physical problems related to the storage of electrical charges and their impact on the operation of a floating gate memory
Three properties determine whether a floating gate memory works well or not: the retention time of the charge in the gate has to be as long as possible (generally >10 years); the speeds of injection and ejection of this charge determine the write and erase time performances; the minimum charge stored which allows reliable reading by the field effect transistor.
2.3.1.2.1. Charge retention
Charge retention is a function of the energy barriers that appear every time an insulator is in contact with an SC or a metal, and for which different conduction mechanisms can be considered (see Box 2.2).
As a result, in the case of a symmetrical Metal/Insulator, (I1)/Metal/Insulator, or (I2)/Metal structure, an electrical charge located in the “potential well” created by the I1/Metal/I2 junction is isolated by two energy barriers of height Wb and of width a (Figure 2.8).
This electrical charge has two possibilities to exit from the potential well (equivalent to the floating gate): either by a tunnel effect (IT current) through the two barriers, or by jumping over the barrier (thermionic emission), after gaining a quantity of energy greater than Wb (current Io-b).
Actually, the presence of electrical charges in the wells increases its potential to Vs, equal to eNs/Cm, where e represents the charge of an electron, Ns the number of electrons trapped in the well and Cm the equivalent capacity of the I1/M/I2 structure. This results in a modification of the profiles of the energy barriers.
Figure 2.8.Diagram of an electrical charge trapped in the potential well resulting from the I1/M/I2 structure (Insulator/Metal/Insulator). Io-b and IT represent leakage currents occurring, by thermionic emission or tunnel effect, respectively. Adapted from [ZHI 12]
Initially rectangular, the energy profiles become trapezoidal, with an increasingly narrow triangular part as the charge becomes greater, which makes electron transfer by tunnel effect easier (Figure 2.9).
Figure 2.9.Energy profile of a symmetrical I1/MFG/I2 structure in the presence of a charge on the floating gate MFG. Adapted from [ZHI 12]
As a consequence, the greater the charge, the more leakage is significant, and the less time the charge is retained. This is the reason why, in practice, the charge is limited to a number of electrons so that eVs does not exceed a value significantly greater than Wb/2.
Under these conditions, the maximum number Nmax of electrons that can be stored in the floating gate is of the order of:
Adapted from [YAN 13] and [WON 12]
Box 2.2.Conduction mechanisms of electrons for a polarized Metal/Insulator/Metal junction
From these numerical values, the theoretical retention times of the charges in a MOSFET floating gate structure can be predicted, by estimating that losing half the charge is a limit that must not be exceeded to ensure the memory works well.
As a result, considering that the charges can disappear by thermionic emission and the tunnel effect, the time tr necessary for the initial charge to decrease by half is:
where factor 2 comes from the fact that, statistically, the electrons can escape in two opposite directions.
By calculating the average of thermionic current IT and tunnel current Io-b depending on Wb and a
