Power Integrity for Electrical and Computer Engineers E-Book

J. Ted Dibene

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 856

Veröffentlichungsjahr: 2019

Beschreibung

A professional guide to the fundamentals of power integrity analysis with an emphasis on silicon level power integrity Power Integrity for Electrical and Computer Engineers embraces the most recent changes in the field, offers a comprehensive introduction to the discipline of power integrity, and provides an overview of the fundamental principles. Written by noted experts on the topic, the book goes beyond most other resources to focus on the detailed aspects of silicon and optimization techniques in order to broaden the field of study. This important book offers coverage of a wide range of topics including signal analysis, EM concepts for PI, frequency domain analysis for PI, numerical methods (overview) for PI, and silicon device PI modeling. Power Integrity for Electrical and Computer Engineers examine platform technologies, system considerations, power conversion, system level modeling, and optimization methodologies. To reinforce the material presented, the authors include example problems. This important book: * Includes coverage on convergence, accuracy, and error analysis and explains how these can be used to analyze power integrity problems * Contains information for modeling the power converter from the PDN to the load in a full system level model * Explores areas of device level modeling of silicon as related to power integrity * Contains example word problems that are related to an individual chapter's subject Written for electrical and computer engineers and academics, Power Integrity for Electrical and Computer Engineers is an authoritative guide to the fundamentals of power integrity and explores the topics of power integrity analysis, power integrity analytics, silicon level power integrity, and optimization techniques.

Leseprobe

Table of Contents

Cover

Part I: Power Integrity Fundamentals

1 Introduction

1.1 Introduction to Power Integrity for Computer Engineers

1.2 Some Advancements in Power Integrity

1.3 First Principles Analysis

1.4 Scope of Text

Bibliography

2 Power Conversion for Power Integrity

2.1 Power Distribution Systems

2.2 The Buck Converter

2.3 Inductors

2.4 Controllers

2.5 Integration of Closed Loop Model into SPICE

2.6 Short Discussion on System Considerations for Power Conversion Integration

2.7 Advanced Topics in Power Conversion

2.8 Summary

Bibliography

3 Platform Technologies and System Considerations

3.1 Physical Elements

3.2 Power Delivery System Interaction

3.3 System Noise Considerations in Power Integrity

3.4 EMI and Power Integrity

3.5 Brief Discussion on Noise Mitigation for Power Integrity

3.6 Summary

Bibliography

4 Electromagnetic Concepts for Power Integrity

4.1 Coordinate Systems

4.2 EM Concepts – Maxwell's Equations

4.3 Some Useful Closed‐Form Equations

4.4 Examples of Using Equations

4.5 Summary

Bibliography

Part II: Tools for Power Integrity Analysis

5 Transmission Line Theory and Application

5.1 Telegrapher's Equations

5.2 Frequency‐Domain Analysis Fundamentals

5.3 Power Planes, Grids, and Transmission Lines

5.4 Summary

Bibliography

6 Signal Analysis Review

6.1 Linear, Time‐Invariant Systems

6.2 The Dirac Delta Function

6.3 Convolution

6.4 Fourier Series

6.5 Fourier Transform

6.6 Laplace Transform

6.7 Summary

Bibliography

7 Numerical Methods for Power Integrity

7.1 Introduction to Analytical Methods

7.2 Numerical Methods

7.3 Error and Convergence

7.4 Summary

Bibliography

Part III: Power Integrity Analytics

8 Frequency‐Domain Analysis

8.1 Introduction to FDA

8.2 The PDN Structure, Physically and Electrically

8.3 Analytical Methods

8.4 Excitation in PDN Systems

8.5 PDN Optimization

8.6 Power Loss in PDN Systems

8.7 Summary

Bibliography

9 Time‐Domain Analysis

9.1 Introduction to TDA

9.2 Voltage Droop Definitions

9.3 Droop Behavior and Dynamic Loads

9.4 Analytical Approach to Step Response

9.5 Boundary Budget System Discussion

9.6 Power Loss Due to the PDN

9.7 Summary

Bibliography

10 Silicon Power Integrity

10.1 Introduction

10.2 Device Construction and Architecture Considerations

10.3 On‐die Decoupling

10.4 Device Metal Routing Revisited

10.5 The Localized Impedance Network

10.6 Multi‐rail vs. Single Rail Power Discussion

10.7 On‐die Gating

10.8 Discussion of System‐Level Issues with Charge and Current Density

10.9 Noise

10.10 Summary

Bibliography

Appendices

A.1 Introduction to SPICE

B.1 Quasi‐Static Fields

C.1 Spherical Coordinate System

D.1 Vector Identities and Formula

E.1 Summary of Common Relationships Among Coordinate Systems

F.1 Some Notation Definitions

G.1 Common Theorems

Bibliography

Index

End User License Agreement

List of Tables

Chapter 1

Table 1.1 Dimensions for example FPA in Figure 1.7.

Table 1.2 Dimensions for example FPA in Figure 1.7 to be used in Problem 1.3.

Chapter 2

Table 2.1 Table of converter efficiencies for Figure 2.4.

Table 2.2 Table of converter efficiencies for Figure 2.4.

Table 2.3 Parameters for computation of on‐resistance.

Table 2.4 Inductor parameters for loss calculation.

Table 2.5 Parameters for controller design.

Table 2.6 Data for efficiency plot.

Table 2.7 Parameters for computation of on‐resistance.

Table 2.8 Parameters for computation of AC losses in NMOS.

Table 2.9 Parameters for computation of AC losses in PMOS.

Chapter 3

Table 3.1 Typical capacitor limits for some common MLCC devices.

Table 3.2 Sources of ToB errors.

Table 3.3 Load line and voltage guardband comparisons.

Table 3.4 FCC class limits class A and B at 50 MHz.

Table 3.5 Typical PDN‐related issues causing potential EMI noise.

Chapter 4

Table 4.1 Dimensions for problem.

Table 4.2 Dimensions for wire above plane.

Table 4.3 Dimensions for Problem 4.8.

Table 4.4 Dimensions for Problem 4.9.

Table 4.5 Dimensions for Problem 4.10.

Table 4.6 Dimensions for Problem 4.11.

Chapter 5

Table 5.1 Values for coaxial calculation.

Chapter 6

Table 6.1 Summary of Fourier transform theorems

Table 6.2 Summary of Fourier transform pairs.

Table 6.3 Summary of Laplace transform theorems.

Table 6.4 Summary of Laplace transform pairs.

Chapter 7

Table 7.1 Values for plotting the voltage function in Eq. (7.35).

Table 7.2 Relative position of voltages.

Table 7.3 Comparison of closed form vs. FD analysis.

Chapter 8

Table 8.1 Values for transmission line computation of Example 8.1.

Table 8.2 Values for Bode plot of Example 8.3.

Table 8.3 Values for transmission line computation of Example 8.4.

Table 8.4 Values for Bode plot of Problem 8.2.

Chapter 9

Table 9.1 Parameters for step response.

Table 9.2 Parameters for load profile and guardband.

Table 9.3 Values for analytical step response in Example 9.3.

Table 9.4 Sources of power loss in PDN.

Table 9.5 Data for workload/current profile in Example 9.4.

Table 9.6 Parameters for power loss problem in Example 9.4.

Table 9.7 Part I computations.

Table 9.8 Part II computations.

Table 9.9 Geometries for resistance calculations.

Table 9.10 Simple plane resistance calculation.

Table 9.11 Plane resistance calculation for complex geometries.

Table 9.12 Values for analytical step response in Problem 9.5.

Table 9.13 Data for workload/current profile in Problem 9.6.

Table 9.14 Parameters for power loss problem in Problem 9.6.

Table 9.15 Geometries for resistance calculations.

Chapter 10

Table 10.1 Parameters for first analysis.

Table 10.2 Parameters for second analysis.

Table 10.3 Parameters for Example 10.2.

Table 10.4 Parameters for Example 10.4.

Table 10.5 Parameters for Example 10.5.

Table 10.6 Parameters for Problem 10.1.

Table 10.7 Parameters for Problem 10.4.

Table 10.8 Parameters for Problem 10.5.

List of Illustrations

Chapter 1

Figure 1.1 Basic components of power integrity.

Figure 1.2 Change in computing devices over years.

Figure 1.3 Transistor density vs. process node size.

Figure 1.4 Illustration of voltage rail proliferation.

Figure 1.5 Trends for microprocessor transistor count (▴) and average powe...

Figure 1.6 Trends in number of cores in microprocessors over time.

Figure 1.7 Simple board layout with power planes.

Figure 1.8 Accuracy diagram for first principles analysis.

Figure 1.9 New estimate of width for Figure 1.7.

Figure 1.10 Pictorial flowchart of accuracy improvements through simulatio...

Chapter 2

Figure 2.1 Distributed power delivery architecture.

Figure 2.2 Centralized power delivery system.

Figure 2.3 Input and outputs of converter.

Figure 2.4 Converter configuration for Example 2.1.

Figure 2.5 Example of linear regulator.

Figure 2.6 Buck regulator duty cycle operation.

Figure 2.7 Commutating cycle of buck regulator.

Figure 2.8 Simple LC filter of buck regulator.

Figure 2.9 Simple impedance plot for an LC filter.

Figure 2.10 LC filter with parasitics added.

Figure 2.11 Transfer function with parasitic values added.

Figure 2.12 Simple plot of

V

NODE

drive voltage waveform.

Figure 2.13 Spectral expansion for square‐wave signal.

Figure 2.14 Spectral components of square‐wave function.

Figure 2.15 Circuit in Figure 2.10 redrawn for

Q

.

Figure 2.16 Admittance equation (2.19) plotted as function of angular fr...

Figure 2.17 Bridge and driver for buck regulator.

Figure 2.18 PMOS device in bridge.

Figure 2.19 PMOS bridge operation.

Figure 2.20 NMOS operation waveforms.

Figure 2.21 Power loss in full switching cycle for bridge.

Figure 2.22 PMOS current waveform (top graph).

Figure 2.23 Simple cross‐section of N‐channel MOSFET device.

Figure 2.24 Physical structure of discrete power N‐channel MOSFET.

Figure 2.25 Cross‐section showing main RDS components.

Figure 2.26 Plot of

R

DS_ON

.

Figure 2.27 Graph of relative

R

DS

_

ON

values.

Figure 2.28 Simplified model for NMOS device.

Figure 2.29 General illustration of where key capacitances reside in NMOS....

Figure 2.30 Voltage/current relationship (simplified) for MOSFET.

Figure 2.31 Gate and drain waveforms.

Figure 2.32 Simple inductor representation.

Figure 2.33 Changes in magnetic flux density with gapping and not gapping ...

Figure 2.34 Hysteresis loop in

B

–

H

curve for magnetic core.

Figure 2.35 Simple model for inductor AC and DC losses.

Figure 2.36 Illustration of eddy currents flowing in magnetic material.

Figure 2.37 Eddy currents in block of magnetic material.

Figure 2.38 Core power loss as function of Δ

B

.

Figure 2.39 Elements which affect output voltage.

Figure 2.40 Illustration of VR bandwidth as function of impedance to load....

Figure 2.41 Feedback added to basic perturbation and control block.

Figure 2.42 Simple buck with feedback system.

Figure 2.43 Equivalent block diagram to converter model.

Figure 2.44 Model with key elements added.

Figure 2.45 Bode plot of uncompensated gain function.

Figure 2.46 Bode plot for compensated VR controller.

Figure 2.47 Initial model setup for SPICE.

Figure 2.48 Simulation output from open‐loop of circuit.

Figure 2.49 Circuit with comparator added.

Figure 2.50 PWM open‐loop drive signal and output voltage.

Figure 2.51 LTSPICE output ramp with square wave output over one cycle.

Figure 2.52 Output voltage plot from LTSPICE circuit with PWM driver.

Figure 2.53 Solution to gain function.

Figure 2.54 Full model with compensation network and PWM.

Figure 2.55 Time‐domain simulation of integrated model in LTSPICE.

Figure 2.56 Migration of motherboard voltage regulation to on‐package and ...

Figure 2.57 Coupled inductor without parasitics.

Figure 2.58 Coupled inductor with parasitics added.

Figure 2.59 Buck regulator in polar form.

Figure 2.60 Current waveforms for coupled system.

Figure 2.61 Magnetic dipole representation.

Figure 2.62 Magnetic slab with no applied magnetic field, random magnetic ...

Figure 2.63 Magnetic slab with dipoles aligned from applied magnetic field...

Figure 2.64 Block diagram with

K

(

s

) added.

Chapter 3

Figure 3.1 Simple electrical/physical representation of path from source t...

Figure 3.2 Current into block of metal with uniform current density.

Figure 3.3 Region showing skin depth of material.

Figure 3.4 Current density between two points in plane.

Figure 3.5 Plot of magnitude of current density for values of

z

.

Figure 3.6 Two copper planes in space.

Figure 3.7 Vias in planes with current flowing in each.

Figure 3.8 Plot of inductance as a function of separation between vias.

Figure 3.9 Currents through vias/planes and corresponding partial inductan...

Figure 3.10 Two parallel wires in space.

Figure 3.11 Two parallel planes.

Figure 3.12 MLCC construction.

Figure 3.13 Simple RLC model for a capacitor.

Figure 3.14 Normalized impedance (1 MHz) for an MLCC capacitor.

Figure 3.15 Example capacitance change as a function of temperature for X7...

Figure 3.16 Percent capacitance change example for Z5U device.

Figure 3.17 Polarization vector relationship to electric field in parallel...

Figure 3.18 Polarization of capacitor as a function of electric field.

Figure 3.19 Change in capacitance for two AC voltages (gray is 50 × smalle...

Figure 3.20 Clock to data relationship for logic signals in a functional u...

Figure 3.21

p‐State

voltage and frequency (normalized).

Figure 3.22 Idealized load line.

Figure 3.23 DC path from voltage regulator to load.

Figure 3.24 Load‐line differentiation with

p‐states

.

Figure 3.25 Graph of power and currents as a ratio of the lowest

p‐state

...

Figure 3.26 Tolerance band in load line.

Figure 3.27 Simple circuit representation of blocks in accumulation of ToB...

Figure 3.28 Voltage guardband stackup.

Figure 3.29 Current waveform for load.

Figure 3.30 Noise current generation in power path.

Figure 3.31 Differential and common‐mode currents.

Figure 3.32 HF noise and cap added to VR filter.

Figure 3.33 Illustration of conducted noise path in a chassis.

Figure 3.34 Example of radiated emissions measurement setup.

Figure 3.35 Electric dipole in spherical coordinates.

Chapter 4

Figure 4.1 Distribution from the source to the load.

Figure 4.2 Illustration of a vector

A

in Cartesian coordinates.

Figure 4.3 Cylindrical coordinate system.

Figure 4.4 Arc in

z

 = 0 plane.

Figure 4.5 Differential elements in

x–y

plane.

Figure 4.6 Spherical coordinate system.

Figure 4.7 Illustration of Ampere's law for a current‐carrying wire.

Figure 4.8 Example with solenoid.

Figure 4.9 Sphere in space with electric flux emanating radially.

Figure 4.10 Biot–Savart physical representation for differential current s...

Figure 4.11 Long wire in space.

Figure 4.12 Short wire in space.

Figure 4.13 Plane pair with uniform current density for inductance computa...

Figure 4.14 Two wires in space.

Figure 4.15 Flux in different regions.

Figure 4.16 Current density between two vias in a plane.

Figure 4.17 Wire above ground plane.

Figure 4.18 Capacitors on either side of a plane structure.

Figure 4.19 Trace above a plane.

Figure 4.20 Wire above ground plane.

Chapter 5

Figure 5.1 Two long, parallel conductors of arbitrary cross‐section compri...

Figure 5.2 Schematic representation of a segment of a transmission line wi...

Figure 5.3 Damped transmission line representation.

Figure 5.4 A depiction of a coaxial transmission line for use in Example 5...

Figure 5.5 Schematic representation with a load for analyzing transmission...

Figure 5.6 Schematic representation with a load for analyzing transmission...

Figure 5.7 Depiction of a voltage‐plane gridded for modeling. The grids ar...

Figure 5.8 Schematic representation of the plane pair depicted in Figure 5...

Chapter 6

Figure 6.1 A reduced circuit of the power transfer circuit. The load is sh...

Figure 6.2 Equivalent circuits for inductors and capacitors for evaluation...

Figure 6.3 Laplace‐transformed circuit for evaluation.

Chapter 7

Figure 7.1 Structure for determining voltage.

Figure 7.2

V

A

problem setup for Figure 7.1.

Figure 7.3

V

B

problem setup for Figure 7.1.

Figure 7.4 Grid positions for voltages in Figure 7.1.

Figure 7.5 Surface plot of voltage.

Figure 7.6 Graph of voltage at center of grid for values of

k

.

Figure 7.7 Brachistochrone problem setup.

Figure 7.8 Test function illustration for functional.

Figure 7.9 Differential path in arc length.

Figure 7.10 Plot of exact and approximate solutions.

Figure 7.11 Coaxial structure.

Figure 7.12 Transformation for conformal mapping.

Figure 7.13 Approximation of function for finite difference method.

Figure 7.14 Grid region for computation molecule.

Figure 7.15 Surface plot of voltage.

Figure 7.16 Node

V

(15,8) voltage as a function of iterations through loop....

Figure 7.17 Surface plot with 4× finer mesh.

Figure 7.18 Voltage for node position

V

(60,29) on grid.

Figure 7.19 Spatial region for parasitic analysis with FD method.

Figure 7.20 Surface plot of voltage for center conductor problem.

Figure 7.21 Simple grid of three triangles for mesh.

Figure 7.22 Single triangle element.

Figure 7.23 Separation of variables problem.

Chapter 8

Figure 8.1 Power distribution network example from the source to the load....

Figure 8.2 Impedance profile of damped transmission line.

Figure 8.3 Damped transmission line model.

Figure 8.4 Simplified damped transmission line.

Figure 8.5 Damped transmission line network.

Figure 8.6 Simple RLC circuit.

Figure 8.7 Plot of output voltage across capacitor.

Figure 8.8 VR portion with parasitics added.

Figure 8.9 Plots of VR circuits in PDN – with (darker impedance line) and ...

Figure 8.10 Changing capacitance of VR filter.

Figure 8.11 Frequency sweep with changing capacitance parasitics.

Figure 8.12 Addition of PCB capacitors to model.

Figure 8.13 PCB capacitance and capacitor parasitics added to PDN.

Figure 8.14 Capacitances with interconnect parasitics added.

Figure 8.15 Simple lumped model with package elements added.

Figure 8.16 Frequency sweep with VR, PCB, and package elements added.

Figure 8.17 Full PDN lumped model with silicon components.

Figure 8.18 SPICE simulation of full PDN with silicon parasitics.

Figure 8.19 Simplified VR impedance looking back from PDN.

Figure 8.20 Components of impedance plot in decibels.

Figure 8.21

Z

 log(

ω

) plotted in terms of frequency.

Figure 8.22 Impedance plots with series elements for PCB added.

Figure 8.23 Simple impedance network.

Figure 8.24 Impedance of

Z

41

.

Figure 8.25 Plot of

Z

41

.

Figure 8.26

Z

6

impedance profile showing SRF of capacitor.

Figure 8.27 Impedance plot (decibels) of

Z

61

.

Figure 8.28 Impedance of

Z

61

.

Figure 8.29 Plot of impedance for

Z

81

.

Figure 8.30 Impedance plots of

Z

81

with changing inductance in

Z

7

by f...

Figure 8.31 Simple load profile.

Figure 8.32 Load profile for example.

Figure 8.33 Pulse function over 6 μs.

Figure 8.34 FFT of pulse waveform.

Figure 8.35 Addition of two pulses at end of step response.

Figure 8.36 FFT with two additional pulses at end of step response.

Figure 8.37 Simple square wave load profile.

Figure 8.38 Spectral amplitudes of square wave load profile.

Figure 8.39 Spectral content of 50% duty cycle current wave.

Figure 8.40 Square wave with

n

 = 13 harmonics, 60% duty cycle.

Figure 8.41 60% duty cycle signal compiled from a Fourier series.

Figure 8.42 Envelope function with

f

 = 40 MHz and edge rate of

T

/4.

Figure 8.43 Envelope function with

f

 = 40 MHz and

tr

 = 

T

/40.

Figure 8.44 Plot of impedance

Z

21

.

Figure 8.45 Derivative of impedance function.

Figure 8.46 Plot of compensation function

Z

c

(

ω

).

Figure 8.47 Added networks for compensation.

Figure 8.48 Compensation function added to

Z

21

.

Figure 8.49 Basic circuit of PDN, AC analysis.

Figure 8.50 Single component Monte Carlo variation.

Figure 8.51 New impedance profile with all components varying.

Figure 8.52 Instantaneous vs. real power consumed.

Figure 8.53 Currents in each of capacitor networks.

Chapter 9

Figure 9.1 Example clock and data relationship with logic.

Figure 9.2 Droop event definitions.

Figure 9.3 Droop and

p‐state

association.

Figure 9.4 Simple

p‐state

process flow.

Figure 9.5 Voltage droop for two different

p‐states

.

Figure 9.6 Different load test examples.

Figure 9.7 Step response characteristic.

Figure 9.8 Second step response characteristics.

Figure 9.9 Figure for adding portion of PDN.

Figure 9.10 Droop with first step response.

Figure 9.11 Voltage droop in example with second step current.

Figure 9.12 First and second voltage droop step measured at load and outpu...

Figure 9.13 Addition of third step.

Figure 9.14 Impedance profile for PDN.

Figure 9.15 High‐frequency pulse pattern.

Figure 9.16 High‐frequency droop behavior.

Figure 9.17 Successive pulses after unload of step function.

Figure 9.18 Droop minima with HF current step and slow step.

Figure 9.19 Droop event from successive pulses after step response.

Figure 9.20 100 MHz droop from two pulses.

Figure 9.21 Minima after two pulses.

Figure 9.22 High‐frequency droop with four successive pulses.

Figure 9.23 High‐frequency droop with six successive pulses.

Figure 9.24 Power consumed due to worst case load line.

Figure 9.25 Step function and repetitive 1 MHz pulses.

Figure 9.26 10 MHz pulses after step function.

Figure 9.27 50 MHz pulses after step function.

Figure 9.28 Extension of duty cycles from Figure 9.27.

Figure 9.29 Guardband for

p‐state

.

Figure 9.30 Simple circuit for analytical modeling.

Figure 9.31 Details for model.

Figure 9.32 Two pulses represented by step functions.

Figure 9.33 Droop derived from analytical methods.

Figure 9.34 Droop with increase in inductance.

Figure 9.35 Typical boundary window for budget.

Figure 9.36 Droop event due to statistical variances in PDN.

Figure 9.37 Illustration of guardband shift due to larger ripple.

Figure 9.38 Nominal active current profile.

Figure 9.39 View of planes (without vias) for resistance estimate.

Figure 9.40 Detailed layout of power planes.

Figure 9.41 Mean free dimensions for planes.

Figure 9.42 Section of plane showing current envelope.

Figure 9.43 Angle between capacitor current and actual current relating to...

Chapter 10

Figure 10.1 Simple example SoC plan and bottom views (X marks main areas o...

Figure 10.2 Example cross‐section and stackup of metal layers in silicon d...

Figure 10.3 Illustration of signal routing to I/O on device on periphery (...

Figure 10.4 Cross‐section of package and silicon regions (expanded).

Figure 10.5 Processing of wafers up to SiO

2

.

Figure 10.6 Next steps in silicon manufacturing.

Figure 10.7 Simple diagram of processor flow.

Figure 10.8 Simple instruction process flow.

Figure 10.9 Example simple topography of core.

Figure 10.10 Relative current densities in a generic core processing unit....

Figure 10.11 Example current density on processor.

Figure 10.12 Cross‐section of die and package.

Figure 10.13 Schematic for local PDN distribution.

Figure 10.14 Simple circuit diagram of SPICE model.

Figure 10.15 Voltage droop for first case.

Figure 10.16 Voltage droop for second case.

Figure 10.17 Simple metal capacitance in a device.

Figure 10.18 Approximate relative capacitor densities (note log scale).

Figure 10.19 Circuit diagram for transistor capacitor.

Figure 10.20 Simple cross‐section of MOS capacitor.

Figure 10.21 Regions of operation for MOS capacitor.

Figure 10.22 Capacitance in accumulation region.

Figure 10.23 Functional block with decoupling capacitance interspersed.

Figure 10.24 Capacitance on‐die appearing as “rings” of capacitance due to...

Figure 10.25 Capacitance as function of time.

Figure 10.26 High‐frequency ringing due to capacitance going to zero.

Figure 10.27 Droop due to capacitance (maximum value) in circuit.

Figure 10.28 Simple circuit diagram for local PDN.

Figure 10.29 Equivalent Spice circuit for analysis.

Figure 10.30 AC sweep of impedance.

Figure 10.31 AC sweep increasing

C

1

by 2×.

Figure 10.32 Single vs. multi‐rail representation.

Figure 10.33 Simple illustration of power gate transistor instantiated in ...

Figure 10.34 Power gate with local inrush.

Figure 10.35 Effect of current flow into load region with power gates.

Figure 10.36 Illustration of region with added power gates.

Figure 10.37 Localized

di

/

dt

events coincident in different FUB's.

Figure 10.38 SPICE diagram for simulation.

Figure 10.39 Droop events with 40 ns separation.

Figure 10.40 Droop events with 30 ns separation.

Figure 10.41 Droop events with 20 ns separation.

Figure 10.42 Droop events with 10 ns separation.

Figure 10.43 Droop events with no separation.

Figure 10.44 Noise generation due to power source.

Figure 10.45 Added low impedance caps to create short loop paths near conv...

Appendices

Figure A.1 Typical voltage source symbol with parasitic elements for notat...

Figure A.2 (a) Voltage‐controlled voltage source and (b) voltage‐controlle...

Figure A.3 Passive component symbols: (a) resistor, (b) inductor, (c) capa...

Figure A.4 AC sweep for example circuit.

Figure A.5 Transient analysis example.

Figure C.1 Spherical coordinate system.

Guide

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Power Integrity for Electrical and Computer Engineers

J. Ted Dibene II

Watsonville CA, US

David Hockanson

Boulder CreekCA, US

Copyright

This edition first published 2020

© 2020 John Wiley & Sons, Inc.

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Library of Congress Cataloging‐in‐Publication Data

Names: DiBene, J. Ted., II (Joseph Ted), author. | Hockanson, David, author.

Title: Power integrity for electrical and computer engineers / J. Ted Dibene,

 II (Watsonville, CA, US), David Hockanson (Boulder Creek, CA, US).

Description: Hoboken, NJ : Wiley, 2020. | Includes bibliographical references

 and index. |

Identifiers: LCCN 2019014832 (print) | LCCN 2019020732 (ebook) | ISBN

 9781119263265 (Adobe PDF) | ISBN 9781119263296 (ePub) | ISBN 9781119263241

 (hardcover)

Subjects: LCSH: Electric power system stability. | Electric power

 systems–Quality control.

Classification: LCC TK1010 (ebook) | LCC TK1010 .D5355 2019 (print) | DDC

 621.319–dc23

LC record available at https://lccn.loc.gov/2019014832

Cover design by Wiley

Cover image: © Suchart Doyemah/EyeEm/Getty Images

Part IPower Integrity Fundamentals

1Introduction

1.1 Introduction to Power Integrity for Computer Engineers

Power integrity as a discipline has evolved over the past 25 years. Once thought of as just a branch of “Signal Integrity,” the area now encompasses many facets of the platform design for computers and other electronic devices and stands on its own as a distinct and necessary discipline. Even as little as 10 years ago, most technologists viewed the study of the power distribution network (PDN) and accompanying areas as simply a verification of the voltage budget of the delivered power to the device. Today, many companies dedicate entire groups with multiple engineers focusing on various aspects of power integrity as it relates to their product. Power integrity is quickly beginning to stand on its own, while conferences are now dedicating significant time and effort to advancing the state of the art.

Possibly the most important change in power integrity is the transition of the issues from being focused mainly on the motherboard to manifesting themselves within the package and silicon. As the complexity of the electrical behavior of the load has increased, so have the intricacies in solving the power delivery between the power source and the load. It is not by accident that this evolution has occurred, but by necessity. The urge to produce electronics with more capability than previous generations has led to these advancements. More performance within a device will invariably lead to higher bandwidth requirements. The consequence of this is that as the frequencies in the devices have increased, so has the rate of change in the current into and out of those devices. Moreover, as silicon processes have continued to shrink, so have the voltage margins required by the transistors to switch properly [1]. This evolutionary change will be discussed in some detail in Section 1.2.

Fundamentally, the study of power integrity has grown out of the need to understand more carefully three key elements: the power source, distribution network (or interconnect), and the load. The complexity of these components, however, has been governed by the requirements of the silicon as mentioned previously. The never‐ending drive to lower the power of the devices (both for battery‐ and non‐battery‐powered applications), along with performance, has forced the voltages in the silicon to decrease linearly over time, while, at the same time, the currents and rate of change of currents going into and out of these components have increased geometrically. However, this is only one of the factors leading to the expansion of the power‐integrity field. The other is that the physics of advanced silicon devices has imposed more stringent requirements on the power delivered to them. To ensure the integrity of the data propagating through the logic, and therefore, the transistors switching in the device, the voltage and currents must be maintained within very stringent limits at all times. To accommodate this, a highly tuned passive network of capacitors, along with the resistance and inductance of the interconnections, is composed of between the load and the power source. Power integrity engineers call this the PDN. Nevertheless, often, in high‐performance devices such as CPUs, this is not enough to ensure proper regulation, and the power supply itself must share in the burden in delivering a suitable voltage and current. Moreover, the effects of developing advanced PDNs and power converters encroach on the entire system design which requires power integrity engineers to often be well versed in many aspects of the platform outside the scope of their discipline.

It is true that engineers are in fact concerned with all aspects of power integrity; from large server systems with alternating current (AC) wall inputs to smaller devices, such as wearables, with small batteries delivering power to one or more pieces of silicon, power integrity is becoming a necessary part of the development process. However, the issues, whether in small or large platforms, are still the same. In many ways, the study of power integrity has allowed the advancement of these electronic devices where just a decade ago, their creation would not have been possible. As the requirements of power silicon progress, it is apparent that as these remarkable devices advance, the study of power integrity will surely evolve along with it.

Because of the changes that have occurred over the past years in the discipline of power integrity, it was evident to the authors that a more comprehensive treatment of the subject was required. Our intention was therefore to present material that would extend beyond many of the more common texts [2] and other books to help those in the field take further steps in their education on this subject. Since there are few texts that focus on the detailed aspects of silicon in the area of power integrity, it was decided that we emphasize this in a practical manner to broaden the field of study. Thus, the purpose was to create a book intended for engineers who are interested in increasing their knowledge in this field beyond an introductory treatment. Consequently, this book was written with a focus towards developing an intermediate text on the subject. As stated in the foreword, the student should already have an advanced undergraduate or beginning graduate level education in engineering. This will be required for the subject matter in many of the chapters since it is believed that the student has a relatively strong mathematics and physics foundation.

At the end of this chapter, we review in more detail the scope of the text to help guide the reader through the different aspects of the study. A quick overview of the contents though is warranted here. Part 1 of the text will form the basis for the other sections of the book. A treatment of power conversion for computer systems as well as the system aspects of a whole platform will give the reader a good description of the electronics and issues that influence the development of the PDN and its aspects. This will be evident in the discussion around signal and numerical analysis for power integrity in Part 2 where an emphasis on toolsets is presented. Much of the foundational math and analysis should already be familiar to the student from their prior engineering education here. These tools will then be used in a number of the examples and analyses later on in Part 3 when frequency‐ and time‐domain analytics are discussed. In addition, the student should be well versed in utilizing math programs and Simulation Program with Integrated Circuit Emphasis (SPICE). Though a review of the basics of SPICE is presented in the appendix, this is only to serve as a refresher since it is believed that the student will have a good foundation in both. The authors here have chosen Mathcad, MATLAB, and LTSPICE as their tools; other programs will suffice for the student should they not be obtainable or familiar with them. However, many of the examples and code will be made available in these tools should the student wish to use them.

In the following chapters of this text, we introduce “Power Integrity” from a brief historical perspective and then discuss some fundamental practices that are used throughout the book.

1.2 Some Advancements in Power Integrity

As discussed earlier, power integrity is, and has been, mainly focused around the three main components shown in Figure 1.1. When the voltages delivered to the loads were in the 1.8 V and greater regime, many power delivery problems were solved with basic layout and decoupling practices [3].

Figure 1.1 Basic components of power integrity.

This was due to a number of factors but mostly because the load currents and voltage margins were manageable with the given capacitor technology at the time and the design limitations of the circuit board. Moreover, many of the devices in a platform only required a single power supply rail and the real estate for the decoupling capacitors, along with the construction of low‐impedance planes, was less of a challenge than it has been in recent years. However, as voltages have decreased on high‐performance silicon, so has the complexity of the electrical network required to deliver power to them increased. Figure 1.2 shows a simple illustration of how things have changed to devices over the years. Many components, such as microprocessors, have stayed relatively constant in size, but their computational power has increased significantly during that time. This has been driven by the amazing advancements we have seen from silicon process manufacturing. However, the increase in computing performance has come about not only through increasing the speed of the device, but also, in part, through logic density. Today, many processors have billions of transistors, which contribute mightily to their processing capability. Figure 1.3 shows the relative increase in transistor density that has occurred relative to the process node size [7].

Figure 1.2 Change in computing devices over years.

Figure 1.3 Transistor density vs. process node size.

Additionally, advancements in computing power, in recent years, have been partially attributable to architectural changes. The advancement of the multi‐core processor also attributed to this evolution. A number of years ago, it was discovered that paralleling multiple processing units (called cores) and grouping them into a single silicon device offered more computing capability than if one were to simply build a single processing unit with that same area of silicon [6]. Additionally, it has been common practice in the computer industry for some time to take the previous generation of a computing core and add more of them to the space that was previously available in an earlier generation [4]. This, as already mentioned, has been achieved through silicon process scaling which has typically reduced the area for a given piece of silicon (for a similar density of logic) by approximately 1.4× every generation [5]. The final assembled device becomes a conglomeration of high‐performance computational devices that were based on this previous core architecture. This segmentation of components within a singular device has resulted in more voltage rail proliferation as well. However, this has also reduced the physical area available to deliver the power into the device. Shrinking the available space, while also decreasing the voltage to the device, and increasing the rate of change of current into the device have placed a very large burden on the power delivery to each processing block within the silicon. This evolution has required power integrity engineers to become more critical in their thinking when it has come to designing a proper power delivery network for such subsystems. Thus, power integrity engineers are now examining closely the aspects of on‐silicon power integrity, which has brought about a completely new field of study.

Figure 1.4 shows an illustration of how the change to continuously shrinking silicon devices has exacerbated the power delivery problem. If each unit shown in Figure 1.4 requires an individual voltage rail to power it, then it is clear that the proliferation of these additional power sources makes up for increased complexity. The first question one might ask is “Why not only use a single power source to all of the computing devices instead of trying to power each processing unit individually?” The answer to this question has to do with the competing trends to reduce or maintain the overall system power while increasing performance. To ensure that the power does not increase for the overall device from one generation to the next (or ensure the power decreases), it is often required to not only control the power to each computational block independently but also provide it with its own power source. For most software workloads, the time in which the work is sent to the processing unit is very indeterminate. That is, the processing units do not know exactly when software will require them to perform actual processing. To combat this problem, architects and engineers figured out that growing the number of processing units on a die and joining them via a common memory and data bus allowed them to select which processing unit or core does the actual processing and to find the one that was idle and available to perform the work [6]. This is partly the rationale behind the multiprocessor architecture. As long as the memory bus feeding the individual cores had sufficient bandwidth to fill the cores adequately, this architecture resulted in many advantages over a larger core utilizing the same space. However, if each processing unit is not active and sits waiting to perform work, due the silicon current leakage [8], particularly in sub‐nanometer processes, the additional power burned when the cores were not active could outweigh the benefit of the extra computing capability. To combat this problem, engineers determined that by either gating off these cores through large‐power metal‐oxide semiconductor field‐effect transistors (MOSFETs), called power gates [9], or through providing individual power sources to each core, they could control the voltage to each unit within the same silicon and reduce the effective leakage to very low values, thus improving the performance/watt for the overall system. Since most processors do actual work at only a small portion of the time when they are active, this reduces the effective power being consumed by the cores and processor over a given workload period to a much lower value than would otherwise be possible.

Figure 1.4 Illustration of voltage rail proliferation.

An example of how this architecture has come about is shown in Figure 1.5. Note that the increases in transistor count (log scale on the left axis) have grown steadily over the years shown. However, the average power consumption has changed over this time and has not scaled with transistor density. This is very evident in the graph in Figure 1.6. Note that from 2005 onward, a change occurred in the architecture of the microprocessor and the number of cores increased. This increase in cores demanded a change in the power consumed and one can see that the power in these devices tended to fluctuate from this time onward. The reason for this is evident once one examines the work that was put into managing power in these cores during this time. It is clear over this more recent generation of processors that power increases within the device forced engineers to become more creative in managing the power delivered to them [12]. It is also evident by examining the same figure that the processing unit has proliferated within the silicon device at a similar rate. However, note that the power consumption either has been capped over those years or has even gone down. This is due in part to the changes in architecture over this time in moving from a single processing unit to a multiprocessing unit. Not only has this change occurred within the microprocessor, but it has now made its way into other units such as graphics processors and SoCs. The ability to extend the capability of processing on silicon has helped fuel the increased processing capability of not just larger systems such as servers but also smaller devices such as laptops and handhelds.

Figure 1.5 Trends for microprocessor transistor count (▴) and average power (▪).

Figure 1.6 Trends in number of cores in microprocessors over time.

This change though has come with a price as shown in Figure 1.4. To manage power in individual components on silicon requires individual power management. This necessitates additional circuitry. As the silicon device shrinks, so must the components that circumscribe the device to power it. If not, then the system begins to grow outward as illustrated. Thus, the power source and distribution must begin to shrink with the device as well. Unfortunately, this facet of the design competes with the performance of the device as well. Even if the component shrinks, there will still be a requirement to boost its capability through frequency changes. This increases the current into the component, resulting in larger devices converting power for this component.

Over the next decade or more, the power integrity engineer will be faced with a number of growing challenges, many of which will be due to rapid increases in voltage proliferation driven by the advancements in process scaling and the need to control power consumption in a device. This will require them to be well versed in the fundamentals of power integrity and all its aspects. Section 1.3 discusses an important aspect to this education: first principles analysis (FPA).

1.3 First Principles Analysis

As discussed in Ref. [2], the aspects of FPA begin with the fundamentals and understanding of the boundary conditions of a problem. Too often engineers are tasked with a problem in which they require a reasonable answer within a short amount of time which requires them to not only be thorough but also give a reasonable answer to a problem. Unfortunately, most engineers forego the understanding and lean too heavily on the software tools to give them the answers they desire. This is where an iterative process of program data analysis forces the engineer into loop after loop of trying to come up with the correct answer based on the output of the tools. The software eventually gives them something that they frequently realize is erroneous or nonsensical, and consequently useless.

In such cases, this is where FPA becomes an integral part to one's analytical education. FPA is simply a variation of the scientific method. It is intended to help the engineer determine the best direction to take when tackling a problem. It also starts with an analysis that is solely based on a strong fundamental understanding of the problem. This requires that the engineer be well versed in the math and physics. In the fast‐paced world of electronics product development, technologists tend to fear not having an answer more than getting the answer wrong. This is unfortunate, given that a lack of understanding typically results in a delay or an unnecessary additional number of resources added to the problem. In virtually all of these cases, it is better to gain the understanding first, rather than rely on a computer program to tell one the answer in the beginning. This is not to say that numerical software tools do not have their place. Chapter 7 is dedicated to a discussion of numerical methods for power integrity problems and reviews their role with respect to analysis in some detail. The point is that before embarking upon a detailed numerical study, it is always better to acquire a baseline understanding of the problem first.

The method of FPA is discussed in some detail in chapter 1 of Ref. [2]. However, FPA can be shown just as well with an example. Suppose that an engineer is trying to come up with a value for the plane inductance from a power source (output inductor) to a group of capacitors underneath a device close to where the load is. Furthermore, the engineer is interested mainly in the low‐frequency effects (third‐order droop) rather than the high‐frequency droop effects. The plane structure (plan view) is illustrated in Figure 1.7. The engineer knows that if the inductance is too large, then more capacitance may be required to dampen the low‐frequency voltage droop in this region. However, if it is small enough, then no further analysis would be required, and the layout person may go ahead with the board design without issue. The key is that a quick value that is accurate enough to allow the design team to continue on with their work must be found.

Figure 1.7 Simple board layout with power planes.

As a starting point, the engineer knows from experience that the inductance must not exceed 800 pH. If it does, then additional capacitance or a lower inductance path may be required. The question is, how accurate does the estimate need to be in order to ensure that the result will satisfy the design requirements? The question may be partially answered in the chart in Figure 1.8. As a general rule, the accuracy of the computation depends upon the type of analysis being done. For example, if the accuracy only needs to be within 50% (in other words, an estimate may be off by 2× on the high side in this case where it will not matter), then a simple hand calculation will usually suffice. However, if the error can be no more than 5%, then only a very good experimental test would be adequate to ensure the accuracy. In most cases, the FPA assumes that an engineer will go through the proper steps prior to dedicating the resources necessary to solve a given problem. Thus, given the complexity of the issue, an engineer may approach the problem differently.

Figure 1.8 Accuracy diagram for first principles analysis.

Referring back to Figure 1.7, one can see that getting the proper dimensions first is required before embarking upon a study. Table 1.1 gives us some of the key measurements to allow us to proceed.

Table 1.1 Dimensions for example FPA in Figure 1.7.

Dimension

Value

Length (mm)

12

Width (mm)

 3

Thickness (μm)

25

The dimensions in the table are enough to estimate the inductance of the structure. However, before doing the computation, it is best to analyze the figure to ensure that a proper computation is done. First, notice that the dimension for the length is taken to the center of the circle where the load is rather than say where the first capacitors are located. If this were a high‐frequency analysis (relative to the load), it might be better to compute the inductance to the center of the first row of capacitors since the AC currents in a higher frequency regime would initially feed the capacitors rather than the load. This is an important distinction since often the problem statement dictates where the computation is bounded. Second, the dimensions for the width of the planes are to the outside of the planes, not to the actual current sources, which are actually from the inductors to the left. Figure 1.9 gives a better profile for the current distribution in both planes. Note that this estimated current profile better predicts the actual current distribution (or envelope) in the planes. Third, no account is given to the perforation of the planes themselves (vias). In a real design, the engineer would check to see if there were a sufficient number of vias to disrupt the flow of current through the planes.

Figure 1.9 New estimate of width for Figure 1.7.

Finally, the thickness of the board must be taken into account. Since there was no tolerance given with this value, it must be assumed that this is a nominal value for the thickness. Usually, the dielectric thickness can have a 20% variation. Thus, it may be good to assume that the inductance could be 20% larger (or smaller) due to manufacturing variations and thermal cycling.

Now we can begin to compute the inductance. Chapter 4 gives a simple first principles equation for the inductance of a plane. The equation itself must also have some assumptions in it. First, and foremost, is the accuracy. For this analysis, we ask, is the estimate valid? It turns out that the equation is valid for plane lengths and widths much larger than the separation between them. In other words

A quick calculation shows that this is a valid assumption. We are now ready to compute an estimate for the plane inductance.

It is clear that this is much less than 800 pH. The error is ±2× in this estimate (per Figure 1.8 as a general rule). Thus, the result is within the error band of the computation. Note also that the result is essentially two decimal places. Since the error is so large, reporting out a more accurate result would be incorrect. A simple dimensional analysis bears this out.

The next step would likely be for the power integrity engineer to perform a SPICE analysis to confirm that the droop was within reason (assuming this had not already been done). If the constraints of the problem were such that the inductance could not exceed say, 250 pH, then the engineer would have gone on to analyze the problem further since a hand calculation would not have been within the bounds of the error bar set for the problem (e.g. 400 pH = 2 × 200 pH > 250 pH). The diagram in Figure 1.8 is a simple guide to the next steps. As a general rule, given here are the tasks that one might follow in each circle to determine which analysis to perform,

50% accuracy

: Hand computation or simple spreadsheet computation.

75% accuracy

: First pass numerical analysis (parameter extraction and/or in combination with SPICE or math program computation).

85% accuracy

: Detailed numerical analysis over boundary or “corner” conditions along with (possibly) first pass test setup and measurement in lab.

95% accuracy

: Advanced lab measurement in controlled environment. Closely calibrated conditions and baseline data from previous measurements used as checks.

The described accuracies are depicted pictorially in Figure 1.10.

Figure 1.10 Pictorial flowchart of accuracy improvements through simulations, testing, and life cycle.

The power integrity engineer should in all cases determine what will be the next best step. Though it seems repetitious for some, doing a reasonable hand computation to gain some understanding of the problem first is usually a good idea. There are cases in which the problem itself at first seems intractable. This is where it is best to break the problem down into smaller items and address them one by one rather than attempt to solve the problem all at once. This is very true of complex power distribution problems, as we shall see later on in the text. Jumping into a detailed numerical analysis will invariably have its drawbacks. This is because if the engineer does not have a good idea of what the result would be, the time it takes to get the assumptions right in the model may outweigh the benefit of a good numerical tool. It will be evident later on in the text where having a good software program to gain accuracy is helpful and what to look out for with regard to accuracy and other issues with these tools.

1.4 Scope of Text

It is clear that Power Integrity as a discipline today requires a broader look into a number of areas. This is mainly due to the complexity that has come about over the years in the problems that many engineers must face. It was with that perspective that the authors decided to include areas where power integrity problems crossed over to other disciplines which are now required for a better understanding of the subject matter.