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- Herausgeber: John Wiley & Sons
- Kategorie: Wissenschaft und neue Technologien
- Sprache: Englisch
Using the load-pull method for RF and microwave power amplifier design This new book on RF power amplifier design, by industry expert Dr. John F. Sevic, provides comprehensive treatment of RF PA design using the load-pull method, the most widely used and successful method of design. Intended for the newcomer to load-pull, or the seasoned expert, the book presents a systematic method of generation of load-pull contour data, and matching network design, to rapidly produce a RF PA with first-pass success. The method is suitable from HF to millimeter-wave bands, discrete or integrated, and for high-power applications. Those engaged in design or fundamental research will find this book useful, as will the student new to RF and interested in PA design. The author presents a complete pedagogical methodology for RF PA design, starting with treatment of automated contour generation to identify optimum transistor performance with constant source power load-pull. Advanced methods of contour generation for simultaneous optimization of many variables, such as power, efficiency, and linearity are next presented. This is followed by treatment of optimum impedance identification using contour data to address specific objectives, such as optimum efficiency for a given linearity over a specific bandwidth. The final chapter presents a load-pull specific treatment of matching network design using load-pull contour data, applicable to both single-stage and multi-stage PA's. Both lumped and distributed matching network synthesis methods are described, with several worked matching network examples. Readers will see a description of a powerful and accessible method that spans multiple RF PA disciplines, including 5G base-station and mobile applications, as well as sat-com and military applications; load-pull with CAD systems is also included. They will review information presented through a practical, hands-on perspective. The book: * Helps engineers develop systematic, accurate, and repeatable approach to RF PA design * Provides in-depth coverage of using the load-pull method for first-pass design success * Offers 150 illustrations and six case studies for greater comprehension of topics
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Table of Contents
Cover
List of Figures
List of Tables
Acronyms, Abbreviations, and Notation
Preface
References
Note
Foreword
Biography
1 Historical Methods of RF Power Amplifier Design
1.1 The RF Power Amplifier
1.2 History of RF Power Amplifier Design Methods
1.3 The Load-Pull Method of RF Power Amplifier Design
1.4 Historical Limitations of the Load-Pull Method
1.5 Closing Remarks
References
2 Automated Impedance Synthesis
2.1 Methods of Automated Impedance Synthesis
2.2 Understanding Electromechanical Tuner Performance
2.3 Advanced Considerations in Impedance Synthesis
2.4 Closing Remarks
References
Notes
3 Load-Pull System Architecture and Verification
3.1 Load-Pull System Architecture
3.2 The DC Power Source
3.3 The Method of System Verification
3.4 Electromechanical Tuner Calibration
3.5 Closing Remarks
References
Notes
4 Load-Pull Data Acquisition and Contour Generation
4.1 Constant Source Power Load-Pull
4.2 Fixed-Parametric Load-Pull
4.3 Harmonic Load-Pull
4.4 Swept Load-Pull
4.5 Advanced Techniques of Data Acquisition
4.6 Closing Remarks
References
Notes
5 Optimum Impedance Identification
5.1 Physical Interpretation of the Optimum Impedance
5.2 The Optimum Impedance Trajectory
5.3 Graphical Extraction of the Optimum Impedance
5.4 Optimum Impedance Extraction from Load-Pull Contours
5.5 Closing Remarks
Notes
6 Matching Network Design with Load-Pull Data
6.1 Specification of Matching Network Performance
6.2 The Butterworth Impedance Matching Network
6.3 Physical Implementation of the Butterworth Matching Network
6.4 Supplemental Matching Network Responses
6.5 Matching Network Loss
6.6 Optimum Harmonic Termination Design
6.7 Closing Remarks
References
Notes
Index
End User License Agreement
List of Tables
Chapter 2
Table 2.1 Maximum PEP and RMS power ratings by tuner frequency and connector ...
Chapter 3
Table 3.1 Examples of
and resultant
for various applications [1].
List of Illustrations
Chapter 1
Figure 1.1 Contemporary microwave tuner spanning 2.5–50 GHz operating bandwi...
Figure 1.2 Contemporary microwave tuner spanning 600 MHz to 18.0 GHz operati...
Figure 1.3 Block diagram of a generic load-pull system illustrating key impe...
Chapter 2
Figure 2.1 Transverse section view of electromechanical tuner slab-line illu...
Figure 2.2 Typical probe used in the passive electromechanical tuner. Each s...
Figure 2.3 Reflection coefficient vector seen at tuner calibration reference...
Figure 2.4 Internal view of a modern electromechanical tuner with three carr...
Figure 2.5 Fundamental reference PA power capability normalized by expected ...
Figure 2.6 The fundamental feed-forward active-loop impedance synthesis arch...
Figure 2.7 The fundamental feed-back active-loop impedance synthesis archite...
Figure 2.8 Modern active-loop load-pull system capable of simultaneous funda...
Figure 2.9 The fundamental active-injection impedance synthesis architecture...
Figure 2.10 Fundamental reference PA power capability normalized by expected...
Figure 2.11 Fundamental reference PA power capability normalized by expected...
Figure 2.12 Modern high-performance vector network analyzer with four ports ...
Figure 2.13 Typical dual-carriage tuner
VSWR
response versus frequency, illu...
Figure 2.14 Phase response of tuner input impedance around its nominal cente...
Figure 2.15 Tuner available (heating) loss in dB versus the magnitude of the...
Figure 2.16 Configuration to evaluate maximum tuner RMS power capability for...
Figure 2.17 Graphical illustration of tuner vector repeatability.
Figure 2.18 Two-port representation of two carriage–probe pairs cascaded on ...
Figure 2.19 Fundamental and harmonic impedance vectors,
and
, respectivel...
Figure 2.20 Fundamental and harmonic impedance vectors,
and
, respectivel...
Figure 2.21 Gamma magnitude at the probe-tip reference versus tuner
for pr...
Chapter 3
Figure 3.1 Contemporary high-performance on-wafer load-pull system.
Figure 3.2 Generic load-pull system illustrating various functional blocks a...
Figure 3.3 Smith chart illustrating vector dependence of DUT source impedanc...
Figure 3.4 Apparent PAE versus total harmonic content with respect to fundam...
Figure 3.5 Voltage and current conventions that define the large-signal inpu...
Figure 3.6 Typical dynamic range curve for IM and ACPR measurements illustra...
Figure 3.7 Response to a two-tone stimulus illustrating a common definition ...
Figure 3.8 Load-pull system configuration to evaluate
.
Figure 3.9 Typical
response for a well-calibrated sub-1
high-power 2 GHz...
Chapter 4
Figure 4.1 Canonical load-pull system defining independent variables from wh...
Figure 4.2 Load power contours illustrating the maximum power impedance, con...
Figure 4.3 Three iterations of (a) load-pull and (b) source-pull contours il...
Figure 4.4 Transducer gain versus load power for each of the three load-pull...
Figure 4.5 Load power (solid contours) and PAE (dashed contours) contours il...
Figure 4.6 Three iterations of (a) load-pull and (b) source-pull contours fo...
Figure 4.7 Load power (solid contours), PAE (dashed contours), and ACPR (sol...
Figure 4.8 Two iterations of (a) load-pull and (b) source-pull contours for ...
Figure 4.9 Generic multistage PA line-up illustrating interstage matching ne...
Figure 4.10 Illustration of regions requiring special attention during fixed...
Figure 4.11 Contoursof load power, PAE, and peak–average ratio. Note the phe...
Figure 4.12 Illustration of multiple contour intersections and their interpr...
Figure 4.13 Common impedance state distribution for harmonic load-pull explo...
Figure 4.14
versus second harmonic phase for fixed available source power ...
Figure 4.15 Vector IM diagram illustrating how the baseband impedance influe...
Figure 4.16 Illustration of geometric-logical search method showing the boun...
Figure 4.17 Illustration of the synthetic geometric-logical search method sh...
Figure 4.18 Illustration of data-structure composed of three independent dim...
Figure 4.19 Illustration of data-structure composed of three independent dim...
Chapter 5
Figure 5.1 Three dimensional rendering of a CW optimum impedance trajectory ...
Figure 5.2 Graphical definition of the optimum impedance trajectory, illustr...
Figure 5.3 Illustration of graphical optimum impedance state extraction, sho...
Figure 5.4 Load-pull contours for a 10 W GaN device, at 1.9 GHz, illustratin...
Figure 5.5 Rectangular-coordinate plot of average load power versus PAE. The...
Figure 5.6 The optimal impedance trajectory of the 10 W GaN HEMT described b...
Figure 5.7 Illustration of the concept of orthogonal contourswhere one param...
Figure 5.8 Load-pull contours for a 38 dBm GSM-900 DUT illustrating its opti...
Figure 5.9 Load-pull contours for a 26 dBm WCDMA DUT illustrating its optimu...
Figure 5.10 Instantaneous transducer gain trajectories illustrating transduc...
Figure 5.11 Load-pull contours for a 26 dBm WCDMA DUT, under constant averag...
Figure 5.12 Expanded-scale graphical representation of high-band, mid-band, ...
Figure 5.13 Extension of Figure 5.12 to illustrate the effect of narrow-band...
Figure 5.14 Contours of constant average load power of 43 dBm for a 400 W PE...
Chapter 6
Figure 6.1 An
section matching network with overall impedance transformati...
Figure 6.2 Low-pass Butterworth
L
-section matching prototype.
Figure 6.3 The four canonical Butterworth
L
-section matching sections based ...
Figure 6.4 Impedance displacement loci for construction of a two-section But...
Figure 6.5 Physical implementation of the two-section low-pass Butterworth m...
Figure 6.6 Impedance loci of a single-section low-pass Butterworth matching ...
Figure 6.7 Physical implementation of the distributed-parameter matching net...
Figure 6.8 Physical implementation of the hybrid-parameter matching network ...
Figure 6.9 Impedance displacement loci for construction of a two-section low...
Figure 6.10 Impedance transformation loci of the first section of the hybrid...
Figure 6.11 Impedance transformation loci of the second section of the hybri...
Figure 6.12 Physical implementation of the hybrid-parametertwo-section low-p...
Figure 6.13 A single-section Hecken taper matching network.
Figure 6.14 A generic Hecken taper illustrating instantaneous impedance resp...
Figure 6.15 Hecken instantaneous characteristic impedance trajectory for Exa...
Figure 6.16 Hecken matching network input impedance spanning 800 MHz to 8 GH...
Figure 6.17 Effective PAE versus load matching network insertion loss.
Figure 6.18 Generalization of
L
-section to include series and shunt loss ele...
Figure 6.19 An optimally engineered drain-source voltage waveform, satisfyin...
Figure 6.20 Transistor load terminations at the fundamental and harmonics fo...
Guide
Cover
Table of Contents
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The Load-Pull Method of RF and Microwave Power Amplifier Design
John F. Sevic, Ph.D.
This edition first published 2020
© 2020 John Wiley & Sons, Inc.
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The right of John F. Sevic to be identified as the author of this work has been asserted in accordance with law.
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Library of Congress Cataloging-in-Publication Data
Names: Sevic, John F., author.
Title: The load-pull method of RF and microwave power amplifier design / John F. Sevic, Vice President of Millimeter-Wave Engineering, Maja Systems, Milpitas, CA.
Description: First edition. | Hoboken, NJ : John Wiley & Sons, Inc., 2020. | Includes index.
Identifiers: LCCN 2020009983 (print) | LCCN 2020009984 (ebook) | ISBN 9781118898178 (hardback) | ISBN 9781119078067 (adobe pdf) | ISBN 9781119078036 (epub)
Subjects: LCSH: Power amplifiers--Design and construction. | Amplifiers, Radio frequency--Design and construction. | Microwave amplifiers--Design and construction.
Classification: LCC TK7871.58.P6 S45 2020 (print) | LCC TK7871.58.P6 (ebook) | DDC 621.3841/2--dc23
LC record available at https://lccn.loc.gov/2020009983
LC ebook record available at https://lccn.loc.gov/2020009984
Cover Design: Wiley
Cover Image: © Elesey/Shutterstock
This book is dedicated to the next generation of load-pull experts: may your experiences be as enriching and rewarding.
List of Figures
Figure 1.1
Contemporary microwave tuner spanning 2.5–50 GHz operating bandwidth. Source: Reproduced with permission of Focus Microwaves, Inc.
Figure 1.2
Contemporary microwave tuner spanning 600 MHz to 18.0 GHz operating bandwidth. Source: Reproduced with permission of Maury Microwave, Inc.
Figure 1.3
Block diagram of a generic load-pull system illustrating key impedance definitions.
Figure 2.1
Transverse section view of electromechanical tuner slab-line illustrating probe placement and its displacement for synthesis of an arbitrary impedance. To first-order, probe displacement from the center conductor (along the
-axis) represents the magnitude of the reflection coefficient and its longitudinal displacement (along the
-axis) from an arbitrary reference-plane, usually the physical end of the tuner nearest the DUT, represents phase.
Figure 2.2
Typical probe used in the passive electromechanical tuner. Each square-grid represents 1 cm. Source: Reproduced with permission of Focus Microwaves, Inc.
Figure 2.3
Reflection coefficient vector seen at tuner calibration reference-plane illustrating relationship between probe displacement and carriage displacement and associated magnitude and phase.
Figure 2.4
Internal view of a modern electromechanical tuner with three carriages. A multi-probe tuner of this style is capable of independent fundamental and harmonic impedance synthesis, as well as frequency-agile dynamic pre-matching. Source: Reproduced with permission of Focus Microwaves, Inc.
Figure 2.5
Fundamental reference PA power capability normalized by expected DUT PEP capability versus required synthetic load impedance at DUT reference-plane for active-loop. The four trajectories illustrate 0–3 dB insertion loss, in 1 dB steps.
Figure 2.6
The fundamental feed-forward active-loop impedance synthesis architecture, due to Takayama, and often referred to as the split-signal method [1].
Figure 2.7
The fundamental feed-back active-loop impedance synthesis architecture.
Figure 2.8
Modern active-loop load-pull system capable of simultaneous fundamental, harmonic, and baseband characterization. Source: Reproduced with permission of Maury Microwave, Inc.
Figure 2.9
The fundamental active-injection impedance synthesis architecture.
Figure 2.10
Fundamental reference PA power capability normalized by expected DUT PEP capability versus required synthetic load impedance at DUT reference-plane for active injection. The nine trajectories illustrate passive pre-matching from 0.1 to 0.9, in 0.1 steps.
Figure 2.11
Fundamental reference PA power capability normalized by expected DUT PEP capability versus required synthetic reflection coefficient magnitude at DUT reference-plane for active-injection impedance synthesis. Insertion loss between the active-injection reference-plane and the DUT reference-plane is assumed to be 2.0 dB, with the initial trajectory set for 0 magnitude pre-match and each subsequent trajectory an increase of 0.1 up to 0.9. The reflection coefficient is normalized to 50
.
Figure 2.12
Modern high-performance vector network analyzer with four ports and time-domain capability. Source: Reproduced with permission of Keysight, Inc.
Figure 2.13
Typical dual-carriage tuner
VSWR
response versus frequency, illustrating operating bandwidth and crossover frequency, in this example being 4 GHz. The operating bandwidth is limited to approximately 9 GHz in this example, illustrated by the 15 : 1
at 10 GHz.
Figure 2.14
Phase response of tuner input impedance around its nominal center frequency illustrating phase nonlinearity representative of nonconstant group delay that induces IM and ACPR asymmetry. The dashed line is tangent to the approximately constant group delay region, which is a function of tuner
.
Figure 2.15
Tuner available (heating) loss in dB versus the magnitude of the reflection coefficient for the side facing the DUT.
Figure 2.16
Configuration to evaluate maximum tuner RMS power capability for a specified change in tuner impedance due to self-heating. Tuner impedance
refers to lowest impedance state of each tuner, as defined in Figure 2.3.
Figure 2.17
Graphical illustration of tuner vector repeatability.
Figure 2.18
Two-port representation of two carriage–probe pairs cascaded on a shared transmission-line, similar to the configuration illustrated by Figure 1.1.
Figure 2.19
Fundamental and harmonic impedance vectors,
and
, respectively, and the
vector sweeping out the constraint circle at
. The circle is shown several orders of magnitude larger than its typical radius to illustrate its location on
.
Figure 2.20
Fundamental and harmonic impedance vectors,
and
, respectively, and the
vector sweeping out the constraint circle at
. The circle is shown several orders of magnitude larger than its typical radius to illustrate its location on
. The dashed lines show the correspondence between the fundamental states on the interior of
and the second-harmonic states on the boundary of the Smith chart. This expansionary mapping process, due to frequency dispersion, is the basis of the multi-probe method of harmonic load-pull with electromechanical tuners.
Figure 2.21
Gamma magnitude at the probe-tip reference versus tuner
for probe insertion loss from 0 to 2.0 dB in 0.2 dB increments.
Figure 3.1
Contemporary high-performance on-wafer load-pull system. Source: Reproduced with permission of Maury Microwave, Inc.
Figure 3.2
Generic load-pull system illustrating various functional blocks and their location within the overall architecture.
Figure 3.3
Smith chart illustrating vector dependence of DUT source impedance on source tuner, the source block, and the source terminating impedance, composed of the signal source and possibly a reference PA.
Figure 3.4
Apparent PAE versus total harmonic content with respect to fundamental power parametrized to actual PAE to assess optimum low-pass filtering requirements.
Figure 3.5
Voltage and current conventions that define the large-signal input impedance of a transistor, at a specific frequency, usually the fundamental.
Figure 3.6
Typical dynamic range curve for IM and ACPR measurements illustrating noise-limited and linearity-limited boundaries. The region between these two boundaries establishes the dynamic range of IM and ACPR characterization.
Figure 3.7
Response to a two-tone stimulus illustrating a common definition of video bandwidth (VBW) when the tone spacing yields 2
of asymmetry in the third-order mixing products. Note that the lower sideband leads in phase and the upper sideband lags in phase with respect to the linear phase response shown. It is this fact that produces intermodulation asymmetry, as described by Sevic and Steer [4].
Figure 3.8
Load-pull system configuration to evaluate
.
Figure 3.9
Typical
response for a well-calibrated sub-1
high-power 2 GHz load-pull system with quarter-wave pre-matching [10].
Figure 4.1
Canonical load-pull system defining independent variables from which all measurement data are derived. DC conditions at the drain (collector) and gate (base) form the basis of DC power for efficiency calculations. For the present load-pull method that transistor output impedance and its available power need not be known nor defined.
Figure 4.2
Load power contours illustrating the maximum power impedance, contour closure, and the impedance-state grid for data acquisition. The large dashed concentric circle at the edge of the Smith chart boundary is the maximum
the tuner can develop while the partial dashed circle near the top of the Smith chart is the load stability circle at the load-pull frequency.
Figure 4.3
Three iterations of (a) load-pull and (b) source-pull contours illustrating convergence to maximum power and gain. The first iteration is based on Cripps estimate, shown as a square, also illustrating the impedance states did not resolve power and gain maxima, thus exhibiting open contours. Subsequent expansion of the impedance states for both load-pull and source-pull enabled power and gain maxima to be uniquely resolved.
Figure 4.4
Transducer gain versus load power for each of the three load-pull iterations of Figure 4.3. As convergence is achieved for optimum load and source impedance, both maximum power and gain increase.
Figure 4.5
Load power (solid contours) and PAE (dashed contours) contours illustrating the maximum power and PAE impedances, contour closure, and the impedance-state grid for data acquisition. The large dashed concentric circle at the edge of the Smith chart boundary is the maximum
the tuner can develop while the partial dashed circle near the top of the Smith chart is the load stability circle at the load-pull frequency. The X symbol illustrates a possible trade-off point for maximum PAE for a given power, at a fixed frequency.
Figure 4.6
Three iterations of (a) load-pull and (b) source-pull contours for load power and PAE illustrating convergence to maximum power, gain, and PAE. The first iteration is based on Cripps estimate, shown as a square, also illustrating the impedance states did not resolve power and gain maxima, thus exhibiting open contours. Subsequent expansion of the impedance states for both load-pull and source-pull enabled power, gain, and PAE maxima to be uniquely resolved. The X symbol illustrates a possible trade-off point for maximum PAE for a given power, at a fixed frequency.
Figure 4.7
Load power (solid contours), PAE (dashed contours), and ACPR (solid lines) contours illustrating the maximum power and PAE impedances, ACPR contours, contour closure, and the impedance-state grid for data acquisition. The large dashed concentric circle at the edge of the Smith chart boundary is the maximum
the tuner can develop while the partial dashed circle near the top of the Smith chart is the load stability circle at the load-pull frequency.
Figure 4.8
Two iterations of (a) load-pull and (b) source-pull contours for load power (solid contours), PAE (dashed contours), and signal quality (dotted contours) illustrating convergence to optimum simultaneous power, gain, PAE, and signal quality. The initial source-pull covers the entire Smith chart to quickly identify trends in optimum signal quality. Note from the first iteration that maximum transducer gain and maximum signal quality, e.g. minimum ACPR, are substantially displaced.
Figure 4.9
Generic multistage PA line-up illustrating interstage matching network and relevant impedance definitions.
Figure 4.10
Illustration of regions requiring special attention during fixed load power from another, with the gray annular ring representative of high available loss and the second gray region the location of relatively high impedances that can induce premature saturation and subsequently lower power capability.
Figure 4.11
Contours of load power, PAE, and peak–average ratio. Note the phenomena of multiple maxima, illustrating the need for fixed peak–average ratio load-pull to be preceded by fixed available source power load-pull to assist in identification of an appropriate load power and PAE stationary point to perform fixed peak–average ratio load-pull. The circular region in gray is identified as the region for fixed peak–average ratio since it encloses the load power and PAE stationary point and while providing a locally unique solution.
Figure 4.12
Illustration of multiple contour intersections and their interpretation.
Figure 4.13
Common impedance state distribution for harmonic load-pull exploring optimum PAE. A usual distribution would be 36 or 72 states, yielding a phase step of 10
or 5
, respectively. The
for harmonic load-pull will usually be the maximum
the tuner is capable of producing, as shown by the vector.
Figure 4.14
versus second harmonic phase for fixed available source power (dashed line) and fixed load power (solid line).
Figure 4.15
Vector IM diagram illustrating how the baseband impedance influences in-band linearity. Maximizing video bandwidth pushes out any resonances of the bias network that expands the length of the second-order IM vector, whereas optimization using baseband load-pull systematically seeks out an impedance antiparallel to the vector sum of the other two mixing product vectors. (a) Phase response deviation, (b) asymmetric intermodulation products, (c) upper IM vector diagram, and (d) lower IM vector diagram.
Figure 4.16
Illustration of geometric-logical search method showing the boundary where PAE and ACPR constraints are satisfied simultaneously for fixed load power and fixed frequency. The elliptical dashed lines are contours of constant
Q
, used later.
Figure 4.17
Illustration of the synthetic geometric-logical search method showing three regions where PAE and ACPR constraints are satisfied, representing low-band, mid-band, and high-band. The tolerance band for each parameter must generally be smaller than the geometric-logical search method to approximate a line versus region. A blow-up is shown in the circle to illustrate this, along with an approximate impedance trajectory.
Figure 4.18
Illustration of data-structure composed of three independent dimensions to illustrate a data slice for fixed available source power.
Figure 4.19
Illustration of data-structure composed of three independent dimensions to illustrate a data slice for fixed frequency.
Figure 5.1
Three dimensional rendering of a CW optimum impedance trajectory illustrating the line that is simultaneously maximum for each parameter. Note that any displacement off the optimum trajectory, represented by the sequence of impedance states on the surface, except in its optimal direction, yields a decrease in at least one of the parameters.
Figure 5.2
Graphical definition of the optimum impedance trajectory, illustrating its definition as the line everywhere orthogonal to the tangent points of adjacent contours connecting the two associated optima. The optimum impedance trajectory is the line composed of the set of optimum impedance states between the two contours, in the present example being load power and PAE.
Figure 5.3
Illustration of graphical optimum impedance state extraction, showing the tangent line at the point where two parametric contours are mutually tangent.
Figure 5.4
Load-pull contours for a 10 W GaN device, at 1.9 GHz, illustrating load power and PAE.
Figure 5.5
Rectangular-coordinate plot of average load power versus PAE. The underlying impedance states attached to the convex hull of the data represent of the optimum impedance trajectory between maximum load power and maximum PAE, with each state representing an optimum point that is simultaneously maximum load power and maximum PAE.
Figure 5.6
The optimal impedance trajectory of the 10 W GaN HEMT described by the load-pull contours of Figure 5.4. Note that this trajectory indeed describes the optimal trade-off in load power and PAE, is everywhere orthogonal to each contour, and terminates at maximum load power and PAE.
Figure 5.7
Illustration of the concept of orthogonal contours where one parameter is held approximately fixed and the other is allowed to vary.
Figure 5.8
Load-pull contours for a 38 dBm GSM-900 DUT illustrating its optimum impedance trajectory and the optimum impedance state at 36 dBm and 75% PAE.
Figure 5.9
Load-pull contours for a 26 dBm WCDMA DUT illustrating its optimum impedance trajectory and the optimum impedance state at 24 dBm and 44% PAE, with approximately
51 dBc ACPR1.
Figure 5.10
Instantaneous transducer gain trajectories illustrating transducer gain and gain compression displacement under constant available source power versus iteration of available source power to fix transducer gain and gain compression.
Figure 5.11
Load-pull contours for a 26 dBm WCDMA DUT, under constant average load power load-pull, illustrating its optimum impedance trajectory and the optimum impedance state at
50 dBc ACPR1 and 48% PAE. An increase of 1 dB in ACPR1 has yielded a substantial 4% point improvement in PAE, from 44% to 48%, while reducing the parameter space from three to two.
Figure 5.12
Expanded-scale graphical representation of high-band, mid-band, and low-band optimal impedance trajectories, with each square denoting the desired optimal impedance at its corresponding frequency. Over frequency, the consolidated collection of impedance states becomes the optimal impedance trajectory over frequency, to be replicated by the matching network. In practice, the collection of optimal impedance states resembles Figure 4.17.
Figure 5.13
Extension of Figure 5.12 to illustrate the effect of narrow-band frequency response using a constant-
circle of
. Note that the impedance states on the exterior of constant-
circle require proportionally higher matching network order or, identically, a change in transistor power capability or technology. The optimal impedance states fall within the capture range of a matching network constrained by the
circle, as illustrated.
Figure 5.14
Contours of constant average load power of 43 dBm for a 400 W PEP LDMOS transistor illustrating ACLR1 and PAE contours superimposed over
and
circles for bandwidth analysis.
Figure 6.1
An
section matching network with overall impedance transformation ratio
. The impedance transformation ratio of each section is
. For the Butterworth matching network,
of each section is identical, so that
.
Figure 6.2
Low-pass Butterworth
L
-section matching prototype.
Figure 6.3
The four canonical Butterworth
L
-section matching sections based on frequency response and transformation. The solid dot on the real axis is the geometric mean between
and
and represents the characteristic impedance of the quarter-wave line matching these two impedances.
Figure 6.4
Impedance displacement loci for construction of a two-section Butterworth distributed-parameter matching network with
. Note that impedances
and
are the geometric means of the impedance pairs
and
and
and
, respectively, and thus represent characteristic impedance of the quarter-wave lines matching these impedance pairs.
Figure 6.5
Physical implementation of the two-section low-pass Butterworth matching network matching 50 to 5
for Example 6.1.
Figure 6.6
Impedance loci of a single-section low-pass Butterworth matching network for ideal chip components (dashed line) and chip components with first-order parasitic resonance effects (solid-line). Note that for both inductance and capacitance, the effect of parasitic resonance is to increase the apparent reactance from nominal, causing overshoot of each loci from the intended target.
Figure 6.7
Physical implementation of the distributed-parameter matching network for Example 4.3 based on a two-section lumped-parameter
L
-section synthesis.
and
.
Figure 6.8
Physical implementation of the hybrid-parameter matching network illustrating the dot-array to solder copper tape for changing characteristic impedance and electrical length and top-metal via arrays for soldering chip capacitors an arbitrary electrical length equivalent to series inductance. The topology illustrated is electrically equivalent to the two-section lumped-parameter and distributed matching networks illustrated in Figures 6.5 and 6.7, respectively.
Figure 6.9
Impedance displacement loci for construction of a two-section low-pass Butterworth hybrid-parameter matching network physically implementing Figure 6.8 by distributed series inductance and lumped shunt capacitance.
Figure 6.10
Impedance transformation loci of the first section of the hybrid-parameter Butterworth matching network of Example 4.4. The reference impedance of the Smith chart is 10
.
Figure 6.11
Impedance transformation loci of the second section of the hybrid-parameter Butterworth matching network of Example 4.4. The reference impedance of the Smith chart is 50
.
Figure 6.12
Physical implementation of the hybrid-parameter two-section low-pass Butterworth matching network of Example 4.4.
Figure 6.13
A single-section Hecken taper matching network.
Figure 6.14
A generic Hecken taper illustrating instantaneous impedance response versus physical length.
Figure 6.15
Hecken instantaneous characteristic impedance trajectory for Example 6.6. The electrical length is at the nominal design frequency.
Figure 6.16
Hecken matching network input impedance spanning 800 MHz to 8 GHz for Example 7.6. The Smith chart reference impedance is 50
.
Figure 6.17
Effective PAE versus load matching network insertion loss.
Figure 6.18
Generalization of
L
-section to include series and shunt loss elements.
Figure 6.19
