Understanding Delta-Sigma Data Converters E-Book

Shanthi Pavan

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: IEEE Press Series on Microelectronic Systems
• Sprache: Englisch

Seitenzahl: 885

Veröffentlichungsjahr: 2016

Beschreibung

This new edition introduces operation and design techniques for Sigma-Delta converters in physical and conceptual terms, and includes chapters which explore developments in the field over the last decade * Includes information on MASH architectures, digital-to-analog converter (DAC) mismatch and mismatch shaping * Investigates new topics including continuous-time DeltaSigma analog-to-digital converters (ADCs) principles and designs, circuit design for both continuous-time and discrete-time DeltaSigma ADCs, decimation and interpolation filters, and incremental ADCs * Provides emphasis on practical design issues for industry professionals

Leseprobe

IEEE Press445 Hoes LanePiscataway, NJ 08854

IEEE Press Editorial BoardTariq Samad, Editor in Chief

George W. Arnold

Xiaoou Li

Ray Perez

Giancarlo Fortino

Vladimir Lumelsky

Linda Shafer

Dmitry Goldgof

Pui-In Mak

Zidong Wang

Ekram Hossain

Jeffrey Nanzer

MengChu Zhou

UNDERSTANDINGDELTA-SIGMA DATACONVERTERS

SECOND EDITION

SHANTHI PAVAN

RICHARD SCHREIER

GABOR C. TEMES

Copyright © 2017 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.Published simultaneously in Canada.

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ISBN: 978-1-119-25827-8

CONTENTS

Preface

1 The Magic of Delta-Sigma Modulation

1.1 The Need for Oversampling Converters

1.2 Nyquist and Oversampling Conversion by Example

1.3 Higher-Order Single-Stage Noise-Shaping Modulators

1.4 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators

1.5 Mismatch Shaping in Multi-Bit Delta-Sigma Modulators

1.6 Continuous-Time Delta-Sigma Modulation

1.7 Bandpass Delta-Sigma Modulators

1.8 Incremental Delta-Sigma Converters

1.9 Delta-Sigma Digital-to-Analog Converters

1.10 Decimation and Interpolation

1.11 Specifications and Figures of Merit

1.12 Early History, Performance, and Architectural Trends

References

2 Sampling, Oversampling, and Noise-Shaping

2.1 A Review of Sampling

2.2 Quantization

2.3 Quantization Noise Reduction by Oversampling

2.4 Noise-Shaping

2.5 Nonlinear Aspects of the First-Order Delta-Sigma Modulator

2.6 MOD1 with DC Excitation

2.7 Alternative Architectures: The Error-Feedback Structure

2.8 The Road Ahead

References

3 Second-Order Delta-Sigma Modulation

3.1 Simulation of MOD2

3.2 Nonlinear Effects in MOD2

3.3 Stability of MOD2

3.4 Alternative Second-Order Modulator Structures

3.5 Generalized Second-Order Structures

3.6 Conclusions

References

4 High-Order Delta-Sigma Modulators

4.1 Signal-Dependent Stability of Delta-Sigma Modulators

4.2 Improving MSA in High-Order Delta-Sigma Converters

4.3 Systematic NTF Design

4.4 Noise Transfer Functions with Optimally Spread Zeros

4.5 Fundamental Aspects of Noise Transfer Functions

4.6 High-Order Single-Bit Delta-Sigma Data Converters

4.7 Loop Filter Topologies for Discrete-Time Delta-Sigma Converters

4.8 State-Space Description of Delta-Sigma Loops

4.9 Conclusions

References

5 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators

5.1 Multi-Stage Modulators

5.2 Cascade (MASH) Modulators

5.3 Noise Leakage in Cascade Modulators

5.4 The Sturdy-MASH Architecture

5.5 Noise-Coupled Architectures

5.6 Cross-Coupled Architectures

5.7 Conclusions

References

6 Mismatch-Shaping

6.1 The Mismatch Problem

6.2 Random Selection and Rotation

6.3 Implementation of Rotation

6.4 Alternative Mismatch-Shaping Topologies

6.5 High-Order Mismatch-Shaping

6.6 Generalizations

6.7 Transition-Error Shaping

6.8 Conclusions

References

7 Circuit Design for Discrete-Time Delta-Sigma ADCs

7.1 SCMOD2: A Second-Order Switched-Capacitor ADC

7.2 High-Level Design

7.3 Switched-Capacitor Integrator

7.4 Capacitor Sizing

7.5 Initial Verification

7.6 Amplifier Design

7.7 Intermediate Verification

7.8 Switch Design

7.9 Comparator Design

7.10 Clocking

7.11 Full-System Verification

7.12 High-Order Modulators

7.13 Multi-Bit Quantization

7.14 Switch Design Revisited

7.15 Double Sampling

7.16 Gain-Boosting and Gain-Squaring

7.17 Split-Steering and Amplifier Stacking

7.18 Noise in Switched-Capacitor Circuits

7.19 Conclusions

References

8 Continuous-Time Delta-Sigma Modulation

8.1 CT-MOD1

8.2 STF of CT-MOD1

8.3 Second-Order Continuous-Time Delta-Sigma Modulation

8.4 High-Order Continuous-Time Delta-Sigma Modulators

8.5 Loop-Filter Topologies

8.6 Continuous-Time Delta-Sigma Modulators with Complex NTF Zeros

8.7 Modeling of Continuous-Time Delta-Sigma Modulators for Simulation

8.8 Dynamic-Range Scaling

8.9 Design Example

8.10 Conclusions

References

9 Nonidealities in Continuous-Time Delta-Sigma Modulators

9.1 Excess Loop Delay

9.2 Time-Constant Variations of the Loop Filter

9.3 Clock Jitter in Delta-Sigma Modulators

9.4 Addressing Clock Jitter in Continuous-Time Delta-Sigma Modulators

9.5 Mitigating Clock Jitter Using FIR Feedback

9.6 Comparator Metastability

9.7 Conclusions

References

10 Circuit Design for Continuous-Time Delta-Sigma Modulators

10.1 Integrators

10.2 The Miller-Compensated OTA-RC Integrator

10.3 The Feedforward-Compensated OTA-RC Integrator

10.4 Stability of Feedforward Amplifiers

10.5 Device Noise in Continuous-Time Delta-Sigma Modulators

10.6 ADC Design

10.7 Feedback DAC Design

10.8 Systematic Design Centering

10.9 Loop-Filter Nonlinearities in Continuous-Time Delta-Sigma Modulators

10.10 Case Study of a 16-Bit Audio Continuous-Time Delta-Sigma Modulator

10.11 Measurement Results

10.12 Summary

References

11 Bandpass and Quadrature Delta-Sigma Modulation

11.1 The Need for Bandpass Conversion

11.2 System Overview

11.3 Bandpass NTFs

11.4 Architectures for Bandpass Delta-Sigma Modulators

11.5 Bandpass Modulator Example

11.6 Quadrature Signals

11.7 Quadrature Modulation

11.8 Polyphase Signal Processing

11.9 Conclusions

References

12 Incremental Analog-to-Digital Converters

12.1 Motivation and Trade-Offs

12.2 Analysis and Design of Single-Stage IADCs

12.3 Digital Filter Design for Single-Stage IADCs

12.4 Multiple-Stage IADCs and Extended Counting ADCs

12.5 IADC Design Examples

12.6 Conclusions

References

13 Delta-Sigma DACs

13.1 System Architectures for Delta-Sigma DACs

13.2 Loop Configurations for Delta-Sigma DACs

13.3 Delta-Sigma DACs Using Multi-Bit Internal DACs

13.4 Interpolation Filtering for Delta-Sigma DACs

13.5 Analog Post-Filters for Delta-Sigma DACs

13.6 Conclusions

References

14 Interpolation and Decimation Filters

14.1 Interpolation Filtering

14.2 Example Interpolation Filter

14.3 Decimation Filtering

14.4 Example Decimation Filter

14.5 Halfband Filters

14.6 Decimation for Bandpass Delta-Sigma ADCs

14.7 Fractional Rate Conversion

14.8 Summary

References

A Spectral Estimation

A.1 Windowing

A.2 Scaling and Noise Bandwidth

A.3 Averaging

A.4 An Example

A.5 Mathematical Background

References

B The Delta-Sigma Toolbox

C Linear Periodically Time-Varying Systems

C.1 Linearity and Time (In)variance

C.2 Linear Time-Varying Systems

C.3 Linear Periodically Time-Varying (LPTV) Systems

C.4 LPTV Systems with Sampled Outputs

References

Index

IEEE PRESS SERIES ON MICROELECTRONIC SYSTEMS

EULA

List of Tables

Chapter 2

Table 2.1

Table 2.2

Chapter 4

Table 4.1

Table 4.2

Chapter 6

Table 6.1

Chapter 7

Table 7.1

Chapter 8

Table 8.1

Table 8.2

Table 8.3

Chapter 10

Table 10.1

Table 10.2

Chapter 11

Table 11.1

Chapter 14

Table 14.1

Table 14.2

Table 14.3

Table 14.4

Appendix A

Table A.1

Appendix C

Table C.1

Guide

Cover

Contents

Preface

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