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- Herausgeber: John Wiley & Sons
- Kategorie: Wissenschaft und neue Technologien
- Sprache: Englisch
75th Anniversary of the Transistor
75th anniversary commemorative volume reflecting the transistor's development since inception to current state of the art
75th Anniversary of the Transistor is a commemorative anniversary volume to celebrate the invention of the transistor. The anniversary volume was conceived by the IEEE Electron Devices Society (EDS) to provide comprehensive yet compact coverage of the historical perspectives underlying the invention of the transistor and its subsequent evolution into a multitude of integration and manufacturing technologies and applications.
The book reflects the transistor's development since inception to the current state of the art that continues to enable scaling to very large-scale integrated circuits of higher functionality and speed. The stages in this evolution covered are in chronological order to reflect historical developments.
Narratives and experiences are provided by a select number of venerated industry and academic leaders, and retired veterans, of the semiconductor industry. 75th Anniversary of the Transistor highlights:
- Historical perspectives of the state-of-the-art pre-solid-state-transistor world (pre-1947) leading to the invention of the transistor
- Invention of the bipolar junction transistor (BJT) and analytical formulations by Shockley (1948) and their impact on the semiconductor industry
- Large scale integration, Moore's Law (1965) and transistor scaling (1974), and MOS/LSI, including flash memories — SRAMs, DRAMs (1963), and the Toshiba NAND flash memory (1989)
- Image sensors (1986), including charge-coupled devices, and related microsensor applications
With comprehensive yet succinct and accessible coverage of one of the cornerstones of modern technology, 75th Anniversary of the Transistor is an essential reference for engineers, researchers, and undergraduate students looking for historical perspective from leaders in the field.
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Veröffentlichungsjahr: 2023
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Table of Contents
Cover
Series Page
Title Page
Copyright Page
About the Editors
About the Authors
Preface
Chapter 1: The First Quantum Electron Device
Reference
Chapter 2: IEEE Electron Devices Society
2.1 Introduction
2.2 Origins of EDS
2.3 Growth of EDS
2.4 Publications
2.5 Conferences
2.6 Awards and Recognition
2.7 Conclusion
References
Chapter 3: Did Sir J.C. Bose Anticipate the Existence of p‐ and n‐Type Semiconductors in His Coherer/Detector Experiments?
3.1 Introduction
3.2 J.C. Bose: A Brief Biography
3.3 Bose's Work on Detectors
3.4 Mott's Remark
3.5 Understanding Semiconductors and Doping
3.6 Interpretation of Mott's Remark
3.7 Conclusion
Acknowledgments
References
Chapter 4: The Point‐Contact Transistor
4.1 Introduction
4.2 Background and Motivation
4.3 Inventors’ Understanding How a Point‐Contact Transistor Operates
4.4 Recreating the Point‐Contact Transistor
4.5 Concluding Remarks
References
Chapter 5: On the Shockley Diode Equation and Analytic Models for Modern Bipolar Transistors
5.1 Introduction
5.2 Adaptation of Shockley Diode Equation to Modern Bipolar Transistors
5.3 Modern Bipolar Transistors Structures
5.4 Analytic Models for Modern Bipolar Transistors
5.5 Discussion
References
Chapter 6: Junction‐Less Field Effect Transistors
6.1 Introduction
6.2 Structure and Operation
6.3 Salient Features of JLFETs
6.4 Challenges for JLFETs
6.5 Unconventional Applications of JL Architecture
6.6 Conclusions
References
Chapter 7: The First MOSFET Design by J. Lilienfeld and its Long Journey to Implementation
7.1 Introduction
7.2 Demand for the Development of the Solid‐State Amplifier and Its Difficulty
7.3 Grid‐Inserted MESFETs
7.4 Lilienfeld Patents for the MESFET and MOSFET
7.5 Necessary Conditions for Successful MOSFET Operation, and MOSFET Development Chronology
7.6 Status of the Semiconductor Physics at the Lilienfeld Period (in the 1920s) and Thereafter
7.7 Improvement of Si and Ge Material Quality and Discovery of the pn Junction in the 1940s
7.8 H. Welker's MISFET with Inversion Channel in 1945
7.9 Shockley's Group Study for MOSFET from 1945 to 1947
7.10 Technology Development in the 1950s Until the First Successful MOSFET Operation in 1960
7.11 Success of MOSFET Operation by D. Kahng and M. Attala in 1960
7.12 After the First Successful Operation of the MOSFET
7.13 Summary and Conclusions
Acknowledgment
References
Chapter 8: The Invention of the Self‐Aligned Silicon Gate Process
References
Chapter 9: The Application of Ion Implantation to Device Fabrication
9.1 Introduction
9.2 Device Fabrication
9.3 Summary
Acknowledgments
References
Chapter 10: Evolution of the MOSFET
10.1 Introduction
10.2 The Early Days: Before 1980
10.3 From 1980 to 2000
10.4 The Latest: After 2000
10.5 Conclusion
References
Chapter 11: The SOI Transistor
11.1 The Beginnings
11.2 The Renaissance
11.3 The Smart‐Cut Dynasty
11.4 Special Mechanisms in FD‐SOI MOSFET
11.5 A Selection of Innovating Devices
11.6 The Future
References
Chapter 12: FinFET
12.1 The Show Stopper
12.2 The Cause of the Power Crises
12.3 The Real Cause of the Power Crises
12.4 A DARPA Request for Proposal
12.5 The Challenges and Team Work
12.6 Further Advancements by Industry
12.7 Conclusion
References
Chapter 13: Historical Perspective of the Development of the FinFET and Process Architecture
13.1 Introduction
13.2 Requirements for the End of CMOS Scaling
13.3 Restrictions of Planar Process Technology
13.4 Prompted Device/Process Technology Evolution by FinFET
13.5 Conclusion
References
Chapter 14: The Origin of the Tunnel FET
14.1 Background
14.2 Conception
14.3 Realization
14.4 Relevance
14.5 Prospects
References
Chapter 15: Floating‐Gate Memory
15.1 Introduction
15.2 The Charge‐Storage Concept
15.3 Early Device Structures
15.4 Multi‐Level Cells and 3D Structures
15.5 Applications
15.6 Scaling Challenges
15.7 Alternative Structures
15.8 Conclusion
Acknowledgments
References
Chapter 16: Development of ETOX NOR Flash Memory
16.1 Introduction
16.2 Background
16.3 Not the Perfect Solution
16.4 ETOX Development Challenges
16.5 Building a Business
16.6 Closing Words
Acknowledgments
References
Chapter 17: History of MOS Memory Evolution on DRAM and SRAM
17.1 Introduction
17.2 Revolutionary Technologies in DRAM History
17.3 Revolutionary Technologies in SRAM History
17.4 Summary
References
Chapter 18: Silicon‐Germanium Heterojunction Bipolar Transistors
18.1 Introduction (JDC)
1
18.2 Some History from Early Days at IBM Research (SSI)
18.3 SiGe Epitaxy and Making the First SiGe Transistor (SSI)
18.4 MBE vs. UHV/CVD vs. APCVD for SiGe epi (SSI)
18.5 Putting Physics to Work – The Properties of SiGe HBTs (JDC)
18.6 SiGe BiCMOS: Devices to Circuits to Systems (JDC and SSI)
18.7 Using SiGe in Extreme Environments (JDC)
18.8 New Directions (JDC and SSI)
18.9 Some Parting Words (SSI)
References
Chapter 19: The 25‐Year Disruptive Path of InP/GaAsSb Double Heterojunction Bipolar Transistors
19.1 Introduction
19.2 Phase I: Simon Fraser Years (1995–2006)
19.3 Phase II: ETH Years (2006–2022)
19.4 Response to Innovation
19.5 Final Words
References
Chapter 20: The High Electron Mobility Transistor
20.1 Introduction
20.2 HEMT Electronics
20.3 Modulation‐Doped Structures in Physics
20.4 Exciting Prospects
20.5 Conclusions
Acknowledgments
References
Chapter 21: The Thin Film Transistor and Emergence of Large Area, Flexible Electronics and Beyond
21.1 Birth of Large Area Electronics
21.2 Polycrystalline Silicon and Oxide Thin Film Transistor
21.3 Trends in TFT Development
Acknowledgments
References
Chapter 22: Imaging Inventions
22.1 Setting the Stage for the Invention of the Charge‐Coupled Device (CCD)
22.2 The Invention of the CCD
22.3 Verifying the CCD Concept
22.4 The Invention of CCD Imagers
22.5 The First Solid‐State Color TV Camera
22.6 Mixed Analog Design Modem Chip
Acknowledgement
References
Chapter 23: The Invention and Development of CMOS Image Sensors
23.1 Introduction
23.2 Underlying Technology
23.3 Early Solid‐State Image Sensors
23.4 Invention of CMOS Image Sensors
23.5 Photon‐Counting CMOS Image Sensors
23.6 Conclusion
Acknowledgments
References
Chapter 24: From Transistors to Microsensors
24.1 Early Encounters
24.2 Integration
24.3 Silicon Sensors
24.4 Transistor Sensors
24.5 CMOS End Fabrication
24.6 Outlook
Acknowledgments
References
Chapter 25: Creation of the Insulated Gate Bipolar Transistor
25.1 Introduction
25.2 Historical Context
25.3 The Brock Effect
25.4 My IGBT Proposal
25.5 The Welch Edict
25.6 Manufacturing the First IGBT Product
25.7 First IGBT Product Release
25.8 IGBT Technology Enhancement
25.9 IGBT Evolution
25.10 IGBT Applications
25.11 IGBT Social Impact
25.12 My Sentiments
References
Chapter 26: The History of Noise in Metal‐Oxide‐Semiconductor Field‐Effect Transistors
26.1 Introduction
26.2 MOSFET Noise Time Line
26.3 Channel Thermal Noise
26.4 Induced Gate and Substrate Current Noise
26.5 Gate–Drain Current Noise Cross Correlation
26.6 Equilibrium Noise
26.7 Bulk Charge Effects
26.8 Gate Resistance Noise
26.9 Substrate Resistance Noise
26.10 Substrate and Gate Current Noise
26.11 Short‐Channel Effects
26.12 Effect on Channel Thermal Noise
26.13 1/
f
Noise
26.14 Conclusions
Acknowledgments
References
Chapter 27: A Miraculously Reliable Transistor
27.1 Introduction: A Transistor is Born
27.2 Transistor Reliability in the Proto‐Scaling Era
27.3 Reliability of Geometric‐ and Equivalent‐Scaling Eras
27.4 Conclusions: Reliability Challenges for the Hyper‐Scaling and Functional‐Scaling Eras
References
Chapter 28: Technology Computer‐Aided Design
28.1 Introduction
28.2 Short History
28.3 Scaling and Model Complexity
28.4 MINIMOS Commercialization and Beyond
28.5 Design Technology Co‐Optimization at Advanced Nodes
28.6 Electron Spin for Microelectronics
28.7 Summary and Outlook
References
Chapter 29: Early Integrated Circuits
References
Chapter 30: A Path to the One‐Chip Mixed‐Signal SoC for Digital Video Systems
30.1 Introduction
30.2 Bipolar ADCs at Early Development Stage of Digital TVs
30.3 A CMOS ADC for Digital Handy Camcorder
30.4 One‐Chip Mixed‐Signal SoC for DVD
References
Chapter 31: Historical Perspective of the Nonvolatile Memory and Emerging Computing Paradigms
31.1 Introduction
31.2 Rise of Solid‐State Nonvolatile Memory
31.3 NVM in Classical Computer Architectures
31.4 NVM‐Driven New Computing Paradigm
31.5 Conclusion
References
Chapter 32: CMOS Enabling Quantum Computing
32.1 Why Cryogenic Electronics?
32.2 The Quantum Stack
32.3 Modeling Cryo‐CMOS Devices
32.4 Specific Effects in Cryo‐CMOS Transistors
32.5 Perspectives and Trends
References
Chapter 33: Materials and Interfaces
33.1 Introduction
33.2 Back‐End‐of‐Line
33.3 Channel Materials
33.4 Gate Stack
33.5 Contacts
33.6 Summary
References
Chapter 34: The Magic of MOSFET Manufacturing
34.1 Introduction
34.2 The Magic of MOS
34.3 The Magic of Self‐alignment
34.4 The Magic of Semiconductor Manufacturing
34.5 Transistor Magic for the NEXT 75 Years?
References
Chapter 35: Materials Innovation
35.1 Introduction
35.2 MOSFET Basics
35.3 Complementary MOS (CMOS) Technology
35.4 MOSFET Scaling Challenges
35.5 MOSFET Materials Innovations
35.6 Outlook for Continued Transistor Scaling
References
Chapter 36: Germanium
36.1 Introduction
36.2 Need for High Mobility Material for MOS Channel
36.3 Surface Passivation of Ge‐Based MOSFETs
36.4 Low Resistance Contacts to Ge
36.5 Heteroepitaxial Growth of Ge on Si
36.6 Strained Ge and Heterostructure FETs
36.7 Nanoscale Ge FETs
36.8 Ge NMOSFETs
36.9 Ge‐Based Novel Devices for Optical Interconnects
36.10 Summary
Acknowledgment
References
Index
End User License Agreement
List of Tables
Chapter 3
Table 3.1 Important milestones in semiconductor research.
Table 3.2 Comparison between coherer and current metal–semiconductor diode....
Chapter 7
Table 7.1 Timeline for the FET development and related theories and technolo...
Chapter 21
Table 21.1 Examples of applications of oxide TFTs.
Chapter 31
Table 31.1 Performance comparison among different NVMs.
Chapter 34
Table 34.1 Dennard scaling.
Chapter 36
Table 36.1 Properties of bulk, undoped Si, Ge, InAs, and GaSb at room temper...
List of Illustrations
Chapter 2
Figure 2.1 Origins of the IEEE EDS on 5 March 1952 as the IRE PGED. And, thr...
Chapter 3
Figure 3.1 Prof. Bose along with his experimental setup at the Friday evenin...
Figure 3.2 View of the spiral spring receiver developed by Bose.
Figure 3.3 Photograph of the Galena detector.
Figure 3.4 I–V characteristics of self‐recovering positive and negative cohe...
Figure 3.5 I–V curves of the replica of Bose detector (solid line in red) an...
Chapter 4
Figure 4.1 (a) Type A point‐contact transistor. (b) Leads and housi...
Figure 4.2 Bardeen and Brattain's explanation of the formation of a p‐type i...
Figure 4.3 Illustration of an active‐mode point‐contact transistor with a po...
Figure 4.4 IC vs. IE plot comparing the alpha gain characteristics between f...
Figure 4.5 Collage of various point‐contact transistor setups we attempted: ...
Figure 4.6 Forward‐bias diode curves between different top‐side contact type...
Figure 4.7 IC vs. IE between two 50 μm × 50 μm pads of various separations o...
Figure 4.8 Left: IC vs. IE plot of Bardeen and Brattain's first published po...
Figure 4.9 Common‐base transistor curves for comparing a Type A point‐contac...
Chapter 5
Figure 5.1 Schematics illustrating the applied voltages in normal operation ...
Figure 5.2 (a) Schematic of a modern vertical n–p–n bipolar transistor struc...
Figure 5.3 Schematic illustrating the approximately linear dependence of IC ...
Chapter 6
Figure 6.1 The device proposed by Lilienfeld to modulate current between two...
Figure 6.2 The structure of a n‐type double‐gate junction‐less FET....
Figure 6.3 Majority carrier (electron) concentration for different modes of ...
Figure 6.4 Electric field profile for different modes of operation of a JLFE...
Figure 6.5 Energy band profiles of a JLFET in (a) ON‐state and (b) OFF‐state...
Figure 6.6 Lateral electric field profile of the JLFETs and the MOSFETs.
Figure 6.7 Transfer characteristics of the JLFETs and the MOSFETs.
Figure 6.8 Unconventional application of junction‐less architecture: (a) JL‐...
Chapter 7
Figure 7.1 Triode vacuum tube invented by Lee de Forest.
Figure 7.2 Difficulty in controlling current by grid potential inserted in t...
Figure 7.3 Solid‐state amplifier ideas using semiconductor: (a, b) MESFETs, ...
Figure 7.4 Ideas of grid‐inserted type of solid‐state amplifiers (MESFETs): ...
Figure 7.5 First record of signal amplification by a solid‐state device (MES...
Figure 7.6 First idea of solid‐state amplifier (MESFET) proposed by J. Lilie...
Figure 7.7 Schematic structure and operation of the Lilienfeld's MESFET.
Figure 7.8 First idea of MISFET/MOSFET proposed by J. Lilienfeld in 1928....
Figure 7.9 Schematic structure and operation of the Lilienfeld's MOSFET.
Figure 7.10 Thin‐film MISFET idea by Oskar Heil in 1934.
Figure 7.11 The five necessary conditions for bulk MOSFETs.
Figure 7.12 The pn junction discovered by R. Ohl in 1940.
Figure 7.13 MISFET proposed by H. Welker in April 1945. Based on the descrip...
Figure 7.14 MISFET proposed by W. Shockley in April 1945. N‐channel FET case...
Figure 7.15 Electric field shielding by trapped electrons at surface states.
Figure 7.16 J. Bardeen's vertical‐type MISFET using electrolyte (distilled w...
Figure 7.17 Junction transistor mechanism: (a) Point‐contact transistor (PCT...
Figure 7.18 MOSFET experiment with SiO2 gate insulator conducted by W. Shock...
Figure 7.19 Idea of junction FET (JFET) proposed by W. Shockley 1952.
Figure 7.20 Concept of inversion layer connected to source/drain with pn jun...
Figure 7.21 Practical MOSFET structure except the gate insulator (ferroelect...
Figure 7.22 The structure of the first successful MOSFETs by D. Kahng and M....
Chapter 8
Figure 8.1 My lab notebook entry describing the steps taken to produce the f...
Figure 8.2 Photo of the three co‐patentees (from left to right), Robert E. K...
Chapter 9
Figure 9.1 Bell Labs, 1968 ion implantation system high voltage end.
Figure 9.2 Bell Labs, 1968 ion implantation system target end.
Chapter 10
Figure 10.1 Trends in lithographic feature size, number of transistors per c...
Figure 10.2 (a) Top: Source–drain region formation with a blocking mask. Bot...
Figure 10.3 Schematic cross‐section of CMOS, consisting of nMOS in p‐well an...
Figure 10.4 Band diagram at threshold of a buried channel pMOS with n+ poly ...
Figure 10.5 Self‐aligned silicide process.
Figure 10.6 Shallow trench isolation process.
Figure 10.7 Trends of power‐supply voltage, threshold voltage, and gate oxid...
Figure 10.8 Lightly doped drain (LDD) process. Top: medium‐dose source–drain...
Figure 10.9 Schematic MOSFET cross section showing Wdm, the depletion depth ...
Figure 10.10 Vertically nonuniform doping profiles: high‐low for MOSFETs lon...
Figure 10.11 HALO: laterally nonuniform doping for mitigating SCE.
Figure 10.12 Measured (dots) and calculated (solid lines) tunneling currents...
Figure 10.13 Replacement gate process.
Figure 10.14 FinFET cross section along a cut perpendicular to the channel b...
Figure 10.15 (a) Cross section of a single‐level metal/contact with no plana...
Chapter 11
Figure 11.1 (a) SOS structure with the defective interfacial layer to be hea...
Figure 11.2 SIMOX variants: (a) regular structure, (b) ITOX with thin film a...
Figure 11.3 Other flavors of SOI wafers: (a) wafer bonding (arrow) and etch‐...
Figure 11.4 Principal steps in the fabrication of SOI wafer by Smart‐Cut....
Figure 11.5 60 years of SOI already.
Figure 11.6 Schematics of (a) N‐channel FD‐SOI MOSFET with ground plane and ...
Figure 11.7 (a) Transfer characteristics illustrating the benefit of thresho...
Figure 11.8 Electron and hole currents versus gate voltage monitored in an u...
Figure 11.9 Persistent floating‐body effects in thin FD‐SOI MOSFETs. (a) Kin...
Figure 11.10 (a) Genuine junctionless transistor on FD‐SOI. (b) Double‐gated...
Figure 11.11 (a) Floating‐body A2RAM memory cell and (b) corresponding trans...
Figure 11.12 Experimental I–V characteristics of an electrostatic diode fabr...
Figure 11.13 Experimental I–V characteristics of TFET and Z2‐FET emulated in...
Figure 11.14 (a) Band‐modulation transistor on FD‐SOI, (b) band configuratio...
Chapter 12
Figure 12.1 Dire projection of CPU chip power consumption.
Figure 12.2 (a) Illustration of the exponential rise of Ioff with decreasing...
Figure 12.3 The correct capacitor network for understanding the short‐channe...
Figure 12.4 Three ways to build thin‐body transistors. (a) Is ultrathin‐body...
Figure 12.5 Photos of researchers. Digh Hisamoto is second from right in the...
Figure 12.6 45 nm gate‐length FinFET with 2.7 nm SiO2 gate oxide, 66 mV/deca...
Figure 12.7 30 nm UTB‐SOI (FDSOI) leakage was suppressed with 3 nm thin body...
Figure 12.8 Each nm reduction of the body thickness reduces the leakage curr...
Figure 12.9 Snapshot of a 2017 NVDIA webpage titled AI Solutions. The latest...
Figure 12.10 FinFET becomes GAA (gate‐all‐around or nano‐sheet)....
Figure 12.11 Nanometer thick 2D semiconductors may be excellent thin‐body ma...
Chapter 13
Figure 13.1 Impurity fluctuation images in scaled MOSFET according to Keyes ...
Figure 13.2 Around 1990, we established a roadmap for CMOS device technology...
Figure 13.3 MOSFET evolution trends and their mask layout design and gate fa...
Figure 13.4 Simulated 3D device structure. In order to reduce the number of ...
Chapter 14
Figure 14.1 The original band diagram from the Esaki tunnel diode paper.
Figure 14.2 The Tunnel FET structure from [6]. The heavily doped p and n reg...
Figure 14.3 Band diagram for the p+−p−n+ Tunnel FET structure in Figure 14.2...
Figure 14.4 Simulation of the output characteristics of the Tunnel FET struc...
Figure 14.5 The measured output and gate transfer characteristics from exper...
Figure 14.6 The Tunnel FET structure commonly used at present, The tunnel...
Chapter 15
Figure 15.1 Cross‐sectional view of the first floating‐gate memory structure...
Figure 15.2 Energy band diagrams of a floating‐gate memory with a semiconduc...
Figure 15.3 First demonstration of an electrically erasable programmable rea...
Figure 15.4 Current–voltage curves of a floating‐gate memory structure when ...
Figure 15.5 Energy band diagrams of a charge‐trapping memory which is a limi...
Figure 15.6 Two early floating‐gate memories: (a) FAMOS [9] and (b) SAMOS....
Figure 15.7 Flash memory proposed in 1984. In the erase operation, a whole b...
Figure 15.8 Market share of three nonvolatile‐semiconductor‐memory products ...
Figure 15.9 Voltage distributions for (a) single‐level cell with 1 bit cell−...
Figure 15.10 An example of a 16‐chip 3‐dimensional structure: a multi‐chip s...
Figure 15.11 Cross‐sectional view of 3D floating‐gate NAND Flash memory bloc...
Figure 15.12 Microphotograph of a 1.33 Tb 4 bit cell−1 3D floating‐gate NAND...
Figure 15.13 Cost per gigabyte (GB) of hard disk drive (HDD) and NAND Flash ...
Figure 15.14 Reduction of half pitch for 2D and 3D NVSM from 1995 to 2022 an...
Figure 15.15 The Unified Memory having high speed, high density, and nonvola...
Chapter 16
Figure 16.1 SEM micrographs of 10 generations of ETOX NOR flash memory. Cell...
Chapter 17
Figure 17.1 Array of one‐device memory cells as shown in the original refere...
Figure 17.2 Various kinds of planar cell structures. (a) Simple planar cell....
Figure 17.3 Cross‐sectional structure of stacked capacitor DRAM cell and US ...
Figure 17.4 SEM cross section of stacked capacitor cell fabricated using 3 μ...
Figure 17.5 Oxidation time dependence of leakage current flowing through ON ...
Figure 17.6 Leakage current‐applied electric field characteristics of poly‐S...
Figure 17.7 Dependence of soft‐error rate on cycle time in 16 kbit DRAM chip...
Figure 17.8 Cross‐sectional structure for three kinds of stacked capacitor (...
Figure 17.9 SEM cross section of COB‐STC cell for 4 Mbit DRAM.
Figure 17.10 Cross‐sectional structure of trench capacitor DRAM cell. (a) Cr...
Figure 17.11 Cross‐sectional structure of the first trench capacitor DRAM ce...
Figure 17.12 Cross‐sectional structure of trench capacitor DRAM cell used in...
Figure 17.13 Soft‐error rates of planar and trench cells.
Figure 17.14 Open‐BL architecture.
Figure 17.15 Folded‐BL architecture.
Figure 17.16 Read out methods in high‐throughput DRAM. (a) EDO (asynchronous...
Figure 17.17 Revolution of DRAM memory cell.
Figure 17.18 Revolution of stacked capacitor cell.
Figure 17.19 Pillar‐type stacked capacitor cell with vertical switching tran...
Figure 17.20 SEM cross section of 3D‐DRAM test chip with 10 memory layers fa...
Figure 17.21 Various kinds of SRAM memory cells. (a) Depletion‐MOS load type...
Figure 17.22 Address decoder circuit with pre‐decoding method. (a) Basic dec...
Figure 17.23 Bit‐line pre‐charge and equalizing circuit.
Figure 17.24 Bit‐line variable impedance circuit.
Figure 17.25 WLUD, NBL, and TVC assist circuit implementation.
Figure 17.26 Read assist (RA) circuit and write assist (WA) circuit. (a) RA ...
Figure 17.27 Memory cell circuit of 8T cell.
Figure 17.28 Memory cell circuit of 10T cell.
Figure 17.29 Memory cell circuit of 2‐read/write (2RW) DP‐SRAM....
Figure 17.30 Block diagram and waveform of pseudo 2RW DP‐SRAM.
Chapter 18
Figure 18.1 Scaled replica of the world’s first transistor (a point‐contact ...
Figure 18.2 Decorated cross‐sectional scanning electron micrograph of a SiGe...
Figure 18.3 Cross‐sectional scanning electron micrograph of a modern SiGe Bi...
Figure 18.4 The 125 mm Si MBE system that was used to build the first SiGe H...
Figure 18.5 The IEDM poster on the first SiGe HBT at the 50th anniversary of...
Figure 18.6 Patton and Iyer posing in front of the 50th anniversary IEDM dis...
Figure 18.7 Some of the key players of the early SiGe team at IBM: (seated a...
Figure 18.8 Example of a SiGe BiCMOS mm‐wave integrated circuit built by Cre...
Figure 18.9 DC total ionizing dose (TID) radiation response of third‐generat...
Figure 18.10 AC total ionizing dose (TID) radiation response of four generat...
Figure 18.11 Frequency response of the world’s fastest SiGe HBT, 800 GHz at ...
Figure 18.12 Global trends in
f
T
and
f
max
for SiGe HBTs.
Chapter 19
Figure 19.1 The four possible band conduction band profiles at the base/coll...
Figure 19.2 Equilibrium band diagram of a modern InP/GaAsSb DHBT featuring E...
Figure 19.3 Scaling dependence of THz emitter‐fin InP/GaAsSb DHBTs. InP/GaIn...
Chapter 20
Figure 20.1 Energy band diagrams explaining field‐effect modulation of two‐d...
Figure 20.2 Cross‐sectional schematic of delta‐doped pseudomorphic HEMT ca. ...
Figure 20.3 Schematic cross-section of state-of-the-art InAlAs/InGaAs HEMT o...
Figure 20.4 Record short-circuit current-gain cut-off frequency (fT) for GaA...
Chapter 21
Figure 21.1 History of TFT and IC development.
Figure 21.2 (a) Structure and (b) transfer characteristics of the first TFT.
Figure 21.3 (a) A 10.4‐inch TFT LCD in a 1990 IBM ThinkPad PC and (b) a LG 8...
Figure 21.4 Transfer characteristics of a‐Si:H, poly‐Si, and a‐IGZO TFTs....
Figure 21.5 (a) An EOG human eye monitor made of a 2‐OTFT amplifier, (b) tra...
Chapter 22
Figure 22.1 Capacitor array test for CCD concept.
Figure 22.2 First 8‐bit pixel
−1
CCD.
Figure 22.3 Readout principle of “Frame‐Transfer” CCD imaging array....
Figure 22.4 First CCD camera.
Figure 22.5 First CCD camera with prism removed showing 3 CCD imagers mounte...
Figure 22.6 Image from first CCD camera.
Chapter 23
Figure 23.1 Early CMOS image sensor chip for webcams. Left is digital log...
Figure 23.2 Photoelectrons are collected in an electrostatic storage well (N...
Figure 23.3 During readout of a CCD or CMOS image sensor, the signal charge ...
Figure 23.4 Illustration of a CCD interline transfer (ILT) pixel, top view (...
Figure 23.5 First CMOS image sensor chip and acquired 28 × 28 pixel image of...
Figure 23.6 Video grabs of the Mars 2020 Perseverance rover landing. Perseve...
Figure 23.7 TCAD simulation of a pinned photodiode (PPD) charge storage regi...
Figure 23.8 Circuit schematic of CMOS image sensor pixel including reset gat...
Figure 23.9 CMOS image sensor sales growth according to IC Insights. The ...
Figure 23.10 2017 Queen Elizabeth Prize for Engineering presentation at Buck...
Figure 23.11 QIS test chip containing 20 different 1 Mpixel arrays designed ...
Figure 23.12 Photon‐counting histogram (# occurrences vs. normalized readout...
Figure 23.13 Data taken from a 1 Mpixel array on the QIS test chip. (a) Clos...
Chapter 24
Figure 24.1 Schematic representation of MOSFET (left) and ISFET (right) stru...
Figure 24.2 CMOS ISFET structure in 0.35 μm technology schematic and macro‐m...
Figure 24.3 Schematic diagram of a resonant gate transistor consisting of a ...
Figure 24.4 Basic structure and currents of a vertical pnp magneto‐transisto...
Chapter 25
Figure 25.1 Cross sections of basic IGBT device structures.
Figure 25.2 B. Jayant Baliga examining photomasks for manufacturing the firs...
Figure 25.3 Evolution of the IGBT during the 1980s.
Figure 25.4 Evolution of the IGBT in the 1990s and beyond.
Figure 25.5 Prominent applications for the IGBT.
Chapter 27
Figure 27.1 The increasing transistor count in ICs fabricated during the Pro...
Chapter 29
Figure 29.1 10‐W HiFi amplifier with Germanium transistors (Radio Electronic...
Figure 29.2 AGC amplifier in 10 μm bipolar technology (JSSC Sansen August 19...
Figure 29.3 Clock generator of PABX system in pMOST technology (1973).
Figure 29.4 MPC‐1: 5 μm p‐well CMOS; 8.5 × 5.6 mm; January 1983....
Figure 29.5 MPC‐3: 5 μm JFET‐p‐well CMOS; 12 × 11 mm; January 1984....
Chapter 30
Figure 30.1 10‐Bit video‐rate A/D converter board.
Figure 30.2 Monolithic 10‐bit video‐rate ADC and comparator.
Figure 30.3 10‐Bit video‐rate Bi‐CMOS ADC and a HDTV receiver board....
Figure 30.4 Bi‐CMOS sample and hold circuit.
Figure 30.5 Characteristics of two‐step flash A/D conversion. (a) Convention...
Figure 30.6 Two‐step flash video rate A/D converter using resistive interpol...
Figure 30.7 10‐Bit 300 MS s−1 ADC using resistive interpolation....
Figure 30.8 Resistive interpolation in flash ADC.
Figure 30.9 10‐Bit 20 MS s
−1
30 mW CMOS ADC.
Figure 30.10 Chopper inverter comparator.
Figure 30.11 Conversion energy of video‐rate 10‐bit ADCs.
Figure 30.12 Early‐stage mixed‐signal LSI for digital handy camcorder....
Figure 30.13 Digital handy camcorder and signal processing circuits.
Figure 30.14 DVD recorder system and pickup and recovered signals.
Figure 30.15 ADC and latch circuit with gate‐weighted MOS. (a) ADC. (b) Latc...
Figure 30.16 Fully one‐chip mixed‐signal SoC for DVD systems....
Figure 30.17 DVD recorders.
Figure 30.18 (a) Flash ADC. (b) Flash ADC using interpolation technique.
Figure 30.19 Amplifier output voltages and interpolated voltages for input v...
Figure 30.20 A/D conversion; conventional and using interpolation technique....
Chapter 31
Figure 31.1 Common solid‐state NVMs: (a) Flash, (b) ReRAM, (c) MRAM, (d) PCR...
Figure 31.2 Multilevel memory hierarchy structure for modern computers.
Figure 31.3 NVM‐based computing‐in‐memory paradigm, where tensor computing c...
Chapter 32
Figure 32.1 The quantum stack from the public talk in [6].
Figure 32.2 Generic architecture of quantum‐classical interface for the cont...
Figure 32.3 Top: 0.16 μm long/narrow NMOS Id − Vds as a function of Vgs. Bot...
Figure 32.4 Subthreshold slope (SS) and non‐ideality factor (n) temperature ...
Figure 32.5 Left: redesign of a D‐flip‐flop in a 40‐nm CMOS technology. Righ...
Figure 32.6 Example of quantum‐classical interface implemented in 40‐nm CMOS...
Chapter 33
Figure 33.1 An example of the IBM copper‐Damascene metallization left after ...
Chapter 34
Figure 34.1 Appreciating the number of zeros!
Figure 34.2 The simplicity of MOS.
Figure 34.3 The first round of upgrades – material replacements.
Figure 34.4 A FinFET is a planar MOS device folded along the width direction...
Figure 34.5 A modern FinFET with both structural and material upgrades.
Figure 34.6 Self‐alignment of the source using the pre‐existing gate electro...
Figure 34.7 Why self‐alignment is important.
Figure 34.8 Fabrication of sidewall spacers.
Figure 34.9 Multiple spacers can define multiple self‐aligned structures (ti...
Chapter 35
Figure 35.1 Schematic illustration of a planar bulk‐silicon metal‐oxide‐semi...
Figure 35.2 Semi‐log plot of MOSFET output (drain) current vs. input (gate) ...
Figure 35.3 (left) Circuit symbols for n‐channel and p‐channel MOSFETs, (cen...
Figure 35.4 (left) Circuit diagram and truth table for a 2‐input NAND logic ...
Chapter 36
Figure 36.1 For many decades transistor performance was improved by shrinkin...
Figure 36.2 Carrier transport in a MOSFET.
Figure 36.3 (a) First demonstration of Ge PMOS with metal/high‐𝜅 technology...
Figure 36.4 Approaches for low resistance contacts. (a) Fermi level pinning ...
Figure 36.5 ρc vs. In composition with different Nd. The blue line and the r...
Figure 36.6 Comparison of contact schemes to n‐type Ge. NiGe formation and c...
Figure 36.7 Cross‐sectional TEM image of a heteroepitaxial‐Ge layer on Si gr...
Figure 36.8 (a) MHAH selective Ge growth on Si, (b) cross‐sectional SEM, and...
Figure 36.9 (a) Schematic and (b) cross‐section TEM of Si/s‐Ge/Si hetero‐str...
Figure 36.10 (a) Schematic and (b) cross‐section TEM (c) hole mobility of na...
Figure 36.11 Schematic illustration of an optical interconnect system and Si...
Guide
Cover Page
Series Page
Title Page
Copyright Page
About the Editors
About the Authors
Preface
Table of Contents
Begin Reading
Index
Wiley End User License Agreement
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IEEE Press445 Hoes LanePiscataway, NJ 08854
IEEE Press Editorial BoardSarah Spurgeon, Editor in Chief
Jón Atli Benediktsson
Behzad Razavi
Jeffrey Reed
Anjan Bose
Jim Lyke
Diomidis Spinellis
James Duncan
Hai Li
Adam Drobot
Amin Moeness
Brian Johnson
Tom Robertazzi
Desineni Subbaram Naidu
Ahmet Murat Tekalp
75th ANNIVERSARY OF THE TRANSISTOR
Edited by
Arokia Nathan
Darwin College, University of Cambridge, Cambridge, UK
Samar K. Saha
Prospicient Devices, Milpitas, CA, USA
Ravi M. Todi
President, IEEE EDS, USA
Copyright © 2023 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Published by John Wiley & Sons, Inc., Hoboken, New Jersey.Published simultaneously in Canada.
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About the Editors
Arokia Nathan is a leading pioneer in the development and application of thin film transistor technologies to flexible electronics, display and sensor systems. His current research interests lie in integration of devices, circuits, and systems using a broad range of inorganic and organic thin film material systems on rigid and mechanically flexible substrates for large area systems. Following his PhD in Electrical Engineering, University of Alberta, Canada in 1988, he joined LSI Logic Corp., Santa Clara, CA, where he worked on advanced multi‐chip packaging techniques and related issues. Subsequently he was at the Institute of Quantum Electronics, ETH Zürich, Switzerland, before joining the Electrical technology and was a recipient of the 2001 Natural Sciences and Engineering Research Council E.W.R. Steacie Fellowship. In 2004, he was awarded the Canada Research Chair in nano‐scale flexible circuits. In 2005/2006, he was a visiting professor in the Engineering Department, University of Cambridge, UK. Later in 2006, he joined the London Centre for Nanotechnology, University College London as the Sumitomo Chair of Nanotechnology. He moved to Cambridge University in 2011 as the Chair of Photonic Systems and Displays, and he is currently a Bye‐Fellow and Tutor at Darwin College. He has over 600 publications in the field of sensor technology and CAD, and thin film transistor electronics including 6 books, and more than 130 patents and four spin‐off companies. He is a recipient of the Royal Society Wolfson Research Merit Award, the BOE Award for contributions to TFT CAD, and winner of the 2020 IEEE EDS JJ Ebers Award. He serves on technical committees of professional societies and conferences in various capacities. He is currently the vice president of Publications and Products in IEEE’s Electron Devices Society. He is a fellow of IEEE, a Distinguished Lecturer of the IEEE Electron Devices Society and Sensor Council, a chartered engineer (UK), Fellow of the Institution of Engineering and Technology (UK), Fellow of the Royal Academy of Engineering, of the Society for Information Displays, and Fellow of the Canadian Academy of Engineering.
Samar K. Saha is the Chief Research Scientist at Prospicient Devices, Milpitas, California, USA. Since 1984, he has worked at various technical and management positions for SuVolta, Silterra USA, DSM Solutions, Synopsys, Silicon Storage Technology, Philips Semiconductors, LSI Logic, Texas Instruments, and National Semiconductor. He has, also, worked as an Electrical Engineering faculty at Santa Clara University, California; the University of Colorado at Colorado Springs, Colorado; the University of Nevada at Las Vegas, Nevada; Auburn University, Alabama; and Southern Illinois University at Carbondale, Illinois. He has authored over 100 research papers; two books entitled, FinFET Devices for VLSI Circuits and Systems (CRC Press, 2020) and Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond (CRC Press, 2015); one book chapter, “Introduction to Technology Computer Aided Design,” in Technology computer Aided design: Simulation for VLSI MOSFET (C.K. Sarkar, ed., CRC Press, 2013); and holds 13 US patents. His book on FinFET has been translated into Chinese language entitled, Nanoscale Integrated Circuits FinFET Device Physics and Modeling (CRC Press/China Machine Press, 2022).
Dr. Saha served as the 2016–2017 President of the Institute of Electrical and Electronics Engineers (IEEE) Electron Devices Society (EDS) and currently serving as a member of the IEEE Fellow Committee. He is a life fellow of IEEE, a fellow of the Institution of Engineering and Technology (IET), UK, and a distinguished lecturer of IEEE EDS. Previously, he has served EDS as senior past and junior past president; Awards chair; vice president of publications; an elected member of the Board of Governors; fellow evaluation committee chair; editor‐in‐chief of IEEE QuestEDS; chair of George Smith and Paul Rappaport awards; editor of Region‐5 and 6 Newsletter; chair of Compact Modeling Technical Committee; and Chair of North America West Subcommittee for Regions/Chapters; IEEE as a member of the Conference Publications Committee and TAB Periodicals Committee; and Santa Clara Valley/San Francisco EDS chapter as the treasurer, vice chair, and chair.
In publications, he has served as a Guest Editor of six Special Issues (SIs) of IEEE EDS journals including head guest editor of the IEEE Transactions on Electron Devices SIs on Advanced Compact Models and 45‐nm Modeling Challenges and Compact Interconnect Models for Giga Scale Integration and two IEEE Journal of Electron Devices Society SIs from the selected extended papers presented at conferences. Dr. Saha received the PhD degree in Physics from Gauhati University, India, and MS degree in Engineering Management from Stanford University, USA. He is the recipient of the 2021 IEEE EDS Distinguished Service Award.
Ravi M. Todi received his Masters and Doctoral degrees in Electrical Engineering from University of Central Florida (UCF), Orlando, Florida. His graduate research was focused on gate stack engineering, with emphasis on binary metal alloys as gate electrode and on high‐mobility germanium channel devices. In his early career, as advisory engineer/scientist at semiconductor research and development center (SRDC) at IBM microelectronics division, his work was focused on high‐performance embedded dynamic random‐access memory (eDRAM) integration on 45 nm silicon on insulator (SOI) logic platform. For his many contributions to the success of the eDRAM program at IBM, Ravi was awarded IBM’s prestigious outstanding technical achievement award. Over the past decade, Ravi has held several lead technical and management positions at Qualcomm, GlobalFoundries, and Western Digital. Most recently he is the silicon technologist responsible for foundry technology at an early‐stage Silicon Valley startup. With over 60 US granted patents, over 30 peer‐reviewed journal publications, over 40 international conference presentations, and over 50 invited distinguished lectures, Ravi is well known in the semiconductor industry as a technical/business leader.
Ravi served as an associate editor for IEEE Transactions on Electron Devices from 2014 to 2019, as IEEE‐EDS treasurer from 2012 to 2015, as IEEE‐EDS vice president for technical activities and conferences from 2016 to 2019, as EDS president‐elect in 2020, and is currently serving as EDS president from 2021 to 2023. He is the recipient of 2011 IEEE EDS Early Career Award. He is an IEEE Fellow and is a Distinguished Lecturer for IEEE Electron Devices Society.
About the Authors
Chapter 1
Leo Esaki was born in Osaka, Japan, in 1925. He received his BS and PhD degrees in physics in 1947 and 1959, respectively, from the University of Tokyo, Japan. He was an IBM Fellow and engaged in semiconductor research at the IBM Thomas J. Watson Research Center, Yorktown Heights, New York, from 1960 to 1992. Prior to joining IBM, he worked at Sony Corp., where his research on heavily doped Ge and Si resulted in the discovery of the Esaki tunnel diode; this device constitutes the first quantum electron device. Since 1969, Esaki has, with his colleagues, pioneered “designed semiconductor quantum structures” such as man‐made superlattices, exploring a new quantum regime at the frontier of semiconductor physics. He also served as President of the University of Tsukuba (1992–1998) and Shibaura Institute of Technology (2000–2005). Since April 2006, he has assumed the position of president of the Yokohama College of Pharmacy.
Dr. Esaki was awarded the 1973 Nobel Prize in Physics in recognition of his pioneering work on electron tunneling in solids. He is also a recipient of the Nishina Memorial Award, the Asahi Press Award, the Toyo Rayon Foundation Award, the IRE Morris N. Liebmann Memorial Prize, the Franklin Institute’s Stuart Ballantine Medal, the Japan Academy Award, the Order of Culture from the Japanese Government, the American Physical Society International Prize for New Materials, the IEEE Medal of Honor, the Japan Prize, and the Grand Cordon of the Order of the Rising Sun, First Class from the Japanese Government.
He is a Fellow of the American Academy of Arts and Sciences, a member of the Japan Academy, a Foreign Associate of the National Academy of Science and the National Academy of Engineering, a member of the Max‐Planck‐Gesellschaft, and a foreign member of the American Philosophical Society, the Russian Academy of Sciences, and the Italian National Academy of Science.
Chapter 2
Dr. Samar K. Saha has served as the 2016–2017 President of the IEEE Electron Devices Society (EDS). Currently, he is the Chief Scientist at Prospicient Devices, Milpitas, USA. Since 1984, he has worked in various technical/management positions at National Semiconductor, LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology, Synopsys, DSM Solutions, Silterra USA, and SuVolta. In academia, he was an Electrical Engineering faculty at Southern Illinois University at Carbondale, Illinois; Auburn University, Alabama; the University of Nevada at Las Vegas, Nevada; the University of Colorado at Colorado Springs, Colorado; and Santa Clara University, Santa Clara, USA.
He has authored over 100 research papers; two books entitled, FinFET Devices for VLSI Circuits and Systems (CRC Press, 2020) and Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond (CRC Press, 2015); one book chapter, “Introduction to Technology Computer Aided Design,” in Technology computer Aided design: Simulation for VLSI MOSFET (C.K. Sarkar (ed.), CRC Press, 2013); and holds 13 US patents. His book on FinFET has been translated in Chinese language entitled, Nanoscale Integrated Circuits FinFET Device Physics and Modeling (CRC Press/China Machine Press, 2022).
Dr. Saha received the PhD degree in Physics from Gauhati University and an MS degree in Engineering Management from Stanford University. He is a distinguished Lecturer of IEEE EDS, an IEEE Life Fellow, and a Fellow of the Institution of Engineering and Technology (IET), UK. He is the recipient of 2021 IEEE EDS Distinguished Service Award.
Chapter 3
Prasanta Kumar Basu (MIEEE’04‐SMIEEE’09) was born in 1946 and obtained BSc (Physics honors), and BTech and MTech. degrees in Radio Physics and Electronics, all from the University of Calcutta (CU). He joined the Institute of Radio Physics and Electronics, CU (IRPE‐CU) as a lecturer in 1971 and retired as professor from there in 2011. He then worked as UGC BSR Faculty Fellow, and afterward as visiting Professors at IIT Kharagpur and National Chung Cheng University, Taiwan. He did research in physics of semiconductors and their nanostructures, and electronic and photonic devices. He has authored more than 140 journal papers, many refereed conference papers, and three book chapters. He has authored and coauthored four books: Theory of Optical Processes in Semiconductors (Oxford University Press, UK, 1997), Silicon Photonics (with M J Deen, Wiley, UK, 2012), Semiconductor Laser Theory (with Bratati Mukhopadhyay and Rikmantra Basu; CRC Press, USA, 2015), and Semiconductor Nanophotonics (with Bratati Mukhopadhyay and Rikmantra Basu; Oxford University Press, UK, 2022). He visited Germany as an Alexander von Humboldt Fellow, and McMaster University, Canada, several times as a visiting professor. He also visited the United States, the United Kingdom, and several European and Asian countries as a visiting professor, researchers, and authors of papers in conferences. Currently, he is engaged in collaborative research and book writing with faculties of IRPE‐CU and NIT Delhi. He writes and gives lectures on topics related to history of science and technology and recent developments in electronics and photonics.
Chapter 4
Robert B. Kaufman is a PhD candidate at the University of Illinois Urbana‐Champaign in the department of Electrical and Computer Engineering. He received a BS and MS in electrical engineering from the University of Illinois Urbana‐Champaign in 2017 and 2021, respectively. His research is in the field of optoelectronics under the advisement of Prof. John Dallesasse. Specifically, Robert has been focused on the design, fabrication, and characterization of a novel variation of the quantum‐cascade laser that incorporates a heterojunction bipolar transistor. He is a student member of IEEE.
John M. Dallesasse is a Professor of Electrical and Computer Engineering and Associate Dean in the Grainger College of Engineering at the University of Illinois at Urbana‐Champaign (UIUC), where he has been for over 11 years. He also has over 20 years of industry experience in technology development and executive management, having led technically diverse and geographically distributed engineering teams. Prior to joining UIUC, he was the Chief Technology Officer, Vice President, and cofounder of Skorpios Technologies, where he was responsible for developing innovative methods for heterogeneous integration of compound semiconductors with silicon. His technical contributions include, with Nick Holonyak, Jr., the discovery of III–V Oxidation, which has become an enabling process technology for the fabrication of Vertical‐Cavity Surface‐Emitting Lasers (VCSELs) for optical networking, 3D imaging, and LIDAR applications. His research group at UIUC works on novel methods for heterogeneous integration using epitaxial transfer which have been applied to the fabrication of VCSELs and other photonic devices on silicon, on mode control methods which have been used to provide record single‐mode powers on conventional VCSEL structures, and on mid‐IR emitters using quantum cascade structures within a transistor structure. John has over 100 publications and conference presentations, and 51 issued patents. He serves or has served as the Chair of the Steering Committee for the IEEE Journal of Lightwave Technology, the Chair of the Steering Committee for the IEEE Transactions on Semiconductor Manufacturing, and as the Vice President of Technical Committees for IEEE‐EDS. He is a Fellow of the IEEE and Optica.
Chapter 5
Tak H. Ning received his PhD degree in physics from the University of Illinois at Urbana‐Champaign in 1971. He joined IBM Thomas J. Watson Research Center in 1973, working there until retirement, as an IBM Fellow, in 2016. He made significant contributions to the understanding of hot‐electron effects in MOSFETs, and to advancing the technologies of bipolar transistors, CMOS and EEPROM. He has received several awards, including the 2007 Electrochemical Society Gordon E. Moore Medal, the 1989 IEEE Electron Devices Society J. J. Ebers Award, and the 1991 IEEE Jack A. Morton Award. He is a member of the U.S. National Academy of Engineering, and a fellow of the IEEE and of the American Physical Society.
Chapter 6
Mamidala Jagadesh Kumar (SMIEEE’98) is a Professor (on‐leave) at the Indian Institute of Technology, New Delhi, India. He was the Vice‐Chancellor of Jawaharlal Nehru University, New Delhi, India. He is currently the Chairman, University Grants Commission, and Chairman, All India Council for Technical Education, Government of India. He is the Editor‐in‐Chief of IETE Technical Review and an Editor of IEEE Journal of the Electron Devices Society. He was an Editor of IEEE Transactions on Electron Devices from 2006 to 2015. He has widely published in the area of Micro/Nanoelectronics and is known for his excellence in teaching. He has coauthored three books and one of them is on “Junctionless Field Effect Transistors: Design, Modeling and Simulation” which is published by the Wiley‐IEEE press.
Shubham Sahay (MIEEE’15) is an assistant professor in the department of Electrical Engineering at Indian Institute of Technology (IIT) Kanpur, India. Prior to joining IIT Kanpur, he worked as a postdoctoral research scholar at the University of California, Santa Barbara (2018–2020). He received the BTech (Hons.) in Electronics Engineering with four gold medals and several cash prizes from the IIT BHU Varanasi in 2014 and the PhD degree in Electrical Engineering from IIT Delhi in 2018. He has coauthored a book on “Junctionless Field Effect Transistors: Design, Modeling and Simulation” which is published by the Wiley‐IEEE press. He has also published several peer‐reviewed articles on topics including semiconductor device design and modeling, neuromorphic computing, and hardware security primitives utilizing emerging nonvolatile memories. He is an editor of IETE Technical Review and review editor for Frontiers in Neuroscience: Neuromorphic Engineering and Frontiers in Electronics: Integrated Circuits and VLSI. He is a member of IEEE and the chair of IEEE EDS UP section. He also appeared in the list of Golden reviewers for IEEE Transactions on Electron Devices and IEEE Electron Device Letters from 2016 to 2022. His present research interests include Hardware Neuromorphic computing platforms, Hardware security primitives, Novel Device Architectures for Sub‐10 nm Regime, Analytical and Compact Modeling of Semiconductor Devices and Nonvolatile Memories, and Spintronics.
Chapter 7
Hiroshi Iwai is a semiconductor device engineer, who contributed to the development of integrated circuits technologies and products. He received BE and Doctor Degree in Engineering from the University of Tokyo. He worked at Toshiba, Tokyo Institute of Technology, and National Yang Ming Chiao Tung University for 50 years since 1973. Especially, he has contributed to the miniaturization of the LSIs since the 8 μm PMOS generation. He developed Toshiba’s first NMOS LSI technology in 1975, as well as 1k bit SRAMs. For the development of a 64 k bit DRAM, he introduced stepper lithography and dry process into production for the first time in the world in 1980. He broke the 0.1 μm limit of CMOS miniaturization by developing 40 nm MOSFET technologies in 1993, which was more than 2 generations earlier than competitive companies. He developed the world’s first 0.15 μm RFCMOS technologies in the middle of 1990s, which contributed to the realization of Bluetooth. Dr. Iwai has contributed to IEEE and EDS activities and administrations over 40 years. He served as the IEEE EDS president and the IEEE Division I director. He was appointed to the first IEEE EDS eminent lecturer. Currently, he is a vice dean and a distinguished chair professor of National Yang Ming Chiao Tung University and a professor emeritus of Tokyo Institute of Technology.
Chapter 8
Robert E. Kerwin is currently an independent consultant in electronics technology, intellectual property management, and quality management practices. In April 1994, he retired from AT&T as a General Manager of the Intellectual Property Division. Prior to that, he had been Manager, Corporate Quality at AT&T after 22 years of experience at AT&T Bell Laboratories.
At AT&T Bell Laboratories, Dr. Kerwin was a member of Technical Staff in the Electronic Component Processes Laboratory (1964–1971), supervised the Photolithography Development Group (1971–1974), supervised the Murray Hill Integrated Circuit Design Capability Line responsible for the development of CMOS processing technology (1974–1980), and headed the Component Quality and Reliability Department responsible for reliability assurance of all electronic components made by or purchased for AT&T (1980–1986).
Dr. Kerwin holds a BS degree in Chemistry from Boston College, an MS degree in Chemistry from the Massachusetts Institute of Technology, and a PhD degree in Chemistry from the University of Pittsburgh. Prior to joining AT&T Bell Laboratories, he was a Research Fellow in the Polymer Studies Group at the Mellon Institute.
He is a Bell Laboratories Fellow, a Fellow of the American Institute of Chemistry, a member of the Society of Sigma Xi, the American Association for the Advancement of Science, and the Institute Electrical and Electronics Engineers. In 1994, he received the Jack A. Morton Award from the IEEE “For Outstanding Contributions in the Field of Solid State Devices,” and Inventor of the Year Award from the New Jersey Inventors Hall of Fame.
He holds 15 patents on microelectronics materials and processes, including the fundamental silicon‐gate process used in all semiconductor memory and microprocessor devices. He has published 15 papers and 5 book chapters on microelectronics technology, quality management principles, and intellectual property management.
Dr. Kerwin served as a member of the Board of Examiners for the Malcolm Baldridge National Quality Award (1988–1991), and lectured on quality management practices at the Brookings Institution (1986–1991).
Chapter 9
Alfred U. MacRae was born in New York City in 1932. He earned his bachelor’s and graduate degrees at Syracuse University, where he studied physics. Upon completing his doctorate in 1960, MacRae began working for Bell Telephone Laboratories, first in Murray Hill and then in Holmdel, New Jersey. He researched the location of atoms on metals and semiconductors, worked on ion implantation, worked on the fabrication, design, and testing of integrated circuits, and finally led an organization that developed large transmission systems and satellite communications. He retired in 1995 as Director of the Satellite Communications Lab. He held 18 patents and was published in numerous technical journals. MacRae was elected a fellow of the American Physical Society in 1964, was the 1994 recipient of the J.J. Ebers Award, presented by the IEEE Electron Devices Society, and was elected to membership of the National Academy of Engineering in 2003. MacRae passed away at home in Seattle, Washington, in early 2023.
Chapter 10
Yuan Taur received the BS degree in physics from National Taiwan University, Taipei, Taiwan, in 1967 and the PhD degree in physics from the University of California, Berkeley, in 1974.
From 1979 to 1981, he worked at Rockwell International Science Center, Thousand Oaks, California, on II–VI semiconductor devices for infrared sensor applications. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was the Manager of Exploratory Devices and Processes. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. He became a Distinguished Professor in 2014.
Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as the Editor‐in‐Chief of the IEEE Electron Device Letters from 1999 to 2011. He has also served on the technical program committees and as a panelist for the Device Research Conference, and the International Electron Devices Meeting, and as the Program Chairman for the Symposium on VLSI Technology.
Dr. Yuan Taur has authored or coauthored over 200 technical papers and holds 14 U.S. patents. He coauthored a book, “Fundamentals of Modern VLSI Devices,” published by Cambridge University Press in 1998. The 2nd edition was published in 2009, the 3rd edition in 2022.
Dr. Yuan Taur received the IEEE Electron Devices Society’s J.J. Ebers Award in 2012 “for contributions to the advancement of several generations of CMOS process technologies.” He also received the IEEE Electron Devices Society’s Distinguished Service Award in 2014.
