Advances in Embedded and Fan-Out Wafer Level Packaging Technologies E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: Wiley - IEEE
• Sprache: Englisch

Seitenzahl: 804

Veröffentlichungsjahr: 2019

Beschreibung

Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges Embedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons. Filled with contributions from some of the field's leading experts,Advances in Embedded and Fan-Out Wafer Level Packaging Technologies begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions. * Discusses specific company standards and their development results * Content relates to practice as well as to contemporary and future challenges in electronics system integration and packaging Advances in Embedded and Fan-Out Wafer Level Packaging Technologies will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.

Leseprobe

Advances in Embedded and Fan‐Out Wafer‐Level Packaging Technologies

Edited by

Beth Keser, Ph.D.andSteffen Kroehnert

This edition first published 2019© 2019 John Wiley & Sons, Inc.

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by law. Advice on how to obtain permission to reuse material from this title is available at http://www.wiley.com/go/permissions.

The right of Beth Keser and Steffen Kroehnert are to be identified as the editors of this work has been asserted in accordance with law.

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Library of Congress Cataloging‐in‐Publication Data

Names: Keser, Beth, 1971– editor. | Kroehnert, Steffen, 1970– editor.Title: Advances in embedded and fan‐out wafer level packaging technologies / [edited by] Beth Keser, Ph.D., Steffen Kroehnert.Description: 1st edition. | Hoboken, NJ, USA : Wiley, [2018] | Includes bibliographical references and index. |Identifiers: LCCN 2018034374 (print) | LCCN 2018037473 (ebook) | ISBN 9781119313977 (Adobe PDF) | ISBN 9781119313984 (ePub) | ISBN 9781119314134 (hardcover)Subjects: LCSH: Chip scale packaging. | Integrated circuits–Wafer scale integration.Classification: LCC TK7870.17 (ebook) | LCC TK7870.17 .A38 2018 (print) | DDC 621.39/5–dc23LC record available at https://lccn.loc.gov/2018034374

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