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- Herausgeber: John Wiley & Sons
- Kategorie: Wissenschaft und neue Technologien
- Serie: Wiley - IEEE
- Sprache: Englisch
A comprehensive guide to antenna design, manufacturing processes, antenna integration, and packaging Antenna-in-Package Technology and Applications contains an introduction to the history of AiP technology. It explores antennas and packages, thermal analysis and design, as well as measurement setups and methods for AiP technology. The authors--well-known experts on the topic--explain why microstrip patch antennas are the most popular and describe the myriad constraints of packaging, such as electrical performance, thermo-mechanical reliability, compactness, manufacturability, and cost. The book includes information on how the choice of interconnects is governed by JEDEC for automatic assembly and describes low-temperature co-fired ceramic, high-density interconnects, fan-out wafer level packaging-based AiP, and 3D-printing-based AiP. The book includes a detailed discussion of the surface laminar circuit-based AiP designs for large-scale mm-wave phased arrays for 94-GHz imagers and 28-GHz 5G New Radios. Additionally, the book includes information on 3D AiP for sensor nodes, near-field wireless power transfer, and IoT applications. This important book: * Includes a brief history of antenna-in-package technology * Describes package structures widely used in AiP, such as ball grid array (BGA) and quad flat no-leads (QFN) * Explores the concepts, materials and processes, designs, and verifications with special consideration for excellent electrical, mechanical, and thermal performance Written for students in electrical engineering, professors, researchers, and RF engineers, Antenna-in-Package Technology and Applications offers a guide to material selection for antennas and packages, antenna design with manufacturing processes and packaging constraints, antenna integration, and packaging.
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Seitenzahl: 558
Veröffentlichungsjahr: 2020
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IEEE Press
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IEEE Press Editorial Board
Ekram Hossain, Editor in Chief
Giancarlo Fortino
Andreas Molisch
Diomidis Spinellis
David Alan Grier
Saeid Nahavandi
Elya B. Joffe
Donald Heirman
Ray Perez
Sarah Spurgeon
Xiaoou Li
Jeffrey Reed
Ahmet Murat Tekalp
Antenna-in-Package Technology and Applications
Edited by
Duixian Liu
IBM Thomas J. Watson Research CenterNew York, USA
Yueping Zhang
School of Electrical and Electronic EngineeringNanyang Technological University, Singapore
Copyright © 2020 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Published by John Wiley & Sons, Inc., Hoboken, New Jersey.Published simultaneously in Canada.
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Library of Congress Cataloging‐in‐Publication data applied for
ISBN: 9781119556633
Cover Design: WileyCover Image: © windwheel/Shutterstock
List of Contributors
Yueping Zhang
School of Electrical and Electronic Engineering
Nanyang Technological University
Singapore
Ning Ye
Package Technology Development & Integration
Milpitas
USA
Xiaoxiong Gu
Thomas. J. Watson Research Center, IBM
New York
USA
Pritish Parida
Thomas. J. Watson Research Center, IBM
New York
USA
A.C.F. Reniers
Department of Electrical Engineering
Eindhoven University of Technology (TU/e)
Eindhoven
The Netherlands
U. Johannsen
Department of Electrical Engineering
Eindhoven University of Technology (TU/e)
Eindhoven
The Netherlands
A.B. Smolders
Department of Electrical Engineering
Eindhoven University of Technology (TU/e)
Eindhoven
The Netherlands
Atif Shamim
Computer, Electrical and Mathematical Sciences and Engineering Division
King Abdullah University of Science & Technology (KAUST)
KSA
Haoran Zhang
Computer, Electrical and Mathematical Sciences and Engineering Division
King Abdullah University of Science & Technology (KAUST)
KSA
Frédéric Gianesello
ST Microelectronics
Technology R&D
Silicon Technology Development
Crolles
France
Diane Titz
Université Nice Sophia Antipolis
Polytech'Lab
Biot
France
Cyril Luxey
Université Nice Sophia Antipolis
Polytech'Lab
Biot
France
Maciej Wojnowski
Infineon Technologies AG
Neubiberg
Germany
Klaus Pressel
Infineon Technologies AG
Regensburg
Germany
Tong‐Hong Lin
The School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta
USA
Ryan A. Bahr
The School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta
USA
Manos M. Tentzeris
The School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta
USA
Duixian Liu
Thomas. J. Watson Research Center, IBM
New York
USA
Amin Enayati
Emerson & Cuming Anechoic Chambers
Antwerp Area
Belgium
Karin Mohammadpour‐Aghdam
School of Electrical and Computer Engineering
University of Tehran
Iran
Farbod Molaee‐Ghaleh
School of Electrical and Computer Engineering
University of Tehran
Iran
Preface
Rapid advances in semiconductor and packaging technologies have promoted the development of two system design concepts known as system on chip (SoC) and system‐in‐package (SiP). SoC integrates analog, digital, mixed‐signal, and radio frequency (RF) circuits on a chip by a semiconductor process, while SiP implements separately manufactured functional blocks in a package by a packaging process. SoC yields improved system reliability and functionality at a much lower system cost. However, it degrades system performance and increase system power consumption due to unavoidable compromises in every circuit type in order to use the same material and process. On the contrary, SiP enhances system performance and reduces system power consumption but results in lower system reliability and higher system cost because of functional blocks and the fabrication of the package with different materials and processes.
Antennas are essential components for wireless systems. It is known that antennas are difficult to miniaturize, let alone integrate. Nevertheless, there have been attempts to integrate an antenna (or antennas) with other circuits in a die on a wafer using the back end of the line. An antenna realized in such a way is called an antenna on a chip (AoC) and is more suitable for terahertz applications for cost and performance reasons. In addition, there have been studies to integrate an antenna (or antennas) with a radio or radar die (or dies) into a standard surface‐mounted device using a packaging process, which has created a new trend in antenna and packaging termed antenna‐in‐package (AiP). AoC and AiP are obviously subsets of the above SoC and SiP concepts, so why do we specifically differentiate them from SoC and SiP? The reason is to highlight their unique property of radiation.
AiP technology balances performance, size, and cost, hence it has been widely adopted by chipmakers for 60‐GHz radios, augmented/virtual reality gadgets, and gesture radars. It has also found applications in 79‐GHz automotive radars, 94‐GHz phased arrays for imaging and data communications, 122‐GHz, 145‐GHz, and 160‐GHz sensors, as well as 300‐GHz wireless links. Recently, AiP technology has been under further development for millimeter‐wave (mmWave) fifth‐generation (5G) technology. Scalable large AiPs and multiple small AiPs have been successfully demonstrated in base stations, mobile phones, and networked cars at 28 GHz. We therefore believe that AiP technology will cause fundamental changes in the design of antennas for mobile communications for 5G and beyond operating in mmWave bands.
The development of mmWave AiP technology is particularly challenging because of the associated complexity in design, fabrication, integration, and testing. This book aims to face these challenges through disseminating relevant knowledge, addressing practical engineering issues, meeting immediate demands for existing systems, and providing the antenna and packaging solutions for the latest and emerging applications.
This book contains 11 chapters. The first five chapters lay some foundation and introduce fundamental knowledge. After the introductory chapter about how AiP technology has been developed as we know it today, several types of antennas are discussed in Chapter 2. An attempt is made to summarize the basic antennas and those antennas specifically developed for AiP technology. Emphasis is given to microstrip patch antennas and arrays, grid array antennas, Yagi–Uda antennas, and magneto‐electric dipole antennas because of their dominance in AiP technology. Performance improvement techniques of antennas for AiP technology are also described. Chapter 3 describes today's mainstream packaging solutions with either wire‐bond or flip‐chip interconnects, wafer‐level package, and fan‐out wafer‐level package. Chapter 4 focuses on the electrical, mechanical, and thermal co‐design for AiP modules. More importantly, the thermal management considerations for next‐generation heterogeneous integrated systems are reviewed in order to address the growing need for cooling the high‐power devices of future radio systems. Chapter 5 presents the design and optimization of an anechoic test facility for testing mmWave integrated antennas. This facility can be used for both probe‐based and connector‐based measurements.
The next five chapters are related to the design, fabrication, and characterization of AiPs in different materials and processes for mmWave applications. Chapter 6 discusses low‐temperature co‐fired ceramic (LTCC)‐based AiP. LTCC has unique properties for packaging mmWave circuits since it can provide a durable hermetic package with antennas, cavities, and integrated passive components. Chapter 7 illustrates how industrial organic packaging substrate technology used for classical integrated circuit (IC) packaging can support the development of innovative, efficient, and cost‐effective mmWave AiPs from 60 GHz up to 300 GHz. Chapter 8 focuses on embedded wafer‐level ball grid array (eWLB)‐based AiP. Unlike LTCC or high‐density integr (HDI), eWLB eliminates the need for a laminate substrate and replaces it with copper redistribution layers. Polymers are used for the electrical isolation between the metal layers. The metal routings are deposited by a combination of sputtering and electroplating with a thin film process. eWLB has historically been developed for mmWave automotive radar systems and therefore has naturally been used for mass production of mmWave AiPs. Chapter 9 presents surface laminar circuit (SLC)‐based AiP. Compared to LTCC, HDI, and eWLB, SLC is more suitable for fabrication of very large or dense AiPs. The chapter describes SLC materials and design guidelines, and then addresses the design challenges and solutions for 8 × 8 dual‐polarized phased arrays at 94 GHz for imaging and 28 GHz for 5G base station applications, respectively. Chapter 10 introduces different additive manufacturing technologies, methods to characterize three‐dimensional (3D)‐printed materials, a hybrid printing process by integrating 3D and inkjet printing, and a broadband 5G AiP realized with the hybrid process.
The last chapter turns to 3D AiP for power transfer, sensor nodes, and Internet of Things applications. This package has a cubic geometry with radiating antennas on its surrounding faces. The chapter highlights small antenna design and miniaturizing techniques as well as multi‐mode capability as a way to achieve wideband antennas.
This book is the result of the joint efforts of the 21 authors in eight different institutions in Asia, Europe, and the United States. A book on an emerging topic like AiP technology would not have been possible without such collaborations. We thank all authors for their creative contributions and careful preparation of manuscripts. We are also pleased to acknowledge the professional cooperation of the publishers.
Duixian LiuIBM Thomas J. Watson Research CenterYorktown Heights, NY, USA
Yueping ZhangSchool of Electrical and Electronic EngineeringNanyang Technological UniversitySingapore
Abbreviations
2D
two‐dimensional
3D
three‐dimensional
3GPP
3rd Generation Partnership Project
5G
fifth‐generation
ABS
acrylonitrile butadiene styrene
ACE
Advanced Semiconductor Engineering, Inc.
ACP
aperture‐coupled patch
ADS
Advanced Design System
AIA
active integrated antenna
AiM
antenna in a module
AiP
antenna‐in‐package
AM
additive manufacturing
AMC
artificial magnetic conductor
AoB
antenna on a board
AoC
antenna on a chip
AR
axial ratio
ARM
advanced reduced‐instruction set‐computer machine
ASIC
application‐specific integrated circuit
ASUT
antenna system under test
AUT
antenna under test
Az
azimuth
BCB
benzocyclobutene
BC‐SRR
broadside‐coupled SRR
BER
bit error rate
BERT
BER tester
BiCMOS
bipolar complementary metal oxide semiconductor
BGA
ball grid array
BLE
Bluetooth low energy
BT
Bluetooth
BT
bismaleimide triazine
BW
bandwidth
C4
controlled collapse chip connection
CATR
compact antenna test range
CCL
copper‐clad laminate
CLIP
continuous liquid interface printing
CMA
characteristic mode analysis
CMF
conjugate match factor
CMG
conjugate match gain
CMOS
complementary metal‐oxide semiconductor
CNC
computer numerical controlled
CP
circular polarization
CPS
coplanar strip
CPU
central processing unit
CPW
coplanar waveguide
CT
computer tomography
CTE
coefficient of thermal expansion
CUF
capillary underfill
DC
direct current
DLP
digital light projection
DMA
dynamic mechanical analysis
DRAM
dynamic random‐access memory
DRIE
deep reactive ion etching
EBG
electromagnetic bandgap
EIRP
equivalent isotropic radiated power
El
elevation
EM
electromagnetic
EMI
electromagnetic interference
ESD
electrostatic discharge
ETS
embedded traces
eWLB
embedded wafer‐level ball grid array
EZL
embedded Z line
FCC
Federal Communications Commission
FDM
fused‐deposition modeling
FE
front end
FF
far‐field
FMCW
frequency modulated continuous wave
FoM
figure of merit
FO PoP
fan‐out package‐on‐package
FO‐WLP
fan‐out wafer‐level packaging
FPGA
field‐programmable gate array
FR4
flame resistant 4
FSS
frequency selective surface
GaAs
gallium arsenide
GaN
gallium nitride
Gb/s
gigabit per second
GPU
graphics processing unit
GSG
ground‐signal‐ground
GSGSG
ground‐signal‐ground‐signal‐ground
GSM
global system for mobile communications
HAST
highly accelerated stress test
HBM
high bandwidth memory
HDI
high‐density integration
HDI
high‐density interconnect
HFSS
high‐frequency structure simulator
HPBW
half‐power beam width
HTCC
high‐temperature co‐fired ceramics
IC
integrated circuit
IEEE
Institute of Electrical and Electronics Engineers
IF
intermediate frequency
InFO_PoP
integrated fan out package on package
I/O
input/output
IoT
Internet of Things
ISM
industrial, scientific and medical
ISSCC
International Solid‐State Circuits Conference
JPL
jet propulsion laboratory
LCD
liquid crystal display
LCP
liquid crystal polymer
LGA
land grid array
LHCP
left‐hand circular polarization
LNA
low‐noise amplifier
LP
linearly polarized
LTCC
low‐temperature co‐fired ceramic
MACM
multiple amplitude component method
MAPCM
multiple amplitude phase component method
MCM
multi‐chip module
MEMS
micro‐electromechanical systems
MIM
metal–insulator–metal
MIMO
multiple input multiple output
MMIC
monolithic microwave integrated circuit
MMWAC
mmWave anechoic chamber
mmWave
millimeter‐wave
mSAP
modified semi‐additive process
MUF
molded underfill
NF
near‐field
NF
noise figure
NIST
National Institute of Standards and Technology
NRE
non‐recurring engineering
NRW
Nicholson–Ross–Weir
OTA
over‐the‐air
PAE
power‐added efficiency
PAM
phase amplitude method
PBO
polybenzoxazoles
PCB
printed circuit board
PEC
perfect electric conductor
PER
packet error rate
PET
polyethylene terephthalate
pHEMT
pseudomorphic high electron mobility transistor
PI
polyimide
PLA
polylactic acid
PLL
phase‐locked loop
PMC
perfect magnetic conductor
PP
polypropylene
PPM
polarization pattern method
PTH
plated‐through‐hole
p.u.l.
per unit length
QFN
quad flat non‐leaded
QFP
quad flat package
R&D
research and development
RAM
random‐access memory
RCC
resin‐coated copper
RCS
radar cross‐section
RDL
redistribution layer
RF
radio frequency
RFIC
radio frequency integrated circuit
RFID
radio‐frequency identification
RHCP
right‐hand circular polarization
RLCG
resistance, inductance, capacitance, and conductance
RMS
root mean square
RoHS
Restriction of Hazardous Substances Directive
RSM
rotating source method
RX
receiver
SAM
scanning acoustic microscopy
SAP
semi‐additive process
SAR
synthetic aperture radar
SEM
scanning electron microscopy
SG
signal‐ground
SiGe
silicon germanium
SiP
system‐in‐package
SISO
single input, single output
SIW
substrate integrated waveguide
SLA
stereolithography
SLC
surface laminar circuit
SLM
selective laser melting
SLS
selective laser sintering
SMA
sub‐miniature version A
SNR
signal‐to‐noise ratio
SoC
system on chip
SoP
system‐on‐package
SPDR
split post dielectric resonator
SPP
surface plasmon polariton
SRR
split‐ring resonator
SSD
solid state drive
SSMA
small SMA
SUB
subtractive process
TCB
thermocompression bonding
TE
transverse electric
TEM
transverse electro‐magnetic
TEV
through encapsulant via
TFMSL
thin‐film microstrip line
TIM
thermal interface material
TIV
through InFO via
TL
transmission line
TMA
thermomechanical analyzer
TM
transverse magnetic
TMV
through‐mold vias
TPP
two‐photo polymerization
TSMC
Taiwan Semiconductor Manufacturing Company
TSOP
thin small outline package
TSV
through silicon via
TX
transmitter
μvia
microvia
UBM
under bump metallurgy
UHF
ultra‐high frequency
UV
ultraviolet
UWB
ultra‐wideband
VCO
voltage‐controlled oscillator
VGA
variable gain amplifier
VLSI
very‐large‐scale integration
VNA
vector network analyzer
VQFN
very thin quad flat no‐lead
VSWR
voltage standing wave ratio
WGP
wave‐guide port
WiGig
wireless gigabit alliance
WLCSP
wafer level chip scale package
WLP
wafer level package
WPAN
wireless personal area network
WPT
wireless power transfer
WSN
wireless sensor network
Symbols
Ae
effective antenna aperture
c
speed of light
D
directivity
D
= max[
D
(
ϑ
,
ϕ
)]
directivity function
η
effciency
unit vector along the
r
axis
electric field in space frequency
f
frequency
G
gain
G
= max[
G
(
ϑ
,
ϕ
)]
gain function
Γ
reflection coeffcient
I
p
input current antenna
k
coverage factor
L
length of the radiating aperture
λ
0
wavelength in free space
M
v
measurement value
P
in
input power
P
t
total radiated power
P
(
ϑ
,
ϕ
)
normalized radiation power
R
radial distance from the antenna
R
a
resistive
R
L
radiated losses
R
r
radiated resistance
R
v
reference value
μ
sys
system uncertainty
Poynting vector
V
p
input voltage antenna
X
a
reactance
Z
0
characteristic impedance
Z
a
input impedance
Z
g
generator impedance =
R
g
1Introduction
Yueping Zhang
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
1.1 Background
As the technology of choice for integration of digital circuitry, a complementary metal oxide semiconductor (CMOS) was proposed for the integration of analog circuitry for radio frequency (RF) applications in the mid‐1980s, aiming for the ultimate goal of full integration of an entire wireless system on a chip [1]. In the mid‐1990s, the first fully integrated CMOS transceiver for data communications in the 900‐MHz industrial, scientific and medical (ISM) band was successfully demonstrated [2]. Since then, CMOS has been the enabler for wireless systems on chip (SoCs) operating from a few to tens of gigahertz. Figure 1.1 shows the die micrograph of the first wireless SoC, a 2.4‐GHz CMOS mixed RF analog–digital Bluetooth radio announced at the International Solid‐State Circuits Conference (ISSCC) 2001 [3]. The die size is 40.1 mm2. It integrates on the same substrate a low intermediate frequency (IF) receiver, a Cartesian transmitter, a baseband processer, an advanced reduced‐instruction set‐computer machine (ARM) processor, flash memory, and random‐access memory (RAM).
Full SoC integration is clearly not suitable in all cases. In fact, the radio chip is separate in many cases. Traditionally, silicon germanium (SiGe) seems to have been preferred to CMOS for analog RF. Figure 1.2 shows the die micrographs of the first SiGe 60‐GHz transmitter and receiver disclosed at ISSCC 2006 [4]. The die sizes are 4.0 × 1.6 mm2 and 3.4 × 1.7 mm2, respectively. The level of integration achieved in these chips was high then for 60‐GHz radios. The transmitter chip integrates a power amplifier, image‐reject driver, IF‐to‐RF up‐mixer, IF amplifiers, quadrature baseband‐to‐IF mixers, phase‐locked loop (PLL), and frequency tripler. The receiver chip includes an image‐reject low‐noise amplifier, RF‐to‐IF mixer, IF amplifiers, quadrature IF‐to‐baseband mixers, PLL, and frequency tripler. The input/output (I/O) pads are peripheral, with 60 on the transmitter and 53 on the receiver chips.
Figure 1.1
Micrograph of the first 2.4‐GHz CMOS wireless SoC, a Bluetooth radio (from [
3
], © 2001 IEEE, reprinted with permission).
Figure 1.2
Photographs of the first 60‐GHz SiGe radio chipset: (a) transmitter and (b) receiver (from [
4
], © 2006 IEEE, reprinted with permission).
The emergence of wireless SoCs or single‐chip radios called for compatible antenna solutions, which provided an excellent opportunity for researchers of prepared minds to seriously explore the feasibility of integrating an antenna in a chip package using packaging materials and processes in the late 1990s, leading to the development of antenna‐in‐package (AiP) technology [5]. This chapter recounts how AiP technology has been developed to its current state. Section 1.2 describes the idea of AiP with respect to the ideas of antenna on chip (AoC), antenna in module (AiM), antenna on board (AoB), and active integrated antenna (AIA). Section 1.3 reviews the early attempts to explore the idea of AiP. Section 1.4 reflects on the milestones in the development of the idea of AiP into a mainstream antenna and packaging technology. Finally, Section 1.5 gives concluding remarks.
1.2 The Idea
The idea of AiP was triggered by the demand for innovative antenna solutions to wireless SoCs [6]. It features using packaging technology to implement an antenna (or antennas) with a radio or radar die (or dies) in a chip package. It emphasizes only the addition of the unique function of radiation to the package. In this sense, it is different from the concept of system‐in‐package (SiP).
The idea of AoC sounds attractive [7]. It attempts to integrate an antenna (or antennas) with other circuits on a die directly using semiconductor technology. It is obviously a subset of the concept of SoC. Then why do we specifically differentiate it from SoC? The reason is to highlight the unique property of radiation, which is not necessarily being improved like digital circuits as the technology scales down. It is clear that AoC is more suitable for terahertz applications for cost and performance reasons.
The idea of AiM was proposed for multichip 60‐GHz radios [8]. It uses micro‐assembly technology to mount a few monolithic microwave integrated circuits (MMICs) and a small flat antenna in a hermetically sealed package. A window for the propagation of electromagnetic waves is formed above the antenna at the lid of the package. The window is also hermetically sealed.
The idea of AoB is similar to the idea of AiP. However, it relies on printed circuit board (PCB) technology to make an antenna (or antennas) on one surface of a board and to solder a packaged chip (or chips) on the other surface of the board. A few techniques, such as probe feeding or aperture coupling, are available to interconnect the packaged chip with the antenna. Of course, the antenna, the packaged chip, and the necessary feed networks can be contained on the same surface of the board. Recently, the idea of AoB has received considerable attention for millimeter‐wave (mmWave) fifth‐generation (5G) base stations [9].
A typical AIA consists of active devices such as Gunn diodes or transistors that form an active circuit and a planar antenna. The idea of AIA was proposed to eliminate the lossy and bulky interconnect between the active device and radiating element [10]. Later, the idea of AIA was employed for quasi‐optical power combining. The output power from an array of many solid‐state devices was combined in free space to overcome the power limitations of individual solid‐state devices at mmWave frequencies.
Although the origin of the above ideas can be traced back to the invention of microstrip antennas in the early 1970s [11], it should be noted that they extended the concept of microstrip antennas to different levels of integration.
1.3 Exploring the Idea
In this section, the early attempts to explore the idea of AiP are reviewed. It should be mentioned that researchers in university labs devoted their efforts regarding Bluetooth radios to 2.4 GHz or other RF applications, while researchers in company labs focused on 60‐GHz radios and other mmWave applications. At 2.4 GHz, a key challenge was how to miniaturize the antenna size, while at 60 GHz, it was how to minimize the interconnect loss between the die and antenna.
1.3.1 Bluetooth Radio and Other RF Applications
In 1998, Zhang started to work in the Division of Circuits and Systems at the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. The division soon initiated a strategic research project entitled “Software radio on a chip.” Zhang was tasked to develop an antenna technology for the project. Inspired by the structural similarity shared by a microstrip antenna and a microchip, shown in Figure 1.3, and foreseeing the outcome of an interesting antenna solution, Zhang immediately started to investigate the antenna performance of the microchip. First, Zhang did antenna experiments with used microchips, as shown in Figure 1.4a. Then, Zhang tried PCB mock‐ups, as shown in Figure 1.4b. Encouraged by good antenna results from the microchips and PCB mock‐ups, the research team led by Zhang realized more sophisticated designs, as shown in Figure 1.4c,d, with low‐temperature co‐fired ceramic (LTCC) technologies in 2004 [12]. It is interesting to note that differential microstrip patch and meander antennas were designed to suit high‐level integration of wireless SoCs. They were integrated on the top surfaces of two ball grid array (BGA) packages. Both packages had cavities to house wireless SoC dies. The interconnects from the die to the antenna were cascaded bond wires, traces, and vias. The interconnected die was encapsulated with epoxy.
Figure 1.3
Photograph of a microchip.
In 2000, Song et al. at University of Birmingham presented an integrated antenna package [13]. An electrically small feed antenna was designed on a semiconductor substrate, which also supported the RF front‐end circuits. The parasitic radiator placed above the feed antenna also acted as a top cover, sealing the entire package. Later, Song et al. presented another integrated antenna package [14]. A small antenna was embedded within the chip encapsulating material. A parasitic radiator was placed in close proximity to the embedded antenna, where it enhanced the poor gain and bandwidth of the packaged antenna.
In 2001, package engineers started to tackle the same problem. Lim et al. at the Georgia Institute of Technology managed to integrate RF passives, a patch antenna, and chips at the package level to enhance the overall performance of and to add more functionalities to an SoP paradigm [15]. Mathews et al. disclosed a package with an integral shield and antenna for a complete Bluetooth radio design [16].
In 2003, Ryckaert et al. at the Interuniversity Microelectronics Center, Belgium reported the co‐design of circular‐polarized slotted patch antenna with a wireless local area network (WLAN) transceiver in a multilayer package [17]. Popov et al. at the Institute of Microelectronics, Singapore reported the design of part of an RF chip package as a dielectric resonator antenna with a high dielectric constant when the antenna feed was integrated with the rest of the circuitry [18]. Leung at City University of Hong Kong independently proposed adding the chip package function to a dielectric resonator antenna in 2004 [19].
In 2005, Castany et al. at Fractus, Spain filed a patent about the integration of fractal antennas in a chip package [20]. They claimed that fractal antennas could provide very good antenna performance while allowing a high degree of miniaturization and an enhancement of isolation between the antenna and the die in the package.
Figure 1.4
Photographs showing the evolution of the integration of antenna in package: (a) an antenna on a used microchip package, (b) an antenna on a chip package mock‐up, (c) a microstrip patch antenna as an LTCC package, and (d) a microstrip meander antenna as an LTCC package.
In 2006, Brzezina et al. at Carleton University reported planar antennas with transceiver integration capability for ultra‐wideband (UWB) radios [21]. Sun et al. devised a novel technique that reduces the size of a conventional planar antenna by 40% and used it as a package to house a single‐chip UWB radio [22].
In 2007, Wi et al. at Yonsei University, Korea presented an antenna‐integrated package [23]. A modified U‐shaped slot antenna was designed and measured, showing bandwidth of 180 MHz at 5.8 GHz. A parametric study was conducted with a full‐wave electromagnetic solver to determine the critical factors in design and fabrication, as well as to estimate the performance accuracy of the antenna‐integrated package.
