Beyond-CMOS Nanodevices 2 E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 196

Veröffentlichungsjahr: 2014

Beschreibung

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

Leseprobe

Contents

Acknowledgments

General Introduction

Introduction to Volume 2: Silicon Nanowire Bio-Chemical Sensors

1 Small Slope Switches

1.1. Introduction

1.2. Tunnel FETs

1.3. Ferroelectric gate FET

1.4. Bibliography

2 Nanowire Devices

2.1. Introduction

2.2. NW for logic CMOS devices

2.3. Nano-CMOS ultimate memories

2.4. Conclusions

2.5. Acknowledgments

2.6. Bibliography

3 Graphene and 2D Layer Devices for More Moore and More-than-Moore Applications

3.1. Introduction

3.2. Graphene

3.3. 2D materials beyond graphene

3.4. Conclusions

3.5. Acknowledgments

3.6. Bibliography

4 Nanoelectromechanical Switches

4.1. Context

4.2. Nanorelay principles

4.3. Electrostatic nanorelay modeling and optimization

4.4. Technological challenges for NEMS computing

4.5. NEMS-based architectures

4.6. Conclusions

4.7. Bibliography

List of Authors

Index

First published 2014 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.

Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:

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© ISTE Ltd 2014

The rights of Francis Balestra to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988.

Library of Congress Control Number: 2014935738

British Library Cataloguing-in-Publication Data

A CIP record for this book is available from the British Library

ISBN 978-1-84821-655-6

Acknowledgments

We would like to thank all the Partners of the FP7 Nanosil and Nanofunction Networks of Excellence supported by the European Commission and the Members of the European Sinano Institute (www.sinano.eu) for their contributions to these research activities, and Pascale Caulier (Sinano) for her contribution to the realization of this book and “Beyond-CMOS Nanodevices 1”.

General Introduction

Microelectronics, based on complementary metal–oxide semiconductor (CMOS) technology, is the essential hardware enabler for electronic product and service innovation in key growth markets, such as communications, computing, consumer electronics, automotives, avionics, automated manufacturing, health and the environment. The global semiconductor industry underpins 16% of the world’s total economy and is growing every year. The worldwide market for electronic products is estimated to be more than $1,800 billion, and the related electronics services market more than $6,500 billion. These product and service markets are made possible by a $310 billion market for semiconductor components and an associated $90 billion market for semiconductor equipment and materials. The new era of nanoelectronics, which started at the beginning of the current millennium with the smallest patterns in state-of-the-art silicon-based devices below 100 nm, is making an exponential increase in system complexity and functionality possible.

Nanoelectronics allows the development of smart electronic systems by switching, storing, monitoring, receiving and transmitting information. In respect to its societal relevance, the ubiquitous nanoelectronics is also closely linked to the notion of ambient intelligence, which is a vision of the future where people are surrounded by intelligent intuitive interfaces that are embedded in all kinds of objects and an environment that is capable of recognizing and responding to the presence of different individuals in a seamless way.

Since the invention of the transistor in 1947 at Bell Labs, followed by the first silicon transistor in 1954 and the concept of integrated circuits in 1958 at Texas Instruments, progress in the field of microelectronics has been tremendous, which has revolutionized society. In these last 50 years, dramatic advances have been achieved in the packing density of transistors. This has resulted in the density of transistors on an integrated chip (IC) doubling every two years (Moore’s law) since the 1970s. At the beginning of the 1970s, the first microprocessor had only about 2,000 transistors (10 μm gate length), the world’s first two-billion transistor processor was reported in 2008 in 65 nm CMOS technology.

The same trend can be observed for memories. The dynamic random access memory (DRAM) capacity has been raised from 1 kb in 1970 to several Gb at present. Several billion transistor static random access memory (SRAM) chips have also been realized. For nonvolatile memories, 256 Gb have been demonstrated. This increase in transistor count and memory capacity has led to increased processing power, measured now in thousands of millions of instructions per second (MIPS).

Moore’s law also means decreasing cost per function, the transistor price has dropped at an average rate of about 1.5 per year (about 108 since the beginning of the semiconductor industry).

However, according to the International Technology Roadmap for Semiconductors and ENIAC Strategic Research Agenda, there are big challenges to overcome in order to continue progressing in the same direction.

The minimum critical feature size of the elementary nanoelectronic devices (physical gate length of the transistors) will drop into the sub-decananometer range in the next decade. In the sub-10 nm range, “beyond-CMOS” devices, based on nanowires, nanodots, carbon electronics or other nanodevices, will certainly play an important role and could be integrated onto CMOS platforms in order to pursue integration down to nanometer structures. Silicon (Si) will remain the main semiconductor material for the foreseeable future, but the required performance improvements for the end of the roadmap for high performance, low and ultra-low power applications will lead to a substantial enlargement of the number of new materials, technologies, device and circuit architectures.

Therefore, new generations of Nanoelectronic ICs present increasingly formidable multidisciplinary challenges at the most fundamental level (novel materials, new physical phenomena, ultimate technological processes, novel design techniques, etc.).

In this timeframe, performance will also derive from heterogeneity, referring to the increasing diversity of functions integrated onto CMOS platforms as envisaged in the “More than Moore (MtM)” approach.

This book, and the related book Beyond-CMOS Nanodevices 1 (Volume 1), also published by ISTE and Wiley offer a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.

Volume 1 particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced MtM (RF, nanosensors, energy harvesters, on-chip electronic cooling, etc.). This book focuses on beyond-CMOS logic and memory applications.

MtM functions allow the world of digital computing and data storage to interact with the real world. MtM devices typically provide conversion of non-digital as well as non-electronic information, such as mechanical, thermal, acoustic, chemical, optical and biomedical functions, to digital data and vice versa. Clearly MtM technologies and products provide essential functional enrichment to the digital CMOS-based mainstream semiconductors. MtM has become one of the major innovation drivers for a very broad spectrum of societally relevant applications.

There has been increased interest recently for using nanoscale beyond-CMOS devices in the More Moore and MtM domains:

– miniaturization remains a major enabler for price reduction, functionality multiplication and integration with electronics;

– the CMOS technology is facing dramatic challenges for future low power, high performance and memory applications;

– nanoscale beyond-CMOS structures can improve devices’ intrinsic performance and enable new functionalities.

Nanotechnologies will also offer powerful ways to bring added value, in terms of cost, reproducibility, sensitivity, automation, analysis and new functionality in healthcare applications such as in vitro diagnostics or drug delivery, as well as in environment control (water, air, soil), agriculture and food, transport monitoring, ambient intelligence, defense or homeland security. A wide range of sensor types will be required, such as biochemical sensors, sensors for liquid and gas spectroscopy.

As a very good example, nanowires have received much attention from the R&D community as components for electrical circuits based on CMOS compatible processes. Although the R&D activities for nanowires were initiated to address the future need of IC technologies beyond the physical limits of CMOS, more and more R&D activity nowadays is devoted to using nanowires to create innovative MtM products.

Other fields in which nanostructured materials and nanodevices could be of great interest are in the domain of energy-autonomous systems using energy harvesting, for wireless sensor networks, in situ monitoring for mobile systems, body-area networks, biomedical devices or mobile electronics; these systems will become very important in the future for the development of “green/sustainable” applications.

The integration of many different types of devices will be needed – for example, bio-sensors, nanoelectro mechanical structure (NEMS) devices, nanocomponents for logic and memory, energy scavenging systems and RF interfaces, for the development of these future nanoelectronics systems.

This book, and Volume 1, are thus reviewing innovative nanoscale structures that can improve performance and/or enable new functionalities in future terascale ICs and nanosystems. The convergence of More Moore and beyond-CMOS, on one hand, and the merging of MtM and beyond-CMOS, on the other hand, have been extensively studied in scientific literature these last years. The two books are offering a detailed overview of the most recent advances in these fields which have gained strong momentum for many applications.

In the MtM field, very sensitive nanosensors for biological and chemical products, mechanical, solar, thermoelectric energy harvesters, localized cooling on a chip with management of heat transfer using nanostructures and high performance, small size, low cost RF passive components using nanodevices or nanostructured materials are highlighted.

In order to develop future autonomous nanosystems, which will be needed for many applications of high industrial and societal relevance (monitoring of health and environment, internet of things, etc.), the main challenges are the development of CMOS-compatible technologies and using mainly “green” materials, the reduction of the energy consumption of sensors, computing and RF communication, together with the increase in the energy harvested from the environment.

This book, and Volume 1, have been written by scientists from universities and research centers, strongly involved in teaching and research programs related to nanoelectronic devices and circuits. Because of their expertise and international commitment, they are very well informed on the state-of-the-art of the physics and technologies and the evolution of nanoelectronic materials, components, circuits and systems.

Part 1, Volume 1, reviews the nanosensing field, including Si nanowire: biochemical sensors, fabrication of nanowires, functionalization techniques, sensitivity, integration of SiNWs with CMOS, and portable system for real-time impedimetric measurements on nanowires biosensors.

Part 2, Volume 1, outlines new materials, nanodevices and technologies for energy harvesting, dedicated to vibrational energy harvesting (piezoelectric and electromagnetic energy transducers), thermal energy harvesting (thermal transport at nanoscale, porous silicon for thermal insulation on silicon wafers, spin dependent thermoelectric effects, composites of thermal shape memory alloy and piezoelectric materials), Nanowire based solar cells, and smart energy management and conversion (power management solutions for energy harvesting devices, sub-mW energy storage solutions).

Part 3, Volume 1, highlights on-chip electronic cooling, including silicon based cooling elements (Schottky barrier junctions, strained silicon Schottky barrier mK coolers, silicon mK coolers with an oxide barrier, silicon cold electron bolometer, integration of detector and electronics), thermal isolation through nanostructuring (lattice cooling by physical nanostructuring, porous silicon platforms, crystalline membrane platforms) and tunnel junction electronic coolers.

Part 4, Volume 1, addresses new materials, nanodevices and technologies for RF applications, devoted to substrate technologies for silicon-integrated RF and mm-wave passives, metal nanolines and antennas for RF and mm-wave applications, and nanostructured magnetic materials (nano-composite materials, nanomodulated continuous films) for high frequency applications.

This volume gives an overview of beyond-CMOS nanodevices for logic and memories applications, including small slope switches (tunnel field effect transistor (FET), ferroelectric gate FET, NEMS), nanowires (ultimate CMOS, ultimate memories with new solutions offered by nanowire technologies in terms of charge storage and resistive change types), 2D layers and devices for More Moore and MtM (graphene and other 2D materials).

Francis BalestraApril 2014

Introduction to Volume 2: Silicon Nanowire Bio-Chemical Sensors

Introduction written by Francis Balestra.

Volume 2 gives an overview of beyond complementary metal oxide semiconductor (CMOS) nanodevices for logic and memories applications, including small slope switches (Tunnel field effect transistor (FET), Ferroelectric (Fe) gate FET and Nano-Electro-Mechanical-Structures (NEMS)), Nanowires (NWs) (Ultimate CMOS, NanoCMOS Ultimate Memories) and two-dimensional (2D) layers and devices for More Moore and More-than-Moore (graphene and other 2D materials).

Chapter 1, Volume 2 addresses the dramatic challenges associated with accelerated energy consumption and heating, and the move from a constant field toward a near constant voltage scaling. Indeed, in 2005, the increase in microprocessor frequency abruptly ceased, but the integration level continued to increase and parallel processors were proposed. Thus, today we are facing dramatic challenges dealing with the limits of energy consumption (static + dynamic) and heat removal, inducing fundamental trade-offs for the future integrated circuits (ICs). The researches on ultimate reduction of computation dissipation are strongly needed for the development of future high-performance terascale integration and autonomous (nano) systems. The introduction reviews the main challenges, limits and possible solutions for strongly reducing the energy per binary switching. Several paths are possible: the adiabatic logic using a slow clock, logic stochastic resonance, feedback-controlled dynamic gate, nanoelectromechanical switches or conventional logic with a reduction in the stored energy, therefore, a decrease of device capacitance C (device integration) or applied bias Vdd, which seem to be the most promising for future ICs.

Indeed, the reduction of the stored energy in conventional logic can be done with a strong reduction in Vdd using new physics and/or devices with sub-60 mV/dec subthreshold swing S, in particular with the main following concepts: energy filtering (Tunnel FET, with metal-oxide-semiconductor (MOS)-NW-CNT or graphene, using band-to-band tunneling to filter energy distribution of electrons in the source, or NW FET with superlattice (e.g. InGaAs-InAlAs) hetererostructure in the source), internal voltage step-up (Ferroelectric gate FET, inducing a negative capacitance to amplify the change in channel potential induced by the gate), NEMS, or Impact Ionization MOS devices.

We will focus here on the best ones, Tunnel FETs, Fe FETs and NEMS, which could lead to ultrashort channel devices with a strong reduction of the applied bias, together with very good performance and reliability.

Chapter 2, Volume 2 will be devoted to Silicon-based NW metal-oxide-semiconductor field effect transistors (MOSFETs), which are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. Both the top–down and the bottom–up approaches are widely studied for the fabrication of NW MOSFET transistors. We will give some highlights of silicon NW MOSFET both in terms of fabrication challenges based on top-down approach, which is probably today the most commonly investigated option by the microelectronic industry and in terms of quantum simulation and electrical characterization issues.

Moreover, semiconductor memories are electronic data storage devices based on MOS technology. There are various types of semiconductor memories that can be grouped into two basic categories: (1) volatile memory that requires power to retain the data content such as Dynamic Random-Access Memory (DRAM) and Static Random-Access Memory (SRAM) and (2) non-volatile memory (NVM), which is able to retain stored information even without power such as floating-gate memory. We will focus on the new solutions for NVM technologies offered by NW technologies in terms of both charge storage and resistive change types.

Chapter 3, Volume 2 will review the current status of graphene and other 2D transistors as potential supplement to silicon CMOS technology, for More Moore and More-Than-Moore applications. An overview of graphene manufacturing and metrology methods is followed by a discussion of macroscopic and nanoribbon graphene FETs. Graphene FETs are shown to be of interest for analog radio frequency applications. Recent discoveries of non-classic switching mechanisms or tunneling-based devices may eventually lead to a cointegration of graphene into silicon technology.

Chapter 4, Volume 2 gives an overview of the use of NEMS for small slope switches. NEMS-based technology may be considered as a long term solution for ultralow power electronics. This chapter investigates the nanorelay principles, the logic operation being performed by the control of a movable structure. The switch is composed of an actuation mechanism and a mechanical contact. Four mechanisms are considered for actuation: the electrostatic actuation, the piezoelectrical actuation, the magnetic actuation and the thermal actuation. The technology challenges for NEMS computing are also addressed. Two challenges are identified: the low voltage operation in order to reduce the active power and the reliability of electrical contacts. Finally, the NEMS-based architectures, conventional and adiabatic, are discussed.

1

Small Slope Switches

Chapter written by Adrian M. Ionescu, Francis Balestra, Kathy Boucart, Giovanni Salvatore and Alexandru Rusu.

1.1. Introduction

Power dissipation in switching devices is considered today as the most important roadblock for future nanoelectronic circuits and systems [SAK 04]. The complementary metal-oxide-semiconductor (CMOS) power consumption consists of two contributions: the dynamic and the static leakage components. In the past, the power increase was due to the different scaling factors for the voltage supply and the device geometry being essentially dominated by the dynamic power. Added to the dynamic power, there is an additional power component, the subthreshold leakage, which starts to dominate for advanced technology nodes and practically limits the supply voltage of modern integrated chip (IC) to a lower limit of 0.5 V. As the technology nodes scale, we have to use a lower supply voltage and, as the threshold voltages are reduced, the leakage or off current, Ioff, becomes dominant because the subthreshold swing, S, of a metal-oxide-semiconductor field-effect transistor (MOSFET) is unscalable and tied to the thermal value of 60 mV/decade at room temperature [GOP 05]. This refers to the gate voltage required to change the drain current by one order of magnitude when the transistor is operated in subthreshold and is defined by

[1.1]

Another solution to lower S is to reduce below 1 the body factor, m, in equation [1.1]. This can be achieved by using the recently proposed negative capacitance effect [RED 95, KOG 96, HAN 00] or by using electromechanical gates [AYD 04] (with a movable electrode) where instability points between electrical and mechanical forces are used to define infinitely abrupt transitions between off and on states in micro/nanoelectromechanical (M/NEM) relays.

1.2. Tunnel FETs1

Compared to other steep slope devices, tunnel FETs seem today the most promising abrupt switches; they do not suffer from the reliability problems such as the impact ionization abrupt switches, I-MOS and the nanoelectromechanical (NEM) relays. Moreover, in both I-MOS and NEM relay, the voltage scaling below 1 V is extremely challenging, being limited not only by the device engineering but also by their fundamental physics.

The basic design of tunnel FET is a gated p-i-n diode where the band-to-band tunneling takes place between the intrinsic and p+ regions, for n-type devices (see Figure 1.1). To operate tunnel FET devices, the p-i-n diode is reverse-biased (for the energy band simulations reported in Figure 1.1, the source is grounded and positive voltages are applied to the drain and to the gate). With a zero gate voltage, the width of the energy barrier between the intrinsic region and the p+ region is wide (larger than 10 nm, one approximate minimum usually adopted for defining the limit of a significant tunneling probability), and the device is in the OFF-state. As the positive gate voltage increases, the bands in the intrinsic region are pushed down in energy, narrowing the tunneling barrier and allowing tunneling current to flow.

Figure 1.1.Principle of tunnel FET and corresponding energy band diagrams in OFF and ON states with their control by the gate voltage

The tunnel MOSFET offers an appealing concept for a substantial lowering of the energy dissipated in a switching device by replacing the thermionic emission of charge carriers over a barrier to enter the MOSFET channel with a tunneling process. If the tunneling process is made sufficiently effective, tunnel FETs can ultimately yield an effective cooling of the injecting source contact through a band-pass filter action that enables steep inverse subthreshold slopes over many orders of magnitude, thus providing low values of the average subthreshold swing, SSavg.

Some of the first-tunnel FETs were proposed in 1978 followed by a small number of subsequent publications dealing with silicon and III–V surface tunnel transistors. Since approximately 2000, the field has been rapidly evolving and, recently, tunnel FETs have attracted an increasing amount of interest due to their potential ability to enable switching with an inverse subthreshold slope steeper than 60 mV/dec. The following list of categories shows the most important contributions to the field and the present state-of-the-art of tunnel FETs.

First, realizations of interband tunneling transistors.– Quinn et al. at Brown University [QUI 78], were the first to propose the gated p-i-n structure of a Tunnel FET in 1978, and suggested the usefulness of this device for spectroscopy. Banerjee et al. [BAN 87] studied the behavior of a three-terminal silicon tunnel device, and Takeda et al. [TAK 88] showed the lack of VT roll-off when scaling. Baba fabricated tunnel FETs, which he called surface tunnel transistors in III–V materials [BAB 92]. In 1995, Reddick and Amaratunga published measured characteristics of silicon surface tunnel transistors [RED 95]. In 1997, Koga and Toriumi proposed a post-CMOS three-terminal forward-biased silicon tunneling device [KOG 96]. In 2000, Hansch et al. reported experimental results from a reverse-biased vertical silicon tunneling transistor made with MBE with a highly-doped boron delta-layer and noted the saturation behavior in the ID-VG characteristics [HAN 00]. Aydin et al. fabricated Lateral Interband Tunneling Transistors on silicon-on-insulator (SOI) in 2004 [AYD 04]. These devices were like tunnel FETs with no intrinsic region and the gate over a p-n junction, aiming to reduce gate capacitance and therefore increase speed. As a particular feature, the authors claim that there should be no current saturation for these devices.

Tunnel FETs in the Si/SiGe material system.– In 2004, Bhuwalka et al. published the first of many articles about their vertical tunnel FET on silicon with a SiGe delta layer, grown by MBE [BHU 04]. The SiGe replaced the silicon delta layer already used by Hansch, and, in theory, the smaller bandgap reduces the tunnel barrier width and increases tunneling current in the on-state as well as lowering the subthreshold swing. In 2006, the same group proposed a lateral tunnel FET on SiGe-on-insulator, and showed through simulation that on-current would increase with the percentage of Ge in the SiGe [BHU 06].

In 2007, Boucart and Ionescu showed the first comprehensive numerical simulations of Si tunnel FETs with a high-k