Chemistry in Microelectronics E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 559

Veröffentlichungsjahr: 2013

Beschreibung

Microelectronics is a complex world where many sciences need to collaborate to create nano-objects: we need expertise in electronics, microelectronics, physics, optics and mechanics also crossing into chemistry, electrochemistry, as well as biology, biochemistry and medicine. Chemistry is involved in many fields from materials, chemicals, gases, liquids or salts, the basics of reactions and equilibrium, to the optimized cleaning of surfaces and selective etching of specific layers. In addition, over recent decades, the size of the transistors has been drastically reduced while the functionality of circuits has increased. This book consists of five chapters covering the chemicals and sequences used in processing, from cleaning to etching, the role and impact of their purity, along with the materials used in "Front End Of the Line" which corresponds to the heart and performance of individual transistors, then moving on to the "Back End Of the Line" which is related to the interconnection of all the transistors. Finally, the need for specific functionalization also requires key knowledge on surface treatments and chemical management to allow new applications. Contents 1. Chemistry in the "Front End of the Line" (FEOL): Deposits, Gate Stacks, Epitaxy and Contacts, François Martin, Jean-Michel Hartmann, Véronique Carron and Yannick Le Tiec. 2. Chemistry in Interconnects, Vincent Jousseaume, Paul-Henri Haumesser, Carole Pernel, Jeffery Butterbaugh, Sylvain Maîtrejean and Didier Louis. 3. The Chemistry of Wet Surface Preparation: Cleaning, Etching and Drying, Yannick Le Tiec and Martin Knotter. 4. The Use and Management of Chemical Fluids in Microelectronics, Christiane Gottschalk, Kevin Mclaughlin, Julie Cren, Catherine Peyne and Patrick Valenti. 5. Surface Functionalization for Micro- and Nanosystems: Application to Biosensors, Antoine Hoang, Gilles Marchand, Guillaume Nonglaton, Isabelle Texier-Nogues and Francoise Vinet. About the Authors Yannick Le Tiec is a technical expert at CEA-Leti, Minatec since 2002. He is a CEA-Leti assignee at IBM, Albany (NY) to develop the advanced 14 nm CMOS node and the FDSOI technology. He held different technical positions from the advanced 300 mm SOI CMOS pilot line to different assignments within SOITEC for advanced wafer development and later within INES to optimize solar cell ramp-up and yield. He has been part of the ITRS Front End technical working group at ITRS since 2008.

Leseprobe

Contents

Preface

Chapter 1 Chemistry in the “Front End of the Line” (FEOL): Deposits, Gate Stacks, Epitaxy and Contacts

1.1. Introduction

1.2. Arrangement of the gate

1.3. Chemistry of crystalline materials

1.4. Contact areas between the gate and the “source” and “drain”

1.5. General conclusion

1.6. List of Abbreviations

1.7. Bibliography

Chapter 2 Chemistry in Interconnects

2.1. Introduction

2.2. Interconnects: generalities and background

2.3. Dielectric deposits

2.4. Deposition and properties of metal layers for interconnect structures

2.5. Cleaning process for copper interconnects

2.6. General conclusions and perspectives

2.7. List of Abbreviations

2.8. Bibliography

Chapter 3 The Chemistry of Wet Surface Preparation: Cleaning, Etching and Drying

3.1. Introduction

3.2. Cleaning

3.3. Wet etching

3.4. Rinsing and drying

3.5. Conclusion

3.6. List of Abbreviations

3.7. Bibliography

Chapter 4 The Use and Management of Chemical Fluids in Microelectronics

4.1. Ultrapure water

4.2. Gases for semiconductors

4.3. Dissolved gases

4.4. High-purity chemicals

4.5. Waste management

4.6. List of Abbreviations

4.7. Bibliography

Chapter 5 Surface Functionalization for Micro- and Nanosystems: Application to Biosensors

5.1. Introduction

5.2. Materials

5.3. Functionalization process

5.4. Molecule and macromolecule immobilization

5.5. Analytes capture

5.6. Conclusion

5.7. List of Abbreviations

5.8. Bibliography

List of Authors

Index

First published 2013 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.

Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:

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© ISTE Ltd 2013

The rights of Yannick Le Tiec to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988.

Library of Congress Control Number: 2012955113

British Library Cataloguing-in-Publication Data

A CIP record for this book is available from the British Library

ISBN: 978-1-84821-436-1

Preface

Over the last few decades, the size of transistors has been drastically shrunk although functionality of their circuits has increased. The physics models have been widely investigated and corrected to take into account physical phenomena happening for very small features. The chemistries used for surface preparation have long been considered as black boxes. Materials consumption has seriously been impacting on transistor performance pushing the engineering teams to develop new alternative chemical mixtures and sequences. At the same time over recent years, the metrology made huge progress, allowing a better characterization and understanding of the phenomena.

This book is divided into five chapters to analyze the role of chemistry in the fabrication of advanced transistors: the chemicals and sequences used in processing, from cleaning to etching, the role and impact of the purity of the sources and materials used in “front end of the line (FEOL)” which correspond to the “heart” and performance of individual transistors, moving further to the “back end of the line” (BEOL) which is related to the interconnection of all the transistors designed earlier during the FEOL processing steps. Finally, the need of specific functionalization also requires key knowledge in surface treatments and chemical management, allowing applications like biosensors to develop new nanosystems. A new era is widely opening with the convergence of electronics and biology.

Chapter 1 allows the reader to enter the fascinating world of the FEOL, which can be considered as the place where the heart of the transistor is manufactured. Many domains are pretty important to properly optimize the transistor performance: from doping level and profile to capacitance and junction consideration, optimized integration of new materials in terms of nature, properties and thicknesses. In this chapter, the focus is on three key modules: the gate stack definition, the crystalline materials involved in source–drain areas and the contacts definition. These key elements will give a transistor its final performance either being on the “high performance” side or being on the “low power” side. The gate stack optimization is mandatory and material choice is very impacting in this area: a careful choice of the best precursors for the deposited materials is necessary. Material science is also much involved not only in the gate area but also in the two main parts of the transistor that are source and drain areas. Optimized undoped (or more recently in situ doped) monocrystalline materials have to be deposited on these areas and a few steps later, specific contacts have then to be realized.

Chapter 2 brings the reader to the next step, which is the understanding of the interconnection between transistors themselves, which is called the BEOL. This chapter covers the aspects of optimizing the material properties so that a given transistor will be able to switch as quickly as requested, even if the signal needs to move through many metal layers of interconnection. Today, in most advanced technologies, there are up to 13 metal levels, which allow connection between a few billions of transistors on “first – ground – floor or level 0”. The chip can be assimilated to a building (like a tower) with an ever smaller surface as a base and ever higher height adding new floors, up to 13 today. Engineering teams have then to design all the interconnections inside such a tower building which could be seen as putting in place the right stairs, elevators, rooms, etc., so that carriers (electrons or holes) can move as fast as possible from one point to other of that building.

Chapter 3 covers the main aspects of the surface preparation that are used in the current industry and research laboratories. Since 1970, wet cleaning is a key driver when advanced technologies request new answers: alternate materials have been introduced to address the following nodes. Over the last 10 years, the specification list given to the cleaning experts is getting new criteria and, today, there are key focuses concerning material consumption or loss, as well as selectivity between materials during chemical exposure. Basic chemistries are revisited to address new competing materials because the “standard” semiconductor silicon surface/substrate is now challenged by germanium, silicon-germanium, and III–V compounds, among others. The main chemical reaction is still about oxidation and reduction or acidic and basic, then there comes the solution of multiple equation systems. This is nothing new to chemical science; only the theoretical approach of the basic knowledge used for years has to be carefully applied to address the future challenges in transistor technology. In successive sections, the chapter describes the cleaning, the etching and the final rinsing-drying sequence: mechanisms, chemical reactions, impact of concentration and temperature are reported.

Chapter 4 describes the use and management of chemical fluids in microelectronics. The production of semiconductor devices is extremely sensitive toward any presence of traces of organic or metallic contamination. Undesired impurities must be kept at very low levels. Hence, it is important for all production steps, starting already with the resourcing of chemicals, for example ultrapure water, gases and liquid chemicals. As device line widths continue to shrink, the requirement for ever higher water purities in semiconductor applications is expected to increase. Techniques to clean these chemicals, control them to the desired concentration and, finally, the treatment of waste water and gas abatement are covered. The chapter also presents unique problems for liquid and gas production as well as quality analysis with the outlook of reducing the overall consumption.

Chapter 5 provides information regarding the surface functionalization for micro- and nanosystems, which are natural extensions of microelectronics and are now found in many convergent applications. Different materials are being investigated, from metal oxides, semiconductors, carbon nanotubes; silicon nanowires, metals or polymers. The functionalization processes are described: activation, cleaning, plasma treatments, chemical vapor deposition, sol-gel and polymer deposition techniques. Localization processes are also discussed: spotting, photolithography, scanning beam lithography, microcontact printing, etc. Mechanisms are explained, chemical reactions and related applications are detailed. This final chapter is a fascinating one to complete the book with, describing some interactions between chemistry and microelectronics.

After this technical outline, let me finally express my thanks for the commitment and considerable work of each coauthor who spent many hours carefully describing their expertise and picking up the most relevant references to his domain. The reader will find many relevant references at the end of each chapter (around 700 references in total throughout the book) including the most recent ones. I also would like to thank the editor for giving us the opportunity to edit this book and for his great support during the review periods making possible this first edition. On behalf of all coauthors, follow us into the inside of the nanochemistry world.

Yannick LE TIECJanuary 2013

Chapter 1

Chemistry in the “Front End of the Line” (FEOL): Deposits, Gate Stacks, Epitaxy and Contacts

1.1. Introduction

The manufacturing of a transistor involves several hundred production and control stages and is a process that takes several weeks, generally between four and twelve depending on the complexity of the electronic component. Production is considered to be either “front end” or “back end”.

A “front end” plant will produce a component consisting of between hundreds of millions and several billion transistors, all interconnected via different stages. Today the most advanced technologies with 20 nm nodes use between eleven and thirteen metal levels to interconnect several billion transistors by means of a specific map that is determined by the feature of the component. The component is tested and the functional chips are identified and selected in order to calculate what is known as the yield, that is the number of chips made to specifications versus the total number made. A “back end” plant will receive the “front end” components and finalize the packaging through a second pathway and specific processes. Tests then guarantee the reliability of the component, generally over a period of 10–20 years.

In the “front end” plant, the manufacturing of the component is itself divided into two main sectors: first, the “front end of the line” (FEOL), which could be considered as the technological heart of the operation. It involves the extreme optimization of each individual transistor: dimensioning, type (N or P), arrangement, characteristic (high performance or low consumption, for example) and application (logic, analog, etc.). The second area of manufacturing is known as the “back-end of the line” (BEOL) and will be explained in Chapter 2 of this book, simplified, its aim is to optimize the interconnection of the individual transistors made by the FEOL sector.

This chapter focuses on the FEOL sector: it can be divided into several subsectors of activity; through processes, we will successively list zones for deposition, mechanical–chemical polishing, dry and wet etching, surface preparation/cleaning, doping or lithography. For each technological node, there are groups of experts aiming to define the specifications required for these different processes, in order to obtain the desired features for various applications. This is done by the international group, International Technology Roadmap for Semiconductors (ITRS) [ITR 12].

A modern transistor must address the various technological aspects that are shown in Figure 1.1. The challenges concern the starting material “A” (generally silicon, eventually modified to a version called silicon on insulator (SOI) corresponding to an ingenious Si/SiO2/Si stack where the highest active layer of silicon is isolated from the substrate by an embedded layer of oxide), the insulation between the transistors (B), the determination of the dopant profiles (target addressed by points C, E and G), the gate stack (D and F), the contact zones of the gate as well as the “Source” and “Drain” zones of the transistor (H and I), etc. [ITR 11].

This chapter describes three important elements. In Figure 1.1, these are described mainly by points F, H and I, and somewhat by D and E as well. First, the chemistry involved in the gate stack is described as this is directly related to a fine tuning of the transistor: the optimization of the gate insulator and the gate itself. The choice of the chemical precursors is of key importance. Next, crystalline heterostructures (based on SiGe in particular) are explained and the involvement of the precursors, temperature, pressure and surface preparation is detailed. Finally, the chemistry involved to address efficient contacts is also precisely described.

Figure 1.1.The challenges of the “front end of the line” as defined by the ITRS [ITR 11]

1.2. Arrangement of the gate

1.2.1. Generalities

After the discovery of the planar structure in the 1960s, for a long time the gate stack of the metal oxide semiconductor (MOS) transistors was made of a silicon (SiO2) insulator covered by a gate for the channel control (itself made of N and P doped polycrystalline silicon). Looking at the chemical processes used in the production of this stack, first a thermal oxidation of the silicon takes place in the heat treatment furnace containing several tens of wafers (reaction [1.1]). Then the silicon gate is deposited by chemical deposition in the vapor phase low pressure chemical vapor deposition (LPCVD) from silane in a furnace under vacuum (reaction [1.2]).

[1.1]

[1.2]

For dimensions of about 0.18 μm and smaller, additional constraints arose: the continuation of transistor size scaling fixed the thickness of the insulation gate (Moore’s Law) and while the current tunnel through the oxide increased drastically, the boron doping diffused from the P-type metal-oxide semiconductor (PMOS) side through the gate insulator to the transistor’s channel. This chapter will explain how scientists first improved the properties of the silicon oxide, before introducing into the 45 to 28 nm nodes an innovation that would replace a large part of SiO by a high-permittivity insulator, known as “High K”: by depositing a greater thickness of a material with a higher permittivity, the leakage current is indeed reduced without adversely affecting the capacitive coupling. To guarantee a greater physicochemical compatibility with the High K material as well as an optimal capacitive coupling, the second major innovation was to deposit a metal gate, rather than a gate made from doped polycrystalline silicon. The latter had the disadvantage of having a slightly depleted interface doping, adding a parasitic capacity, which adversely affected the transistor’s performance. In this section, the chemical mechanisms that come into play inside the fine layers of the gate stacks will be defined as well as the precursors used for depositing the films in the manufacturing environment. The motivation behind the choice of the High K material and the interaction with its environment will only be described briefly (for more information, the reader may refer to review papers about this topic) [WIL 01, LOC 06, CHO 11].