CMOS Sigma-Delta Converters E-Book

José M. de la Rosa

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: Wiley - IEEE
• Sprache: Englisch

Seitenzahl: 581

Veröffentlichungsjahr: 2013

Beschreibung

A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance.

This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations − going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues – from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence Design FrameWork II. As well as being a comprehensive reference to the theory, the book is also unique in that it gives special importance on practical issues, giving a detailed description of the different steps that constitute the whole design flow of sigma-delta ADCs.  

The book begins with an introductory survey of sigma-delta modulators, their fundamentals architectures and synthesis methods covered in Chapter 1. In Chapter 2, the effect of main circuit error mechanisms is analysed, providing the necessary understanding of the main practical issues affecting the performance of sigma-delta modulators. The knowledge derived from the first two chapters is presented in the book as an essential part of the systematic top-down/bottom-up synthesis methodology of sigma-delta modulators described in Chapter 3, where a time-domain behavioural simulator named SIMSIDES is described and applied to the high-level design and verification of sigma-delta ADCs. Chapter 4 moves farther down from system-level to the circuit and physical level, providing a number of design recommendations and practical recipes to complete the design flow of sigma-delta modulators. To conclude the book, Chapter 5 gives an overview of the state-of-the-art sigma-delta ADCs, which are exhaustively analysed in order to extract practical design guidelines and to identify the incoming trends, design challenges as well as practical solutions proposed by cutting-edge designs.

• Offers a complete survey of sigma-delta modulator architectures from fundamentals to state-of-the art topologies, considering both switched-capacitor and continuous-time circuit implementations
• Gives a systematic analysis and practical design guide of sigma-delta modulators, from a top-down/bottom-up perspective, including mathematical models and analytical procedures, behavioural modeling in MATLAB/SIMULINK, macromodeling, and circuit-level implementation in Cadence Design FrameWork II, chip prototyping, and experimental characterization.
• Systematic compilation of cutting-edge sigma-delta modulators
• Complete description of SIMSIDES, a time-domain behavioural simulator implemented in MATLAB/SIMULINK
• Plenty of examples, case studies, and simulation test benches, covering the different stages of the design flow of sigma-delta modulators
• A number of electronic resources, including SIMSIDES, the statistical data used in the state-of-the-art survey, as well as many design examples and test benches are hosted on a companion website

Essential reading for Researchers and electronics engineering practitioners interested in the design of high-performance data converters integrated in nanometer CMOS technologies; mixed-signal designers.

Leseprobe

Table of Contents

Title Page

Copyright

Dedication

Praise Page

List of Abbreviations

Preface

References

Acknowledgements

Chapter 1: Introduction to ΣΔ Modulators: Basic Concepts and Fundamentals

1.1 Basics of A/D Conversion

1.2 Basics of Sigma-Delta Modulators

1.3 Classification of ΣΔ Modulators

1.4 Single-Loop ΣΔ Modulators

1.5 Cascade ΣΔ Modulators

1.6 Multibit ΣΔ Modulators

1.7 Band-Pass ΣΔ Modulators

1.8 Continuous-Time ΣΔ Modulators

1.9 Summary

References

Chapter 2: Circuits and Errors: Systematic Analysis and Practical Design Issues

2.1 Nonidealities in Switched-Capacitor ΣΔ Modulators

2.2 Finite Amplifier Gain in SC-ΣΔMs

2.3 Capacitor Mismatch in SC-ΣΔMs

2.4 Integrator Settling Error in SC-ΣΔMs

2.5 Circuit Noise in SC-ΣΔMs

2.6 Clock Jitter in SC-ΣΔMs

2.7 Sources of Distortion in SC-ΣΔMs

2.8 Nonidealities in Continuous-Time ΣΔ Modulators

2.9 Clock Jitter in CT-ΣΔMs

2.10 Excess Loop Delay in CT-ΣΔMs

2.11 Quantizer Metastability in CT-ΣΔMs

2.12 Finite Amplifier Gain in CT-ΣΔMs

2.13 Time-Constant Error in CT-ΣΔMs

2.14 Finite Integrator Dynamics in CT-ΣΔMs

2.15 Circuit Noise in CT-ΣΔMs

2.16 Sources of Distortion in CT-ΣΔMs

2.17 Case Study: High-Level Sizing of a ΣΔM

2.18 Summary

References

Chapter 3: Behavioral Modeling and High-Level Simulation

3.1 Systematic Design Methodology of ΣΔ Modulators

3.2 Simulation Approaches for the High-Level Evaluation of ΣΔMs

3.3 Implementing ΣΔM Behavioral Models

3.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C-MEX S-Functions

3.5 SIMSIDES: A SIMULINK-Based Behavioral Simulator for ΣΔMs

3.6 Using SIMSIDES for the High-Level Sizing and Verification of ΣΔMs

3.7 Summary

References

Chapter 4: Circuit-Level Design, Implementation, and Verification

4.1 Macromodeling ΣΔMs

4.2 Including Noise in Transient Electrical Simulations of ΣΔMs

4.3 Processing ΣΔM Output Results of Electrical Simulations

4.4 Design Considerations and Simulation Test Benches of ΣΔM Basic Building Blocks

4.5 Auxiliary ΣΔM Building Blocks

4.6 Layout Design, Floorplanning, and Practical Issues

4.7 Chip Package, Test PCB, and Experimental Set-Up

4.8 Summary

References

Chapter 5: Frontiers of ΣΔ Modulators: Trends and Challenges

5.1 Overview of the State of the Art on ΣΔMs

5.2 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs

5.3 Cutting-Edge ΣΔM Architectures and Techniques

5.4 Classification of State-of-the-Art References

5.5 Summary

References

A: SIMSIDES User Guide

A.1 Getting Started: Installing and Running SIMSIDES

A.2 Building and Editing ΣΔM Architectures in SIMSIDES

A.3 Analyzing ΣΔMs in SIMSIDES

A.4 Example

A.5 Getting Help

B: SIMSIDES Block Libraries and Models

B.1 Overview of SIMSIDES Libraries

B.2 Ideal Libraries

B.3 Real SC Building-Block Libraries

B.4 Real SI Building-Block Libraries

B.5 Real CT Building-Block Libraries

B.6 Real Quantizers and Comparators

B.7 Real D/A Converters

B.8 Auxiliary Blocks

Index

This edition first published 2013

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Library of Congress Cataloging-in-Publication Data

Rosa, Jose M. de la.

CMOS sigma-delta converters : practical design guide / Jose M. de la Rosa and

Rocio del Rio.

pages cm

Includes bibliographical references and index.

ISBN 978-1-119-97925-8 (hardback : alk. paper) — ISBN 978-1-118-56922-1

(ebook/epdf) — ISBN 978-1-118-56843-9 (epub) — ISBN 978-1-118-56842-2 (mobi)—

ISBN 978-1-118-56923-8 1. Metal oxide semiconductors, Complementary— Design and

construction. I. Title.

TK7871.99.M44R668 2013

621.3815′9— dc23

2012041956

ISBN: 978-1-119-97925-8

This book is dedicated to the memory of my son José Manuel

José M. de la Rosa

To my wife Visi, my daughter María, my son Jaime, my parents Carmen and Juan, and my parents-in-law María Luisa and José Antonio

José M. de la Rosa

To my husband Juanan and my son Mario

Rocío del Río

“If you love what you do and are willing to do what it takes, it's within your reach. And it'll be worth every minute you spend alone at night, thinking and thinking about what it is you want to design or build. It'll be worth it, I promise.”

Steve Wozniak (iWoz, 2006)

List of Abbreviations

Sigma-delta

M

Sigma-delta modulator

AAF

Antialiasing filter

AC

Alternate current

A/D

Analog-to-digital

ADC

Analog-to-digital converter

ADSL

Asymmetric digital subscriber line

AMPS

Advanced mobile phone system

ASIC

Application-specific integrated circuit

BB

Baseband

BE

Backward-Euler

BGA

Ball grid array

BP

Band-pass

BP-M

Band-pass sigma-delta modulator

BPF

Band-pass filter

CAD

Circuit aided design

CDMA

Code division multiple access

CDS

Correlated double sampling

CLA

Clocked averaging

CMFB

Common-mode feedback

CMOS

Complementary MOSFET

CPU

Central processing unit

CS

Current-steering

CT

Continuous-time

CT-M

Continuous-time sigma-delta modulator

D/A

Digital-to-analog

DAC

Digital-to-analog converter

DC

Direct current

DCL

Digital cancelation logic

DEM

Dynamic element matching

DMT

Discrete multitone

DNL

Differential nonlinearity

DOR

Digital output rate

DR

Dynamic range

DRC

Design rule checker

DSP

Digital signal processor

DT

Discrete-time

DT-M

Discrete-time sigma-delta modulator

DVB

Digital video broadcasting

DVB-H

Digital video broadcasting - handheld

DWA

Data weighted averaging

EDGE

Enhanced data-rates for global evolution

ELD

Excess loop delay

ENOB

Effective number of bits

ESD

Electrostatic discharge

FE

Forward-Euler

FFT

Fast Fourier transform

FIR

Finite impulse response

FOM

Figure of merit

FS

Full scale

GB

Gain-bandwidth product

GPS

Global positioning system

GSM

Global system for mobile communications

GUI

Graphic user interface

H-M

Hybrid sigma-delta modulator

HD

Harmonic distortion

HDL

Hardware description language

HRZ

Half-delay return-to-zero

IBN

In-band noise power

IC

Integrated circuit

IF

Intermediate frequency

IIP

Input-referred intercept point

IIR

Infinite impulse response

IIT

Impulse-invariant transformation

ILA

Individual level averaging

IM

Intermodulation distortion

INL

Integral nonlinearity

I/O

Input–output

I/Q

Inphase/quadrature

ISI

Intersymbol interference

ITF

Integrator transfer function

LDI

Lossless discrete integrator

LNA

Low-noise amplifier

LP

Low-pass

LP-M

Low-pass sigma-delta modulator

LPE

Layout parasitic extractor

LPF

Low-pass filter

LSB

Least significant bit

LTE

Long term evolution

LTCC

Low-temperature co-fired ceramic

LTI

Linear time-invariant

LVS

Layout versus schematic

MASH

Multistage noise shaping

MEX

MATLAB executable

MiM

Metal-insulator-metal

MoM

Metal-oxide-metal

MOS

Metal-oxide-semiconductor

MOSFET

MOS field-effect transistor

MOST

MOS transistor

MR

Multirate

MR-M

Multirate sigma-delta modulator

MTPR

Multitone power ratio

nMOS

n-channel MOSFET

NRZ

Nonreturn-to-zero

NTF

Noise transfer function

OL

Overload level

OS

Output swing

OSR

Oversampling ratio

OTA

Operational transconductance amplifier

PCB

Printed circuit board

PDF

Probability density function

PDM

Pulse-density modulation

PLL

Phase-locked loop

pMOS

p-channel MOSFET

PSD

Power spectral density

PWL

Piece-wise linear

PWM

Pulse-width modulation

QFP

Quad flat package

RF

Radio frequency

RTF

Resonator transfer function

RZ

Return-to-zero

SAR

Successive approximation register

SC

Switched-capacitor

SDR

Software-defined radio

SFDR

Spurious-free dynamic range

S/H, S&H

Sample and hold

SI

Switched-current

SMASH

Sturdy multistage noise shaping

SMD

Surface-mount device

SNR

Signal-to-noise ratio

SNDR

Signal-to-noise-plus-distortion ratio

SQNR

Signal-to-quantization-noise ratio

SoC

System on chip

SR

Slew rate

STF

Signal transfer function

TDC

Time-to-digital converter

TEQ

Time-encoding quantizer

THD

Total harmonic distortion

UGBW

Unity gain bandwidth

UMTS

Universal mobile telecommunications system

USMR

Upsampling multirate

USTF

Unity signal transfer function

VCO

Voltage-controlled oscillator

VCRO

Voltage-controlled ring oscillator

V/I

Voltage-to-current

WCDMA

Wideband code division multiple access

WiMAX

Worldwide interoperability for microwave access

WLAN

Wireless local area network

Preface

Sigma-Delta modulators (Ms) have become one of the best choices for the implementation of analog/digital interfaces integrated in CMOS technologies. Compared to other kinds of analog-to-digital converters (ADCs), Ms cover the widest conversion region of the resolution-versus-bandwidth plane, being the most efficient solution to digitize very diverse types of signals in an increasing number of application scenarios, which span from high-resolution low-bandwidth data conversion (like digital audio, sensor interfaces, and instrumentation) to ultra-low power biomedical systems and medium-resolution broadband wireless communications. This versatility, together with their robustness and their simplicity in many practical situations, has motivated that more and more engineers today consider Ms as a first choice for their research projects and their industrial products.

The first idea underlying the operation of Ms was patented by Cutler in 1960 [1], although its application to the construction of data converters was first reported in the published literature by Inose et al in 1962 [2]. The operation of Ms is relatively simple to describe, although sometimes difficult to analyze. Essentially, the fundamental principle behind Ms is based on the combination of two signal processing techniques, namely oversampling and quantization noise shaping. The former consists of taking the signal samples at a higher rate than the one dictated by the Nyquist sampling theorem. These samples are commonly quantized with a large error by using a low-resolution quantizer. The resulting oversampled quantization error is filtered in the modulator feedback loop, so that its frequency spectrum is shaped in such a way that a large portion of its power is pushed out of the signal band, where it is removed by a digital filter. The outcome of the combined action of oversampling and noise shaping allows Ms to achieve a high-precision digitization by using a low-resolution coarse quantizer. Therefore, unlike other kinds of ADC architectures that require high-precision analog circuits, Ms trade the accuracy of their analog circuitry by the speed of digital signal processing, thus achieving a higher degree of insensitivity to circuit error mechanisms and potentially benefiting from CMOS technology evolution towards the nanometer scale.

Prompted by the mentioned benefits and fueled by technology downscaling and industry trends in consumer digital electronics, the original concept of noise shaping described above has evolved over the last five decades through many M generations, giving rise to a pleiad of architectures, circuit and system design techniques, and a number of Integrated Circuits (ICs), which have pushed the state-of-the-art on Ms forward, yielding to innovative research results and successful industry products. All these advances and research works have lead (and continue doing so) to a vast amount of technical literature. Indeed, since the publication of pioneer works like the widely cited papers written by Candy [3, 4] and Boser and Wooley [5], the number of publications has increased significantly including hundreds of patents, thousands of research papers, some tutorial papers [6–8], as well as tens of introductory and specialized monographs [9–29]. However, with so much material and abundance of technical information published, many designers—particularly novel designers and also some experienced designers focused on a specific subtopic of Ms—may become disoriented and lost. This has motivated some authors to put all these pieces of information together in a comprehensive and systematic way.

Apart from the earlier books aiming to catalogue the existing publications on Ms [9], one of the first attempts to present a guide for M designers is the book edited by Norsworthy et al in 1997 [10], also known as “the yellow book” by the M community. This book deals with a number of important subjects in Ms and it was contributed by a number of experts in the field, thus making it more difficult to present its contents in a coherent and consistent way. With this objective in mind, some authors have put their effort on writing tutorial monographs dealing with the systematic design of Ms.

Among others, the book written by Schreier and Temes, published in 2005 [21], often named “the green book”, has become one of the most popular books on converters. This book provides an excellent and comprehensive treatment of Ms, their operating principles, and main architectures, presenting several design examples constructed using the well-known Schreier's MATLAB toolbox [30]. Although some examples of continuous-time (CT) circuit implementations are given, the book mainly focuses on system-level description, considering a switched-capacitor (SC) implementation. Some other remarkable examples are the book written by Medeiro et al in 1999 [13]—focused on the systematic design of SC Ms—and the book of Ortmanns and Gerfers [22] published in 2006, which is still one of the most complete monographs on CT Ms reported to date. All these books, as well as other monographs reported in the technical literature, give a partial view of Ms, paying more attention to some particular aspects of the design of Ms, and/or a type of architecture, circuit technique, or application.

In this scenario, this book attempts to cover some of these knowledge gaps, by providing a broader and systematic description of the universe of Ms, their diverse types of architectures, circuit techniques, analysis and synthesis methods and CAD tools, as well as their practical design considerations. From this perspective, the book has a twofold purpose. First, it constitutes a unique monograph that results from compiling the enormous number of technical and research works reported to date on the topic of Ms, and presents the results of such a compilation in a didactical, pedagogical, and intuitive style. The second main objective and a key feature of this book is to serve as a practical guide for designers, putting emphasis on explaining practical design issues involved in the whole design flow of Ms: from specifications to chip implementation and characterization. To this end, a top-down approach is followed, presenting the contents in a hierarchical way; that is, going from theoretical fundamentals, system-level design equations, and behavioral models to circuit, transistor-level, and physical implementation, in order to provide readers the necessary understanding and insight into the recent advances, trends, and challenges involved in the design of state-of-the-art ICs.

Indeed, it is the top-down approach adopted in this book that inspires the hierarchical way in which the contents are organized. Thus, following this introduction, Chapter 1 begins from top, giving an introductory survey of Ms, their principles of operation, fundamental architectures, analysis and synthesis methods, as well as a taxonomical description of the diverse variety of practical M topologies, the nature of signal (low-pass and band-pass), as well as the dynamics involved (either discrete-time or continuous-time). In this chapter Ms are considered ideal systems, except for their inherent quantization error. Chapter 2 descends one level in the modulator hierarchy to analyze the effect of main circuit error mechanisms as well as architectural and timing nonidealities, considered in both SC and CT circuit implementations. The mathematical models, analytical procedures, and design guidelines described in this chapter provide sufficient understanding of the main practical problems affecting the performance of Ms in practice.

The knowledge derived from the first two chapters is presented in this book as an essential part of the systematic top-down/bottom-up synthesis methodology of Ms, that is described in Chapter 3. This chapter analyzes different strategies for the high-level modeling and simulation of Ms, focusing on the so-called behavioral modeling and simulation techniques. A step-by-step procedure to develop efficient behavioral models in the MATLAB/SIMULINK environment is described and illustrated with a number of examples of the main M building-block models. As an application, a time-domain behavioral simulator named SIMSIDES, is described and applied to the high-level sizing and verification of some case studies. The contents of this chapter are extended and complemented in Appendixes A and B. Appendix A gives a more complete user guide of SIMSIDES and Appendix B provides an overview of all behavioral models and libraries included in this simulator.

Chapter 4 moves farther down from the system-level description given in previous chapters to the circuit and physical level. This chapter provides a number of necessary design recommendations and practical recipes to complete the design flow of a M, showing the step-by-step methodology to transform a behavioral-model description given in Chapter 3 into an electrical schematic initially based on macromodels, and then implemented with transistors, and finally concluding the design cycle with the layout and chip implementation. Plenty of examples, case studies, and simulation test benches are given to illustrate the practical issues and design considerations addressed in the chapter, that cover from electrical analysis and simulation using SPICE-like simulators to layout design considerations, chip prototyping, and experimental measurements of Ms in the laboratory.

To conclude the book, Chapter 5 gives an overview of the state-of-the-art M ICs, comparing their performance with Nyquist-rate ADCs. Overall, more than 300 state-of-the-art IC references have been studied in detail and considered in this review, including papers published from 1990 to June 2012. Therefore, following the practical philosophy that inspires this book, the diverse families of state-of-the-art M architectures and circuit techniques are exhaustively analyzed and compared to extract practical and empirical design guidelines from the statistical data, trying to identify the incoming trends, design challenges, as well as the solutions proposed by cutting-edge ICs that are in the frontiers of Ms.

The book contents are addressed and structured for a large audience: from senior designers who want to acquire a deeper and updated insight into Ms, to nonexperienced undergraduate students who are looking for a comprehensive, uniform, and self-contained reference into this hot topic. Bearing this in mind, the style and main purpose of the book is to serve also as an educational and reference textbook for undergraduate and graduate students. Indeed, the book is based on a number of graduate courses given by the authors, including master and doctorate degree programs, invited lectures, and IEEE conference tutorials. All these materials have been adapted and updated so that a large portion of the book can be also used (and indeed it has been used) in both undergraduate and graduate courses.

However, in spite of the encyclopedic nature of the book, it is impossible to give an exhaustive description of all the topics contained in the thousands of publications dealing with Ms. Instead, the book tries to cover the main subtopics, providing sufficient insight to understand the other ones, that are just overviewed and sometimes even omitted. In order to try to palliate these unavoidable deficiencies, an exhaustive list of specific references is included at the end of each chapter. Overall, the book contains around 500 selected references in order to guide readers to increase their understanding of the diverse research topics dealing with the world.

The huge amount of information contained in the book is complemented and updated with a number of electronic resources, that have been prepared by the authors and are freely available on the Web. To this purpose, all the data analyzed in the state-of-the-art survey presented in Chapter 5 have been collected in a spreadsheet, which is available at http://www.imse-cnm.csic.es/∼jrosa/CMOS-SDMs-Survey-IMSE-JMdelaRosa.xlsx. This database is periodically kept up to date and aims to be a complement to the popular Murmann's ADC survey data collection [31]. In addition, a fully functional version of the time-domain behavioral simulator SIMSIDES is freely available on demand at http://www.imse-cnm.csic.es/simsides. The simulator includes a number of examples, containing the case studies presented in the book and many more examples and demos. Apart from the SIMSIDES software, the majority of examples and test benches of different CAD tools used throughout the book are also available on the Web at www.wiley.com/go/delarosa_converters.

Last but not least, it is important to mention that the aforementioned web sites will be regularly updated with new pieces of information and updated material related to the state-of-the-art M ICs, SIMSIDES examples and demos, as well as new inputs provided by us and hopefully by our readers. Therefore, your feedback is very important and very welcomed!

We hope that you enjoy reading this book as much as we have enjoyed writing it.

José M. de la Rosa and Rocío del RíoSevilla, October 2012

References

[1] C. C. Cutler, “Transmission System Employing Quantization,” US Patent No. 2,927,962, 1960.

[2] H. Inose, Y. Yasuda, and J. Murakami, “A Telemetering System by Code Modulation—- Modulation,” IRE Transactions on Space Electronics and Telemetry, vol. 8, pp. 204–209, September 1962.

[3] J. Candy and O. J. Benjamin, “The Structure of Quantization Noise from Sigma-Delta Modulation,” IEEE Transactions on Communications, pp. 1316–1323, 1981.

[4] J. Candy, “A Use of Double Integration in Sigma-Delta Modulation,” IEEE Transactions on Communications, vol. 33, pp. 249–258, March 1985.

[5] B. E. Boser and B. A. Wooley, “The Design of Sigma-Delta Modulation Analog-to-Digital Converters,” IEEE Journal of Solid-State Circuits, vol. 23, pp. 1298–1308, December 1988.

[6] P. M. Aziz et al., “An Overview of Sigma-Delta Converters,” IEEE Signal Processing Magazine, vol. 13, pp. 61–84, January 1996.

[7] I. Galton, “Delta-Sigma Data Conversion in Wireless Transceivers,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, pp. 302–315, January 2002.

[8] J. M. de la Rosa, “Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, pp. 1–21, January 2011.

[9] J. Candy and G. Temes, Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press, 1991.

[10] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press, 1997.

[11] J. Cherry and W. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion, Kluwer Academic Publishers, 1999.

[12] J. V. Engelen and R. van de Plassche, BandPass Sigma-Delta Modulators: Stability Analysis, Performance and Design Aspects, Kluwer Academic Publishers, 1999.

[13] F. Medeiro, B. Pérez-Verdù, and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Sigma-Delta Modulators, Kluwer Academic Publishers, 1999.

[14] V. Peluso, M. Steyaert, and W. Sansen, Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters, Kluwer Academic Publishers, 1999.

[15] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, 1999.

[16] L. Breems and J. H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers, Kluwer Academic Publishers, 2001.

[17] Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-bit Delta-Sigma A/D Converters, Kluwer Academic Publishers, 2002.

[18] J. M. de la Rosa, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips, Kluwer Academic Publishers, 2002.

[19] M. Kozak and I. Kale, Oversampling Delta-Sigma Modulators, Springer, 2003.

[20] O. Bajdechi and J. Huising, Systematic Design of Sigma-Delta Analog-to-Digital Converters, Kluwer Academic Publishers, 2004.

[21] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE Press, 2005.

[22] M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations, Springer, 2006.

[23] K. Philips and A. H. M. van Roermund, Sigma Delta A/D Conversion for Signal Conditioning, Springer, 2006.

[24] R. del Río, F. Medeiro, B. Pérez-Verdú, J. M. de la Rosa, and A. Rodríguez-Vázquez, CMOS Cascade Modulators for Sensors and Telecom: Error Analysis and Practical Design, Springer, 2006.

[25] L. Yao, M. Steyaert, and W. Sansen, Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS, Springer, 2006.

[26] P. G. R. Silva and J. H. Huijsing, High Resolution IF-to-Baseband ADC for Car Radios, Springer, 2008.

[27] R. H. van Veldhoven and A. H. M. van Roermund, Robust Sigma Delta Converters, Springer, 2011.

[28] A. Morgado, R. del Río, and J. M. de la Rosa, Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio, Springer, 2011.

[29] E. Janssens and A. van Roermund, Look-Ahead Based Sigma-Delta Modulation, Springer, 2011.

[30] R. Schreier, The Delta-Sigma Toolbox v. 7.3. [Online]. Available: http://www.mathworks.com/matlabcentral/fileexchange/19, 2009.

[31] B. Murmann, ADC Performance Survey 1997–2012. [Online]. Available: http://www.stanford.edu/∼murmann/adcsurvey.html, 2012.

Acknowledgements

We would like to express our deepest gratitude to Prof. Belén Pérez-Verdú and Prof. Angel Rodríguez-Vázquez from the University of Sevilla. We are indebted to them for so many things we learnt, not only related to the contents of this book, but also many life values and skills we have put in practice throughout our professional careers, first as their PhD students, then as senior researchers, and later as university professors. Our warm and special acknowledgement and dedication of this book goes to them.

We are also particularly grateful to our colleagues at the Institute of Microelectronics of Sevilla and the Department of Electronics and Electromagnetism of the University of Sevilla, especially to Prof. Francisco Fernández, Dr. Manuel Delgado, Dr. Rafael Castro, Dr. Rafael Domínguez, Dr. Oscar Guerra, Mr. Joaquín Ceballos, and Mr. Miguel Angel Lagos. Among them, we are especially grateful to our friend Dr. Fernando Medeiro, with whom we took our first steps in the fascinating world of sigma-delta modulators, working side by side in a number of research and industrial projects. Thank you very much Fernando!

We would also like to acknowledge our past and present undergraduate and graduate students, especially Dr. Jesús Ruíz-Amaya, Mr. Rafael Romay, Dr. Ramón Tortosa, Dr. Alonso Morgado, Dr. Edwin Becerra, Mr. Gerardo García, Mr. Luis Guerrero-Linares, and Mr. Sohail Asghar. Some pieces of material used for the preparation of this book have been adapted from their PhD works, including a number of examples and case studies. Specifically, the first version of SIMSIDES—the time-domain behavioral simulator described in this book— was developed by Dr. Ruíz-Amaya as part of his graduate thesis.

We would like to give our thanks to the staff at Wiley, in particular to the editors Liz Wingett, Laura Bell, Richard Davies, and Peter Mitchell, as well as to the anonymous reviewers of the book proposal for their constructive and valuable comments and suggestions, which became very useful for us to make this manuscript a reality, trying to keep a good trade-off between accuracy (resolution) and time to publication (speed). This is indeed a well-known compromise for us as analog designers. We also appreciate our discussions over all these years with so many experts in the field of sigma-delta converters, with whom we had the opportunity to meet at diverse conferences and technical meetings. Many of them were sponsored by the IEEE Circuits and Systems Society and the IEEE Solid-State Circuits Society.

In addition to all these great people, our work has been always supported by a number of National and International Research and Industrial Projects. More recently, our research was funded by the Spanish Ministry of Economy and Competitiveness (with support from the European Regional Development Fund) under contract TEC2010-14825/MIC.

Finally, our most grateful thanks go for our families. None of this would have been possible without their love, patience, confidence, and support. Thank you so much for everything!

Chapter 1

Introduction to ΣΔ Modulators: Basic Concepts and Fundamentals

This chapter is conceived as an introduction to analog-to-digital converters (ADCs). Their operation principle consists in combining oversampling, quantization error processing, and negative feedback for improving the effective resolution of a coarse quantizer. These basic concepts are presented in Section 1.1 and their effects on the performance of converters are compared with Nyquist-rate converters. Section 1.2 shows the basic architecture, ideal behavior, and performance metrics of converters, and sketches the architectural alternatives to enhance their resolution.

Before presenting practical topologies for the implementation of modulation, the large variety of the existing realizations is briefly classified in Section 1.3 according to the type of modulator architecture (single loops or cascades), the circuit techniques employed (discrete time (DT) or continuous time (CT)), and the nature of the signals being converted (low pass (LP) or band pass (BP)). Starting from the case of DT, LP, single-bit modulators, the implications of these different alternatives are then presented in an incremental way.

Section 1.4 is dedicated to single-loop architectures. Second- and higher-order single-loops are considered, taking into account issues related to their practical implementation and problems not addressed by linear models, such as instabilities. Cascade topologies are covered in Section 1.5. In Section 1.6 the topological study is extended to modulators using multibit embedded quantizers, analyzing their pros and cons. Techniques to circumvent the disadvantages, such as dynamic element matching (DEM) or dual quantization, are revised.

The conversion of BP signals is covered in Section 1.7, taking into account its typical application in digital radio receivers. The basic techniques for synthesizing DT, BP modulators are presented, together with practical aspects for their implementation. Finally, Section 1.8 addresses the realization of CT modulators, discussing their advantages compared to DT ones and the existing alternatives for the loop filter and the feedback implementation.

1.1 Basics of A/D Conversion

ADCs are electronic systems that perform the transformation of analog signals—which are continuous in time and in amplitude—into digital signals—which are discrete in both time and amplitude. Figure 1.1 illustrates the general block diagram of an ADC intended for the conversion of LP signals, which essentially consists of an antialiasing filter (AAF), a sampler, and a quantizer. First, the analog input signal of the ADC passes through the AAF, an LP analog filter than prevents out-of-band components from folding over the signal bandwidth during the subsequent sampling, what would corrupt the signal information. The resulting band-limited signal is sampled at a rate by the S/H circuit, thus yielding a DT signal , where . Finally, the values of are quantized using bits, so that each continuous-valued input sample is mapped onto the closer discrete-valued level out of the that cover the input range, yielding the converter digital output .

Figure 1.1 General block diagram of an A/D converter. A Nyquist-rate ADC is assumed.

As shown in Figure 1.1, the fundamental processes involved in the A/D conversion are sampling and quantization, whose implications are discussed in the following text.

1.1.1 Sampling

The sampling process performs the continuous-to-discrete transformation of the input signal in time and imposes a limit on the bandwidth of the analog input signal. According to the Nyquist theorem, to prevent information loss, must be sampled at a minimum rate of , often referred to as the Nyquist frequency. On the basis of this criterion, ADCs in which analog input signal is sampled at the minimum rate () are called Nyquist-rate ADCs. Conversely, ADCs in which are called oversampling ADCs. How much faster than required the input signal is sampled is expressed in terms of the oversampling ratio (OSR), defined as

1.1

Whether oversampling is used or not in an ADC has a noticeable influence on the requirements of its AAF. As in Nyquist-rate ADCs the input signal bandwidth coincides with , aliasing will occur if in Figure 1.1 contains frequency components above . High-order analog AAFs are thus required to implement sharp transition bands capable of removing out-of-band components with no significant attenuation of the signal band, as illustrated in Figure 1.2a for the LP case. Conversely, as in oversampling ADCs, the replicas of the input signal spectrum that are created by the sampling process are farther apart than in Nyquist-rate ADCs. As illustrated in Figure 1.2b, frequency components of the input signal in the range do not alias within the signal band, so that the filter transition band can be smoother, what greatly reduces the order required for the AAF and simplifies its design.

Figure 1.2 Antialiasing filter for (a) Nyquist-rate ADCs and (b) oversampling ADCs.

1.1.2 Quantization

The quantization process also introduces a limitation on the performance of an ideal ADC, because an error is generated while performing the continuous-to-discrete transformation of the input signal in amplitude, commonly referred to as quantization error. The operation of quantizers is illustrated in Figure 1.3. As a matter of example, Figure 1.3c depicts the I/O characteristic of a quantizer with , although results apply to a generic -bit quantizer. Input amplitudes within the full-scale input range are rounded to 1 out of the different output levels, which are usually encoded into a binary digital representation. If these levels are equally spaced, the quantizer is said to be uniform and the separation between adjacent output levels is defined as the quantization step

1.2

where stands for the full-scale output range. As and are not necessarily equal, the quantizer may exhibit a gain different from unity, as indicated in Figure 1.3c by the slope . As shown in Figure 1.3e, the quantizer operation thus inherently generates a rounding error that is a nonlinear function of the input. Note that, if is kept within the range , the quantization error is bounded within . The former input range is known as the nonoverload region of the quantizer, as opposed to ranges with , for which the magnitude of grows monotonously.

Figure 1.3 Illustration of the quantization process: (a) multibit quantizer block, (b) single-bit quantizer block, (c) I/O characteristic of a multibit quantizer, (d) I/O characteristic of a single-bit quantizer, (e) multibit quantization error, and (f) single-bit quantization error.

Figure 1.3 also shows the operation of a single-bit quantizer (). Note from Figure 1.3d that, compared to the multibit case, the output of a single-bit quantizer is determined by the input sign only, regardless of its magnitude. Therefore, the gain is undefined and can be arbitrarily chosen.

1.1.3 Quantization White Noise Model

In practice, an ideal quantizer as that shown in Figure 1.4a is often modeled using the linear scheme in Figure 1.4b if several assumptions are made on the statistical properties of the quantization error [1–3]. As already shown in Figure 1.3e, the quantization error is systematically determined by the quantizer input signal . Nevertheless, if is assumed to change randomly from sample to sample within the range , will also be uncorrelated from sample to sample. Under these requirements, the quantization error can be viewed as a random process with a uniform probability distribution in the range , as illustrated in Figure 1.4c. The power associated to the quantization error can thus be computed as

1.3

The former assumption implies that, as illustrated in Figure 1.4d, the power of the quantization error will also be uniformly distributed in the range , yielding

1.4

so that the power spectral density (PSD) of the quantization error in that range is

1.5

These assumptions are collectively known as the additive white noise approximation

of the quantization error and allow the representation of a quantizer, which is deterministic and nonlinear, with the random linear model in Figure 1.4b, in which with being a quantization noise.1

Figure 1.4 Quantization noise: (a) multibit quantizer block, (b) equivalent linear model with additive white noise, (c) probability density function (PDF), and (d) power spectral density.

On the basis of this approximation of the quantization error to a white noise, the performance of ideal ADCs can be easily evaluated. For a Nyquist ADC, in which , all the quantization noise power falls inside the signal band and passes to the ADC output as a part of the input signal itself, as illustrated in Figure 1.5a. Conversely, if an oversampled signal is quantized, because , only a fraction of the total quantization noise power lies within the signal band, as illustrated in Figure 1.5b. The in-band noise power (IBN) caused by the quantization process in an ideal oversampling ADC is thus,

1.6

so that the larger the OSR, the smaller the IBN.2

Figure 1.5 Quantization noise in (a) Nyquist-rate ADCs and (b) oversampling ADCs.

The dynamic range (DR) of an ideal ADC can be determined as the ratio of the output power at the frequency of an input sinusoid with maximum amplitude to the in-band quantization noise power:

1.7

From Figure 1.3c, the maximum input amplitude in the nonoverload region of an -bit quantizer is and its corresponding output power can be approximated to [5],

1.8

so that, using Equations 1.6 and 1.8, the DR of an ideal oversampling ADC yields

1.9

Note that, for a Nyquist ADC—that is, in Equation 1.9—each additional bit in the quantizer results in a DR increase of approximately . For an oversampling ADC, the DR further increases with the OSR by approximately , so that using for instance an OSR of 4 is similar to having one extra bit in the -bit quantizer.

1.1.4 Noise Shaping

An approach to further increase the accuracy of an oversampling ADC is shaping the quantization white noise in the frequency domain—that is, filtering it—in such a way that most of its power lies outside the signal band. This is illustrated in Figure 1.6a, where the quantization noise is conceptually obtained by subtracting the quantizer input signal from its output and then passes through a filter transfer function, usually called noise transfer function (NTF).

Figure 1.6 Quantization noise shaping: (a) conceptual block diagram and (b) effect on the in-band noise of an oversampling noise-shaping ADC.

For quantizers working on LP signals, the NTF is of high-pass type and can be easily obtained from a differentiator filter, with a -domain transfer function given by

1.10

where stands for the filter order. Taking into account that , the magnitude of the pure-differentiator NTF in Equation 1.10 can be approximated for low frequencies to

1.11

so that the power due to the shaped quantization noise that lies within the signal band (Figure 1.6b) yields

1.12

Using Equations 1.8 and 1.12, the DR of an ideal oversampling noise-shaping ADC can be obtained as

1.13

Note that, in comparison with Equation 1.9, if oversampling is used in combination with noise shaping, the DR increases with OSR by approximately .

1.2 Basics of Sigma-Delta Modulators

Contrary to the ADCs discussed so far, which are open loop systems from a control perspective, Sigma-Delta () ADCs rely on a feedback path to achieve a closed-loop control of the quantization error. The fundamentals on how the shaping of quantization noise is implemented in practice, as well as the basic architecture, performance metrics, and ideal behavior of oversampling noise-shaping ADCs is presented in the following sections.

1.2.1 Topology of ADCs

Figure 1.7 illustrates the basic block diagram of a ADC intended for the conversion of LP signals, which consists of the following:

Antialiasing filter (AAF)

, which band limits the analog input signal to avoid aliasing during its subsequent sampling. As discussed in Section 1.1.1, oversampling considerably relaxes the attenuation requirements of the AAF, so that smooth transition bands are usually sufficient compared to Nyquist-rate ADCs.

Sigma-Delta modulator

(

M

), in which the oversampling and quantization of the band-limited analog signal take place. The quantization noise of the embedded -bit quantizer is shaped in the frequency domain by placing an appropriate loop filter before it and closing a negative feedback loop around them. Low-resolution quantizers, with typically in the range 1–5 bit, are sufficient for obtaining small IBN and high accuracy in the A/D conversion.

Decimation filter

, in which a high-selectivity digital filter sharply removes the out-of-band spectral content of the M output and thus most of the shaped quantization noise. The decimator also reduces the data rate from down to the Nyquist frequency, while increasing the word length from to bits to preserve resolution.

Figure 1.7 General block diagram of a ADC. A low-pass discrete-time M is assumed.

The modulator is the block that has most influence on the performance of the ADC, basically because it is responsible for the sampling and quantization processes that ultimately limit the accuracy of the A/D conversion. We will focus on this block from now on, although it must be kept in mind that a ADC is more than a M!

1.2.2 Signal Processing in Ms

The basic scheme of a modulator consists of a loop filter and a -bit quantizer in a feedback loop, as shown in Figure 1.8a [6]. Let us consider that the gain of the loop filter is large within the signal band and small outside it. Owing to the action of negative feedback, the analog input signal and the analog version of the M output will practically coincide within the signal band, so that the error signal in this closed-loop system is very small within the signal band. As the -bit quantizer is uniform, mostof the differences between the input and the output of the M will be placed at higher frequencies, so that the quantization noise is shaped in the frequency domain and most of its power is pushed outside the signal band.

Figure 1.8 modulator: (a) block diagram and (b) ideal linear model.

Using the linear additive white noise model in Figure 1.4b for the embedded quantizer, the M in Figure 1.8a can be modeled as the two-input ( and ) one-output () linear system in Figure 1.8b, which is described in the -domain as

1.14

where STF and NTF stand for the signal and noise transfer functions, respectively given by

1.15

Note that, if the loop filter is designed such that within the signal band, then and ; that is, the quantization noise is ideally canceled while the input signal is perfectly transferred to the output.

For the conversion of LP signals, the simplest loop filter that exhibits the desired frequency performance is an integrator,

1.16

that, in combination with an embedded quantizer with , leads to a M whose output is given by

1.17

and builds up a first-order, high-pass shaping of the quantization noise—see Equation 1.10. For the sake of illustration, Figure 1.9 shows the output signal of a first-order M with a embedded 3-bit (8-level) quantizer for a sinusoidal input signal. Note that, due to the combined action of oversampling and negative feedback, the modulator output is a pulse-density modulated (PDM) signal whose local average tracks the input signal value within adjacent code transitions.

Figure 1.9 PDM output signal of a first-order, modulator with an embedded 3-bit quantizer for an input sinusoid.

1.2.3 Performance Metrics of Ms

Contrary to Nyquist-rate ADCs, whose performance is mainly characterized by static performance metrics—that is, monotonicity, gain and offset errors, differential nonlinearity (DNL), and integral nonlinearity (INL) [5]— ADCs' characteristics are typically measured using dynamic performance metrics, which are obtained from the frequency-domain representation of the time-domain digital output sequence. The latter thus requires the computation of the fast Fourier transform (FFT) of a finite-length output sequence with a specific windowing function, as will be discussed in Chapter 4. From that power spectrum representation of a M output sequence, some spectral metrics are directly measured and other noise and power metrics are derived.

Figure 1.10 illustrates an exemplary spectrum of a M output sequence when a sinusoidal signal with frequency is applied at its input. The main characteristics of the spectrum are highlighted; for example, the length of the digital sequence from which the FFT has been computed, the output signal peak at the frequency corresponding to the converted signal, etc. As will be discussed in Chapter 2, nonidealities of the circuitry used for implementing the M deviate in practice the output spectrum from a purely shaped quantization noise. On the one hand, linear errors give rise to a noise floor, as well as to a degradation of the shaping order. On the other, nonlinear errors generate distortion, which is typically noticeable for large input amplitudes, but submerged under the noise floor for small input signal amplitudes. Spectral metrics such as the spurious-free dynamic range (SFDR)—that is, the ratio of the signal power to the strongest spectral tone [5]—can be directly measured from the output modulator spectrum, as shown in Figure 1.10.

Figure 1.10 Illustration of a typical output spectrum of a modulator and its main characteristics. A low-pass M is assumed.

Noise and power metrics are derived from the M output spectra by integration over the signal bandwidth and are typically collected in a single plot as shown in Figure 1.11. These metrics are usually the most important measures and comprise the following:

Signal-to-noise ratio

(SNR), which is the ratio of the output power at the frequency of an input sinusoid to the

uncorrelated

IBN:

1.18

It accounts for the modulator linear performance only, so that the in-band power associated to harmonics of the input signal is not considered as part of the IBN for SNR computation.If an ideal M is considered and only the in-band quantization noise is accounted for in the IBN computation, the term signal-to-quantization-noise ratio (SQNR) is often employed.

Signal-to-noise-plus-distortion ratio

(SNDR), which is defined as the ratio of the output power at the frequency of an input sinusoid to the total IBN power, also accounting for possible harmonics at the M output. As illustrated in

Figure 1.11

, this makes a typical SNDR curve to deviate from the SNR curve only for large input amplitudes, for which the generated distortion is noticeable. Therefore, the output spectra from which the SNDR curve is computed are typically obtained by applying an input signal at (for LP Ms), so that at least the second and third harmonics lie within the signal band.

Dynamic range

(DR), which can be defined as the ratio of the output power at the frequency of an input sinusoid with maximum amplitude to the output power for a small input amplitude for which ; that is, so it cannot be distinguished from the error. Ideally, a sinusoid with maximum amplitude at the modulator input will provide an output sinusoid sweeping the full-scale range of the embedded quantizer, so that

1.19

Effective number of bits

(ENOB): as the DR of an ideal -bit Nyquist-rate converter is given by

Equation 1.9

with , a similar expression can be established for Ms

1.20

where ENOB can be defined as the number of bits needed for an ideal Nyquist-rate ADC to achieve the same DR as the ADC. The performance of oversampled converters and Nyquist-rate ADCs can thus be compared in a simple way [7].Instead of the DR, the peak SNDR is also often used in Equation 1.20 to express the accuracy of the A/D in a modulator in bits.

Overload Level

(OL): as illustrated in

Figure 1.11

, the SNR of a modulator increases monotonously with the input signal amplitude (), but sharply drops for input amplitudes close to half of the full-scale input range of the embedded quantizer () due to its overload and the associated IBN increase. The overload level is considered to define the maximum input amplitude for which the M still operates correctly and can almost be arbitrarily defined, but it is typically chosen as the amplitude for which the SNR drops below the peak SNR [8].

Figure 1.11 Illustration of the performance metrics of a modulator on a typical SNR curve.

1.2.4 Performance Enhancement of Ms

The output of an ideal LP th-order modulator in the -domain can be considered to be

1.21

where and the NTF builds up an th-order high-pass shaping of the quantization noise of the embedded quantizer. If a -bit quantizer is employed, the DR of the M can be obtained from Equations 1.12 and 1.19 to ideally yield

1.22

taking into account that —see Equation 1.2 —and considering quantization noise as the only contribution to the IBN.

Note from Equation 1.22 that the DR of a modulator is ideally determined by the values of , OSR, and , which can thus be considered as the three key parameters that define the M at the high level. The pros and cons of increasing the DR of a modulator by increasing each of these parameters are briefly discussed in the following:

High-order

modulators

. The accuracy of the A/D conversion can be considerably improved by increasing the noise-shaping order, because a larger fraction of the total quantization noise power will be pushed out of the signal band.

Figure 1.12

illustrates the ideal noise-shaping functions of orders ranging from 1 to 5. The case —that is, no shaping—is also included for comparison purposes. The DR enhancement if is increased in one for a given OSR can be obtained from

Equation 1.22

to be

1.23

This means that, for instance, the DR of a fourth-order M with is ideally () larger than that of a third-order M. However, as will be discussed in Section 1.4.2, the use of high-order () loop filters gives rise to stability problems in a M. Although these problems can be circumvented, the DR of a high-order M will in practice be smaller than predicted in Equation 1.22.

High OSR

modulators

.

Figure 1.13

shows the ideal DR as a function of OSR for noise-shaping orders ranging from 0 (no shaping) to 5 and assuming a single-bit embedded quantizer (). As illustrated, the combination of oversampling and noise-shaping considerably enhances the M performance for . Note from

Equation 1.22

that the DR of an ideal th-order modulator increases with OSR in . However, for a given conversion bandwidth , the OSR cannot be arbitrarily increased, because it leads to a higher sampling frequency for the operation of the circuitry. The latter, if achievable in practice for a given technological process, leads to larger power consumption.

Multibit

modulators

. An increase in leads to a decrease of the quantization step and thus to a reduction of the quantization noise power. Each additional bit in the embedded quantizer of a M is considered to typically yield a 6 dB (1 bit) improvement on the DR [9]. However, a multibit embedded quantizer requires a multilevel DAC to close the negative feedback loop in the M. Contrary to a two-level feedback DAC (), which is inherently linear, a multilevel DAC will in practice be nonlinear to some extent. As noticeable from

Figure 1.14

, the DAC nonlinearity will be directly added to the M input and will thus appear at the output, as within the signal band. Therefore, the linearity required in a multibit DAC equals in practice that wanted for the modulator. This point will be further discussed in Section 1.6.

Figure 1.12 Illustration of the shaping of quantization noise as a function of frequency in a M. NTF is given by Equation 1.10 and stands for the noise-shaping order.

Figure 1.13 Ideal dynamic range of a M as a function of the oversampling ratio for different noise-shaping orders (). A single-bit internal quantizer () is assumed.

Figure 1.14 Second-order modulator with unity STF.

1.3 Classification of Modulators

The strategies discussed in Section 1.2.4 for improving the DR of a M may be combined in many different ways, giving rise to the huge number of M topologies reported in literature, which can be grouped attending to different classification criteria [10]:

Single-Loop versus Cascade

Ms (attending to the number of quantizers employed)

. Ms employing only one quantizer are called

single-loop

topologies, whereas those employing several quantizers are often named

cascade

or MASH Ms. These topological alternatives will be discussed in Sections 1.4 and 1.5.

Single-Bit versus Multibit

Ms (attending to the number of bits in the embedded quantizer)

. Their pros and cons will be discussed in Section 1.6.

Low-Pass versus Band-Pass

Ms (attending to the nature of the signals being converted)

. The A/D conversion of LP signals has been assumed in previous sections, but BP Ms can also be built, as will be discussed in Section 1.7.

Discrete-Time versus Continuous-Time

Ms (attending to the nature of loop filter dynamics)

. The use of a DT loop filter in the M has been assumed in previous sections. However, CT Ms can be also implemented in practice. According to this classification criteria,

hybrid

CT/DT Ms take advantage of the benefits of both DT and CT implementations, which will be discussed in Section 1.8.

Describing all possible M architectures derived from previous classification criteria goes beyond the scope of this book. A detailed analysis of them can be found in the many papers and books devoted to the topic in the literature [4, 9, 11–23]. Instead, we will hereafter focus on the most representative families of modulators.

1.4 Single-Loop Modulators

modulators that make use of only one embedded quantizer are usually referred to as single-loop topologies. To get familiar with these architectures, their performance, their circuit-level implementation, as well as some other practical aspects are first addressed considering the case of second-order Ms. Afterward, the problematics of stability in higher-order Ms is presented, together with architectural alternatives to circumvent it.

1.4.1 Second-Order M

Figure 1.15a shows a second-order modulator built up by cascading two DT integrators [24], with each integrator receiving a weighted feedback path from the DAC. Coefficients are usually called integrator scalings or weights. Under linear analysis, the modulator output in the -domain yields

1.24

where stands for the gain of the quantizer. For a pure second-order shaping, Equation 1.24 needs to be simplified to

1.25

so that the following expressions for the integrator coefficients need to be fulfilled:

1.26

Figure 1.15 Block diagram of second-order Ms and different notations: (a) general representation of the DT-M using the notation in [8, 9] and (b) alternative representation of the DT-M using the notation in [12, 19].

Figure 1.15b shows an alternative representation of the second-order M according to the coefficients notation in [12, 19], which allows to allocate different weights in the forward and feedback paths of each integrator, using coefficients and , respectively. As exemplary illustrated in Figure 1.16, the notations in Figure 1.15a and b can be easily connected with the equalities:

1.27

Figure 1.16 Illustration of the equivalence between the DT representations in Figure 1.15a and 1.14b.

Both nomenclatures for the integrator scaling coefficients of modulators will be used throughout this book. The notation in [8, 9] is closer to the modulator architectural level, whereas the notation in [12, 19] is closer to the actual circuit-level implementation, in which integrators with more than one SC input branch are usually employed. The latter is thus useful to accurately account for some nonidealities of the practical M implementation, which will be covered in Chapter 2.

For the sake of illustration, Figure 1.17 shows a possible implementation of the second-order M in Figure 1.15 using fully-differential SC circuitry and assuming single-bit quantization. The modulator differential input signal is denoted by and the modulator digital output , after the comparator, controls the feedback connection of reference voltages and to the integrators. The modulator full scale range thus equals , with . Note from the first SC integrator in Figure 1.17 that both the modulator input signal and the DAC feedback signal are processed through the sampling capacitor . For the second integrator, the output of the first integrator is processed through both and , whereas the DAC feedback signal is processed only through . The modulator scaling coefficients are thus implemented as the following capacitor ratios (Figure 1.15b)

1.28

Figure 1.17 Fully-differential SC implementation of a second-order modulator.

In practice, the value of the integrator weights are selected to fulfill the relations in Equation 1.26, also taking into account their implication in some aspects of the modulator performance, such as the following:

Keeping the state variables (integrator outputs) bounded to ensure the modulator stability. The second-order M is stable for inputs in the range if , regardless the quantizer gains [24]. This condition is already met if —see

Equations 1.26

and

1.27

.

Keeping the modulator overload level as close as possible to the full scale to ensure a high-peak SNR—see Figure 1.11.

Minimizing the required signal range at the integrators outputs; that is, the integrator output swing demands must be attainable with the intended voltage supply and as low as possible to reduce power consumption and to facilitate circuit design.

Simplifying the practical implementation of the integrator weights as ratios of unit capacitors.

Generally speaking, the selection of the scaling coefficients of a modulator involves solving several trade-offs between architectural-, circuit-, and technological-level aspects of the practical implementation, so that the optimum selection for a given application may not apply in a different scenario. For the sake of illustration, Table 1.1 shows several sets of weights reported for the second-order, single-bit M in Figure 1.15. All sets exhibit an overload level (i.e., below the full-scale amplitude ). The required integrator output swing and the minimum number of unit capacitors are also included. Capacitor sharing between weights in the same integrator has been considered.

Table 1.1 Comparison of some sets of coefficients reported for the second-order single-bit M

Second-Order M with Unity STF

Figure 1.14 shows an alternative second-order M topology that makes use of feed-forward paths to implement a so-called unity STF [28, 29]. Under linear analysis, the modulator output in the -domain yields

1.29

so that —that is, the signal transfer function equals 1 at all frequencies—whereas NTF is unaffected.

One of the most appealing features of the unity-STF M in Figure 1.14 is that ideally there is no input signal trace processed by the integrators. Indeed, the integrator inputs in -domain can be obtained as

1.30

showing that they depend only on the quantization error. In practice, there will be some residual component of the modulator input signal at the integrator inputs, but it is normally negligible. This means that, if nonlinearities of the circuit implementation are accounted for, the generated distortion will be considerably lower for the unity-STF M in Figure 1.14 compared to the one traditional M in Figure 1.15. Moreover, the technique is effective for any OSR, which makes unity-STF Ms especially suited for lowering the sensitivity to circuit imperfections in wideband applications, in which low OSR values are required.

The described concept of unity STF can be extended to a noise shaping of any order. The only requirement is to ideally make , without changing the modulator NTF. In recent years, it has been often applied in Ms for wideband and multimode applications [30–34].

1.4.2 High-Order Ms

The simplest way to extend a M to an arbitrary th-order shaping consists of including integrators before the quantizer. Extending the second-order M in Figure 1.15a, the topology in Figure 1.18 is obtained, which is known as an th-order single-loop M with distributed feedback [35].3 Ideally, its NTF can be derived from linear analysis and equated to Equation 1.10 to derive a set of relations between the integrator scaling coefficients to be fulfilled for obtaining a pure-differentiator noise shaping—similarly as done in Equation 1.26 for the second-order M. The in-band quantization noise and the modulator DR would thus be ideally given by Equations 1.12 and 1.13, respectively.

Figure 1.18 High-order single-loop M with distributed feedback.

However, this modulator performance cannot be met in practice because Ms with pure-differentiator FIR NTFs are prone to instability if , exhibiting unbounded states and poor SNR compared to that predicted by linear analysis. In general, instability appears at the modulator output as a large-amplitude, low-frequency oscillation, leading to long bitstreams of alternating s and s. This tendency to instability can be explained as follows [36]. For a M to be stable, the quantizer input must not be allowed to become too large. As the quantizer input is obtained as (Figure 1.18)

1.31

the gain of , or simply , must not be too large. However, as clearly visible from Figure 1.12, the out-of-band gain of FIR NTFs of the form rapidly increases for , yielding at . Consequently, it starts to overload the quantizer, which yields a significant decrease of the modulator SNR.

This problem can be circumvented by resorting to single-loop Ms with IIR NTFs of the form , with being a polynomial determined by the modulator scaling coefficients that helps to limit the out-of-band gain of NTF.4 However, unlike second-order Ms, for which a stability condition has been extracted [24], determining exact conditions that guarantee the stability of higher-order, single-loop Ms is still an open question. In [8, 37], it is shown, using behavioral simulations, that high-order Ms are conditionally