Sigma-Delta Converters E-Book

José M. de la Rosa

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: Wiley - IEEE
• Sprache: Englisch

Seitenzahl: 926

Veröffentlichungsjahr: 2018

Beschreibung

Thoroughly revised and expanded to help readers systematically increase their knowledge and insight about Sigma-Delta Modulators Sigma-Delta Modulators (SDMs) have become one of the best choices for the implementation of analog/digital interfaces of electronic systems integrated in CMOS technologies. Compared to other kinds of Analog-to-Digital Converters (ADCs), SigmadeltaMs cover one of the widest conversion regions of the resolution-versus-bandwidth plane, being the most efficient solution to digitize signals in an increasingly number of applications, which span from high-resolution low-bandwidth digital audio, sensor interfaces, and instrumentation, to ultra-low power biomedical systems and medium-resolution broadband wireless communications. Following the spirit of its first edition, Sigma-Delta Converters: Practical Design Guide, 2nd Edition takes a comprehensive look at SDMs, their diverse types of architectures, circuit techniques, analysis synthesis methods, and CAD tools, as well as their practical design considerations. It compiles and updates the current research reported on the topic, and explains the multiple trade-offs involved in the whole design flow of Sigma-Delta Modulators--from specifications to chip implementation and characterization. The book follows a top-down approach in order to provide readers with the necessary understanding about recent advances, trends, and challenges in state-of-the-art SigmadeltaMs. It makes more emphasis on two key points, which were not treated so deeply in the first edition: * It includes a more detailed explanation of SigmadeltaMs implemented using Continuous-Time (CT) circuits, going from system-level synthesis to practical circuit limitations. * It provides more practical case studies and applications, as well as a deeper description of the synthesis methodologies and CAD tools employed in the design of Sigmadelta converters. Sigma-Delta Converters: Practical Design Guide, 2nd Edition serves as an excellent textbook for undergraduate and graduate students in electrical engineering as well as design engineers working on SD data-converters, who are looking for a uniform and self-contained reference in this hot topic. With this goal in mind, and based on the feedback received from readers, the contents have been revised and structured to make this new edition a unique monograph written in a didactical, pedagogical, and intuitive style.

Leseprobe

Table of Contents

Cover

Dedication

Preface

References

Acknowledgements

List of Abbreviations

Chapter 1: Introduction to

Modulators: Fundamentals, Basic Architecture and Performance Metrics

1.1 Basics of Analog‐to‐Digital Conversion

1.2 Sigma‐Delta Modulation

1.3 The First‐order

Modulator

1.4 Performance Enhancement and Taxonomy of

Ms

1.5 Putting All The Pieces Together: From

Ms to

ADCs

1.6

DACs

1.7 Summary

References

Chapter 2: Taxonomy of

Architectures

2.1 Second‐order

Modulators

2.2 High‐order Single‐loop

Ms

2.3 Cascade

Modulators

2.4 Multi‐bit

Modulators

2.5 Band‐pass

Modulators

2.6 Continuous‐time

Modulators: Architecture and Basic Concepts

2.7 DT–CT Transformation of

Ms

2.8 Direct Synthesis of CT‐

Ms

2.9 Summary

References

Chapter 3: Circuit Errors in Switched‐capacitor

Modulators

3.1 Overview of Nonidealities in Switched‐capacitor

Modulators

3.2 Finite Amplifier Gain in SC‐

Ms

3.3 Capacitor Mismatch in SC‐

Ms

3.4 Integrator Settling Error in SC‐

Ms

3.5 Circuit Noise in SC‐

Ms

3.6 Clock Jitter in SC‐

Ms

3.7 Sources of Distortion in SC‐

Ms

3.8 Case Study: High‐level Sizing of a

M

3.9 Summary

References

Chapter 4: Circuit Errors and Compensation Techniques in Continuous‐time

Modulators

4.1 Overview of Nonidealities in Continuous‐time

Modulators

4.2 CT Integrators and Resonators

4.3 Finite Amplifier Gain in CT‐

Ms

4.4 Time‐constant Error in CT‐

Ms

4.5 Finite Integrator Dynamics in CT‐

Ms

4.6 Sources of Distortion in CT‐

Ms

4.7 Circuit Noise in CT‐

Ms

4.8 Clock Jitter in CT‐

Ms

4.9 Excess Loop Delay in CT‐

Ms

4.10 Quantizer Metastability in CT‐

Ms

4.11 Summary

References

Chapter 5: Behavioral Modeling and High‐level Simulation

5.1 Systematic Design Methodology of

Modulators

5.2 Simulation Approaches for the High‐level Evaluation of

Ms

5.3 Implementing

M Behavioral Models

5.4 Efficient Behavioral Modeling of

M Building Blocks using C‐MEX S‐functions

5.5 SIMSIDES: A SIMULINK‐based Behavioral Simulator for

Ms

5.6 Using SIMSIDES for High‐level Sizing and Verification of

Ms

5.7 Summary

References

Chapter 6: Automated Design and Optimization of

Ms

6.1 Architecture Exploration and Selection: Schreier's Toolbox

6.2 Optimization‐based High‐level Synthesis of

Modulators

6.3 Lifting Method and Hardware Acceleration to Optimize CT‐

Ms

6.4 Using Multi‐objective Evolutionary Algorithms to Optimize

Ms

6.5 Summary

References

Chapter 7: Electrical Design of

Ms: From Systems to Circuits

7.1 Macromodeling

Ms

7.2 Examples of

M Macromodels

7.3 Including Noise in Transient Electrical Simulations of

Ms

7.4 Processing

M Output Results of Electrical Simulations

7.5 Summary

References

Chapter 8: Design Considerations of

M Subcircuits

8.1 Design Considerations of CMOS Switches

8.2 Design Considerations of Operational Amplifiers

8.3 Design Considerations of Transconductors

8.4 Design Considerations of Comparators

8.5 Design Considerations of Current‐Steering DACs

8.6 Summary

References

Chapter 9: Practical Realization of

Ms: From Circuits to Chips

9.1 Auxiliary

M Building Blocks

9.2 Layout Design, Floorplanning, and Practical Issues

9.3 Chip Package, Test PCB, and Experimental Setup

9.4 Experimental Test Set‐Up

9.5

M Design Examples and Case Studies

9.6 Summary

References

Chapter 10: Frontiers, Trends and Challenges: Towards Next‐generation

Modulators

10.1 State‐of‐the‐Art ADCs: Nyquist‐rate versus

Converters

10.2 Comparison of Different Categories of

ADCs

10.3 Empirical and Statistical Analysis of State‐of‐the‐Art

Ms

10.4 Gigahertz‐range

Ms for RF‐to‐digital Conversion

10.5 Enhanced Cascade

Ms

10.6 Power‐efficient

M Loop‐filter Techniques

10.7 Hybrid

M/Nyquist‐rate ADCs

10.8 Time‐based

ADCs

10.9 DAC Techniques for High‐performance CT‐

Ms

10.10 Classification of State‐of‐the‐Art References

10.11 Summary and Conclusions

References

Appendix A: State‐space Analysis of Clock Jitter in CT‐ΣΔMs

A.1 State‐space Representation of

A.2 Expectation Value of

A.3 In‐band Noise Power due to Clock Jitter

References

Appendix B: SIMSIDES User Guide

B.1 Getting Started: Installing and Running SIMSIDES

B.2 Building and Editing

M Architectures in SIMSIDES

B.3 Analyzing

Ms in SIMSIDES

B.4 Optimization Interface

B.5 Tutorial Example: Using SIMSIDES to Model and Analyze

Ms

B.6 Getting Help

Appendix C: SIMSIDES Block Libraries and Models

C.1 Overview of SIMSIDES Libraries

C.2 Ideal Libraries

C.3 Real SC Building‐Block Libraries

C.4 Real SI Building‐Block Libraries

C.5 Real CT Building‐Block Libraries

C.6 Real Quantizers & Comparators

C.7 Real D/A Converters

C.8 Auxiliary Blocks

Index

End User License Agreement

List of Tables

Chapter 2

Table B.1 Building‐block model parameters used for simulating the

M in Figure B.16b.

Chapter 3

Table C.1 Overview of SIMSIDES libraries.

Table C.2 Library of SC (FE/LD) integrators included in SIMSIDES.

Table C.3 Model parameters used in SIMSIDES SC (FE/LD) integrators.

Table C.4 Library of SC (FE/LD) resonators included in SIMSIDES.

Table C.5 Library of SI (FE/LD) integrators included in SIMSIDES.

Table C.6 Library of SI (FE/LD) resonators included in SIMSIDES.

Table C.7 Gm‐C integrator library models in SIMSIDES.

Table C.8 Gm‐MC integrator library models in SIMSIDES.

Table C.9 Active‐RC integrator library models in SIMSIDES.

Table C.10 MOSFET‐C integrator library models in SIMSIDES.

Table C.11 Gm‐C resonator library models in SIMSIDES.

Table C.12 Gm‐LC resonator library models in SIMSIDES.

Table C.13 Real quantizers and comparator models included in SIMSIDES.

Table C.14 Error model parameters used in SIMSIDES real quantizers.

Table C.15 Real DAC models included in SIMSIDES.

Table C.16 Auxiliary building‐block models used in SIMSIDES.

Table C.17 Error model parameters used in SIMSIDES auxiliary blocks.

Chapter 1

Table 1.1 Repetitive patterns in 1‐bit

Ms with DC inputs.

Chapter 2

Table 2.1 Comparison of some sets of coefficients reported for the second‐order single‐bit

M.

Table 2.2 Comparison of some sets of coefficients reported for the 2‐1‐1 single‐bit

M.

Table 2.3 CT equivalents of first‐order to fourth‐order DT low‐pass loop filter poles for the rectangular feedback DAC pulses defined in Equation 2.43 [23].

Table 2.4 DT equivalents of first‐order to fourth‐order CT low‐pass loop filter poles for the rectangular feedback DAC pulses defined in Equation 2.43 [23].

Chapter 3

Table 3.1 High‐level sizing of the 2‐1‐1 SC‐

M.

Table 3.2 Noise budget for the high‐level sizing of the 2‐1‐1 SC‐

M proposed in Table 3.1.

Chapter 5

Table 5.1 Example of CPU time required to simulate a fourth‐order single‐loop

M considering different situations in a multi‐level approach. Simulations were carried out in a SUN Fire X2200 M2 server with 4‐GB RAM and a 2.2‐GHz Dual Core AMD Opteron CPU, running a 64‐bit Linux operating system.

Table 5.2 Circuits and error mechanisms modeled in SIMSIDES.

Table 5.3 High‐level sizing of the second‐order SC‐

M shown in Figure 5.46 (

).

Table 5.4 Loop‐filter coefficients of the CT cascade 3‐2

M in Figure 5.55.

Table 5.5 High‐level sizing of the CT cascade

M in Figure 5.55.

Chapter 6

Table 6.1 High‐level synthesis results of a cascade 2‐1‐1 SC‐

M, 3‐bit in the back‐end stage (

MHz,

16,

V).

Chapter 9

Table 9.1 Example of high‐level synthesis of the BP CT‐

M in Figure 6.10.

Table 9.2 Sizing example of unitary transconductors (see Figure 8.23].

Table 9.3 Reconfiguration of resonators.

Chapter 10

Table 10.2 State‐of‐the‐art SC single‐loop multi‐bit LP‐

Ms.

Table 10.3 State‐of‐the‐art SC cascade single‐bit LP‐

Ms.

Table 10.4 State‐of‐the‐art SC cascade multi‐bit LP‐

Ms.

Table 10.5 State‐of‐the‐art SC BP‐

Ms.

Table 10.6 State‐of‐the‐art CT single‐loop single‐bit LP‐

Ms.

Table 10.7 State‐of‐the‐art CT single‐loop multi‐bit LP‐

Ms.

Table 10.8 State‐of‐the‐art CT cascade LP‐

Ms.

Table 10.9 State‐of‐the‐art CT BP‐

Ms.

Table 10.10 State‐of‐the‐art

Ms with time‐coded quantization.

Table 10.11 State‐of‐the‐art hybrid

Ms.

Table 10.12 State‐of‐the‐art SC adaptive/reconfigurable

Ms.

Table 10.13 State‐of‐the‐art CT reconfigurable

Ms (sorted by date of publication).

Table 10.1 State‐of‐the‐art SC single‐loop single‐bit LP‐

Ms (sorted by FOMW).

List of Illustrations

Chapter 1

Figure A.1 Conceptual diagram of a CT‐

M.

Figure A.2 Transpose of the Direct II implementation of

.

Figure A.3 State‐space representation of

.

Chapter 2

Figure B.1 Installing and starting SIMSIDES: (a) setting the MATLAB path; (b) starting SIMSIDES at the MATLAB prompt.

Figure B.2 Building and editing

Ms in SIMSIDES: (a) creating a new

M architecture; (b) opening an existing model.

Figure B.3 Illustrating different sublibraries included in the

Real Integrators

library.

Figure B.4 Analysis menu in SIMSIDES.

Figure B.5 Node spectrum analysis menu.

Figure B.6 Integrated power noise menu.

Figure B.7 SNR/SNDR menu.

Figure B.8 Harmonic distortion analysis menu.

Figure B.9 Integral and differential non‐linearity analysis menu.

Figure B.10 Multi‐tone power ratio analysis menu.

Figure B.11 Histogram analysis menu.

Figure B.12 Parametric analysis menu.

Figure B.13 Monte Carlo analysis menu.

Figure B.14 SIMSIDES optimization menu: (a) main window; (b) GUI for setting up the optimization; (c) model including the additional block to compute SNR while running the optimization.

Figure B.15

‐domain block diagram of a cascade 2‐1 DT‐

M.

Figure B.16 SIMSIDES block diagram of the

M shown in Figure B.15: (a) building and editing the block diagram; (b) complete modulator block diagram in SIMSIDES.

Figure B.17 M‐file including all model parameters required to simulate the

M in Figure B.16b.

Figure B.18 Output spectrum (magnitude) of the

M in Figure B.16b.

Figure B.19 SNDR versus input amplitude level of the

M in Figure B.16b.

Figure B.20 Using parametric analysis to study the effect of a single model parameter: SNDR versus transconductance of the front‐end amplifier for the

M in Figure B.16b.

Figure B.21 Parametric analysis considering the effect of two parameters (

and

) on the SNDR.

Figure B.22 Illustrating the use of histograms of the modulator in Figure B.16b.

Figure B.23 Help menu.

Chapter 3

Figure C.1

‐domain block diagram of: (a) Ideal_LD_Resonator. (b) Ideal_FE_Resonator.

Figure C.2 Input and output signals in an Ideal_Comparator_for_SI model.

Figure C.3 Illustrating the input/output DC characteristic of: (a) multi‐bit (3‐bit)

midrise

quantizer; (b) multi‐level (7‐level)

midtreat

quantizer.

Figure C.4 Equivalent circuit of Ideal_DAC_for_SI model.

Figure C.5 SC integrator symbol in SIMSIDES: (a) one‐branch integrator; (b) two‐branch integrator.

Figure C.6 Block diagram of SC resonators in SIMSIDES: (a) LDI‐based resonator; (b) FEI‐based resonator.

Figure C.7 Excerpt of SC resonator libraries in SIMSIDES.

Figure C.8 SI integrator symbol used in SIMSIDES and its corresponding conceptual schematics.

Figure C.9 SI buffer used in SIMSIDES: (a) symbol; (b) equivalent circuit.

Figure C.10 Block diagram of SI resonators in SIMSIDES: (a) FEI‐loop resonator; (b) LDI‐loop resonator.

Figure C.11 Modeling finite input‐output conductance ratio error in SIMSIDES: (a) SI LD integrator; (b) equivalent circuit during sampling phase (

).

Figure C.12 Classification of SIMSIDES CT model libraries.

Figure C.13 One‐pole Gm‐C integrator model used in SIMSIDES.

Figure C.14 Two‐pole Gm‐MC integrator model used in SIMSIDES: (a) conceptual schematic; (b) equivalent circuit of the transconductor and the opamp.

Figure C.15 Two‐pole active‐RC integrator model used in SIMSIDES: (a) conceptual schematic; (b) equivalent circuit.

Figure C.16 Conceptual schematic of a MOSFET‐C integrator like that modeled in SIMSIDES by the building blocks listed in Table C.10.

Figure C.17 CT resonator libraries included in SIMSIDES: (a) Gm‐C resonators; (b) Gm‐LC resonators.

Figure C.18 Conceptual schematics of the CT resonators modeled in SIMSIDES: (a) Gm‐C resonator; (b) Gm‐LC resonator.

Figure C.19 Example of a second‐order feedforward SC‐

M with 16‐level quantization and DEM: (a) SIMSIDES block diagram; (b) Mux_SD2 dialogue box; (c) first integrator block dialogue box; (d) second integrator block dialogue box; (e) DAC‐DEM block dialogue box.

Figure C.20 MATLAB code used for defining capacitor arrays and DEM parameters of Figure C.19e.

Chapter 1

Figure 1.1 Analog‐to‐digital conversion: (a) conceptual block diagram; (b) signal processing. A Nyquist‐rate ADC is assumed.

Figure 1.2 Resolution (accuracy) versus speed achieved by state‐of‐the‐art ADCs.

Figure 1.3 Antialiasing filter for: (a) Nyquist‐rate ADCs; (b) oversampling ADCs.

Figure 1.4 Quantization process: (a) multi‐bit quantizer block; (b) single‐bit quantizer block; (c) I/O characteristic of a multi‐bit quantizer; (d) I/O characteristic of a single‐bit quantizer; (e) multi‐bit quantization error; (f) single‐bit quantization error.

Figure 1.5 Midtread quantization: (a) conceptual I/O characteristic; (b) illustration of a three‐level ADC made up of two single‐bit quantizers (comparators).

Figure 1.6 Quantization linear model: (a) multi‐bit quantizer block; (b) equivalent model with additive white noise.

Figure 1.7 Illustrating the validity of the white‐noise model for a quantizer when the number of levels of the quantizer is increased when a two‐tone input signal is applied.

Figure 1.8 Quantization white noise: (a) probability density function (PDF); (b) power spectral density.

Figure 1.9 Quantization noise in: (a) Nyquist‐rate ADCs; (b) oversampling ADCs.

Figure 1.10 Quantization noise shaping: (a) conceptual block diagram; (b) effect on the in‐band noise of an oversampling noise‐shaping ADC.

Figure 1.11 Conceptual block diagram of a noise‐shaped ADC. Two different shaped noise output spectra are illustrated, for when the NTF is either a band‐pass or a low‐pass filter.

Figure 1.12

modulator: (a) block diagram; (b) ideal linear model.

Figure 1.13 Illustration of a typical experimental output spectrum of a

modulator and its main characteristics. An LP

M is assumed.

Figure 1.14 Illustration of the performance metrics of a

M on a typical SNR curve.

Figure 1.15 Block diagram of a first‐order

M and its corresponding fully‐differential SC circuit implementation with 1‐bit quantization.

Figure 1.16 PDM output signal of a first‐order

modulator with a embedded (a) 3‐bit quantizer for an input sinusoid and (b) 1‐bit quantizer and an input stair waveform.

Figure 1.17 Noise pattern of a first‐order

M with 1‐bit quantizer.

Figure 1.18 Output spectra of a first‐order

M for a 1‐bit and a 5‐bit quantizer.

Figure 1.19 Illustration of the shaping of quantization noise as a function of frequency in a

M. NTF is given by Equation 1.10 and

is the noise‐shaping order.

Figure 1.20 Ideal dynamic range of a

M as a function of the oversampling ratio for different noise‐shaping orders (

). A single‐bit internal quantizer (

) is assumed.

Figure 1.21 General block diagram of a

ADC with: (a) LP signal; (b) BP signal.

Figure 1.22 Illustrating the signal processing in

decimators for: (a) LP

ADCs, (b) BP

ADCs.

Figure 1.23 Block diagram of a

‐order (

) CIC decimation filter.

Figure 1.24 Decimation stage filter implementation [4].

Figure 1.25 Signal waveforms in a

ADC made up of a 1‐bit second‐order

M and a third‐order CIC decimator.

Figure 1.26 Conceptual block diagram of a

DAC.

Figure 1.27 Illustration of signal processing in

DACs.

Figure 1.28 Conceptual block diagram of a digital

M typically used in

DACs.

Figure 1.29 Block diagram of a second‐order digital

M.

Chapter 2

Figure 2.1 Block diagram of second‐order

Ms and different notations: (a) synthesis of the architecture from a first‐order

M; (b) general representation of the second‐order DT‐

M using the loop‐filter notation in [1, 2]; (c) alternative representation of the second‐order DT‐

M using the notation in [3, 4].

Figure 2.2 Illustrating the noise‐shaping of second‐order

Ms: (a) half‐scale output spectrum; (b) noise pattern.

Figure 2.3 Equivalence between the DT representations in Figures 2.1b and 2.1c.

Figure 2.4 Fully‐differential SC implementation of a second‐order

modulator.

Figure 2.5 Second‐order

modulator with unity STF.

Figure 2.6 Illustrating the use of unity‐STF in second‐order

Ms with 3‐bit quantization: (a) magnitude spectrum of integrators' outputs; (b) output swings of integrators.

Figure 2.7 High‐order single‐loop

M with distributed feedback.

Figure 2.8 High‐order single‐loop

M with feedforward summation.

Figure 2.9 High‐order single‐loop

M with distributed feedback and distributed feedforward input paths.

Figure 2.10 High‐order single‐loop

M with feedforward summation and local feedback loops.

Figure 2.11 Illustrating different implementations of a fourth‐order NTF with

.

Figure 2.12 General topology of an

‐stage cascade

modulator.

Figure 2.13 Illustrating the noise‐shaping in a 2‐stage cascade

M with

.

Figure 2.14 Block diagram of a 2‐1‐1 cascade

modulator using the notation in [1, 2]. The relations in Equations 2.24 and 2.25 must be fulfilled for the correct operation of the cascade.

Figure 2.15 Alternative representation of the 2‐1‐1

M in Figure 2.14 using the notation in [3, 4]. Modulator coefficients

are mapped onto integrator input coefficients

, which are closer to the circuit‐level implementation.

Figure 2.16 Illustrating the noise‐shaping in a 2‐1‐1 cascade

M with 3‐bit quantization in the back‐end stage and the loop‐filter coefficients of del Rio

et al

. [39].

Figure 2.17 Conceptual block diagram of a two‐stage SMASH

M [40, 41].

Figure 2.18 Block diagram of a 2‐2 SMASH

M [41].

Figure 2.19 SMASH

M with USTF [43].

Figure 2.20 Effect of mismatch on the effective resolution of SMASH

Ms [43].

Figure 2.21 Linear model of a multi‐bit

M including errors in the embedded ADC and DAC.

Figure 2.22 Parallel topology of a typical multi‐bit quantizer embedded in a

M.

Figure 2.23 Incorporating an element selection logic for applying DEM to a multi‐bit DAC.

Figure 2.24 Selection of unit elements in a 15‐element DAC according to the DWA algorithm in Equation 2.31. The shaded boxes indicate the elements that contribute to generate the DAC output level

for the corresponding input code

.

Figure 2.25 Illustrating the action of DWA in the noise‐shaping performance of a second‐order feedforward SC‐

M with USTF and 4‐bit quantization and

MHz.

Figure 2.26 A third‐order single‐loop

M employing dual quantization [56].

Figure 2.27 Output spectrum of a BP‐

M and a Nyquist‐rate ADC.

Figure 2.28 Typical section of an IF‐conversion receiver based on a band‐pass

ADC. For the sake of illustration, the input IF frequency

is assumed to be

and a notch frequency

is assumed in the BP‐

M and in the quadrature digital mixer.

Figure 2.29 Quadrature BP‐

Ms: (a) conceptual block diagram; (b) example of complex filter realization.

Figure 2.30 Illustrating the noise shaping of a fourth‐order quadrature BP‐

M with asymmetric NTF.

Figure 2.31 Illustration of the

LP–BP transformation of

Ms: (a) block diagram of a second‐order LP‐

M; (b) block diagram of the resulting fourth‐order

BP‐

M; (c) zero‐pole plot of the NTF of the LP‐

M; (d) zero‐pole plot of the NTF of the BP‐

M; (e) output spectrum of the LP‐

M (

; (f) output spectrum of the BP‐

M (

.

Figure 2.32 Illustration of fourth‐order band‐pass

topologies which allow the NTF optimization: (a) cascade of resonators with feedback; (b) cascade of resonators with feedforward summation.

Figure 2.33 Illustration of an LDI resonator: (a) block diagram; (b) SC implementation. Only half of the differential circuit is explicitly shown for the sake of simplicity.

Figure 2.34 Conceptual block diagram of a TI BP‐

M.

Figure 2.35 Block diagram of a second‐order polyphase BP‐

M [89].

Figure 2.36 Output spectra of the second‐order polyphase BP‐

M in Figure 2.35 for

.

Figure 2.37 Block diagram of a continuous‐time

ADC. A low‐pass

M is assumed.

Figure 2.38 Conceptual block diagrams of

Ms: (a) DT modulator; (b) CT modulator; (c) open‐loop representation of a DT‐

M; (d) open‐loop representation of a CT‐

M.

Figure 2.39 Most common DAC impulse responses: (a) nonreturn‐to‐zero (NRZ); (b) return‐to‐zero (RZ); (c) half‐delay return‐to‐zero (HRZ); (d) switched‐capacitor (SC); (e) exponential slope; (f) cosine.

Figure 2.40 Conceptual diagram of a CT‐

M for an intuitive analysis. (a) nonlinear diagram; (b) equivalent linear model.

Figure 2.41 Block diagram of single‐loop CT‐

Ms: (a) second‐order; (b)

‐th order.

Figure 2.42 SNR vs.

for a second‐order CT‐

M and different values of OSR.

Figure 2.43 Implicit AAF in CT‐

Ms: (a) equivalent system representation of a CT‐

M; (b) AAF block diagram.

Figure 2.44 Antialiasing filtering in second‐order CT‐

Ms for an input signal at 1 kHz and an aliased signal at

‐

kHz with

MHz: (a) DT‐

M output; (b) CT‐

M output.

Figure 2.45 Block diagram of a second‐order CT‐

M using the notation in [23].

Figure 2.46 Active‐RC implementation of a second‐order CT‐

M with a 1‐bit NRZ DAC.

Figure 2.47 Third‐order CT‐

M with Chebyshev loop filter approximation [23]: (a) block diagram; (b) output spectrum.

Figure 2.48 Block diagram of a cascade

‐stage CT‐

M.

Chapter 3

Figure 3.1 The main nonidealities affecting the performance of switched‐capacitor

Ms.

Figure 3.2 SC FE integrator with

input paths and finite amplifier gain

.

Figure 3.3 Degradation of the noise‐shaping of a second‐order SC‐

M with finite amplifier gain.

Figure 3.4 Influence of finite amplifier gain on the in‐band noise of SC‐

Ms: (a) second‐ and third‐order loops; (b) 2‐1‐1 cascade and fourth‐order loop. Approximate results obtained from Equations 3.10 and 3.11.

Figure 3.5 Influence of capacitor mismatch on the in‐band noise of a 2‐1‐1 SC‐

M: (a) considering the same mismatch error in all integrators; (b) individual impact of the mismatch error in each integrator for OSR = 32. Worst‐case estimations of IBN considering

in Equation 3.16.

Figure 3.6 SC FE integrator under consideration followed by a loading SC integrator.

Figure 3.7 Amplifier single‐pole model with limited output current.

Figure 3.8 Illustration of the influence of switching load conditions on the transient response of an SC integrator: (a) loading SC branches are not considered; (b) one loading SC branch with a 0.5‐pF capacitor is considered. (Vertical dashed lines indicate time positions

where the integrator ends a slew‐rate‐limited response and starts evolving linearly). Parameters used are (see Figures 3.6 and 3.7]:

,

,

,

,

,

,

, and

for the SC integrator under consideration,

and

for the loading SC integrator, and

.

Figure 3.9 Simulation results for the influence of amplifier GB on the in‐band noise of SC‐

Ms: (a) second‐ and third‐order loops; (b) 2‐1‐1 cascade. Approximate results have been obtained from Equations 3.14 and 3.16 with

.

Figure 3.10 Simulation results for a third‐order SC‐

M with

under the influence of finite amplifier slew rate: (a) effect on the in‐band noise; (b) effect on the output spectrum for

. Input signal with

and

. Generated distortion is included in the IBN computation.

Figure 3.11 Simulation results for a 2‐1‐1 SC‐

M with

under the influence of finite amplifier slew rate: (a) effect on the in‐band noise; (b) effect on the output spectrum for

. Input signal with

and

. Generated distortion is included in the IBN computation.

Figure 3.12 SC FE integrator with a single input branch.

Figure 3.13 Illustration of the influence of the switch on‐resistance on the transient response of an SC integrator with a loading SC branch. Simulation parameters used are the same as those for Figure 3.8.

Figure 3.14 Influence of switch on‐resistance on the in‐band noise of SC‐

Ms: (a) third‐order loop; (b) 2‐1‐1 cascade. Approximate results have been obtained from Equations 3.14 and 3.16 with

.

Figure 3.15 Circuit noise analysis in an SC integrator: (a) SC FE integrator with two input paths (single‐ended version); (b) equivalent circuit model for sampling, with noise sources due to switches active during

; (c) equivalent circuit model for integration, with noise sources due to switches active during

and due to the amplifier.

Figure 3.16 Illustration of the PSD of the amplifier noise showing the contributions of

and thermal noise.

Figure 3.17 Illustration of nonuniform sampling of a signal due to clock jitter. The shaded areas represent the timing uncertainties.

Figure 3.18 Illustrating the effect of clock jitter (

) in a fourth‐order BP‐

M.

Figure 3.19 Main sources of distortion in a fully‐differential SC integrator.

Figure 3.20 Illustration of the dependency of the amplifier gain on the output voltage level.

Figure 3.21 Illustration of a switch on‐state performance: (a) sketch of the on‐conductance versus input voltage; (b) simulation results of the on‐resistance versus input voltage in a 2.5‐V 0.25‐

m CMOS process.

Figure 3.22 Equivalent circuit for evaluating distortion during sampling due to switch nonlinearity.

Figure 3.23 Illustration of the switch on‐resistance nonlinearity for different transistor sizings in a 2.5‐V 0.25‐

m CMOS process.

Figure 3.24 Illustration of: (SL2) second‐order; (21) third‐order; (211mb) fourth‐order shaping in the 2‐1‐1

M. Quantization noise in the three

stages is considered as the only source of error. Input signal with

and

.

Figure 3.25 Fully‐differential SC implementation of a 2‐1‐1 multi‐bit

modulator.

Figure 3.26 Effect of noise leakages on the modulator output spectrum (

,

,

). Input signal with

and

.

Figure 3.27 Modulator effective resolution versus the number of bits in the last‐stage quantizer for varying OSR. All noise leakages are considered (

,

,

).

Figure 3.28 Influence of the amplifier dynamics on the modulator performance: (a) IBN against the amplifier transconductance for different values of the amplifier output current; (b) output spectrum for

and different amplifier output currents. Input signal with

and

. Noise leakages and thermal noise are also accounted for in the behavioral simulations.

Chapter 4

Figure 4.1 Main nonidealities affecting the performance of continuous‐time

Ms.

Figure 4.2 Conceptual schematic of most common circuit techniques for realizing CT integrators: (a) active‐RC; (b) OTA‐RC; (c) Gm‐C.

Figure 4.3 Examples of CT resonators using: (a) Gm‐C integrators [1]; (b) single‐opamp active‐RC integrators [2].

Figure 4.4 Active‐RC integrator with

input paths and finite amplifier gain.

Figure 4.5 Gm‐C integrator with

input paths and finite amplifier gain.

Figure 4.6 Effect of

on the SNR of a second‐order single‐bit CT‐

M.

Figure 4.7 Simulation results for the in‐band noise of CT‐

Ms under the influence of time‐constant errors: (a) second‐order single‐loop. (b) third‐order single‐loop. (c) 2‐1‐1 cascade. Simulation results have been obtained for an input signal with

and

and for an NRZ rectangular feedback. Approximate results have been obtained from Equations 4.12 and 4.13.

Figure 4.8 Model of GB in CT‐

Ms, as proposed by Ortmanns

et al

. [14].

Figure 4.9 Conceptual model of finite slew rate in CT integrators.

Figure 4.10 Illustrating the effect of SR on a second‐order single‐bit Gm‐C

M (

MHz,

V

s).

Figure 4.11 The main sources of distortion in active‐RC integrators.

Figure 4.12 Behavioral model of nonlinearity in CT integrators [17]: (a) Gm‐C integrator; (b) active‐RC integrator.

Figure 4.13 Illustrating the effect of nonlinearities on single‐bit and multi‐bit CT‐

Ms as predicted by Sankar and Pavan [17]. A fifth‐order single‐loop with feedforward topology is considered, using 5‐bit quantization and a

third‐order nonlinear coefficient.

Figure 4.14 Influence of the DAC slew rate limitation on the feedback charge for: (a) NRZ DAC, causing a signal‐dependent charge error (ISI); (b) RZ DAC, causing a constant charge error.

Figure 4.15 Circuit noise sources in a CT active‐RC integrator with two input paths. Single‐ended version.

Figure 4.16 Model of noise sources of different feedback DACs on CT‐

Ms: (a) NRZ; (b) SC; (c) RZ; (d) RTO [23].

Figure 4.17 Clock jitter in CT‐

Ms: (a) main error sources. (b) jittered rectangular (NRZ, RZ) DAC waveforms; (c) jittered SC DAC waverforms.

Figure 4.18 Detail of the jitter effect on the feedback signal of a single‐bit CT‐

M: (a) NRZ DAC. (b) RZ DAC. The gray shaded areas represent the timing uncertainties. A pulse sequence of

is considered.

Figure 4.19 Illustration of the jitter effect on the feedback signal of a multi‐bit CT‐

M: (a) NRZ DAC; (b) RZ DAC. The gray shaded areas represent the timing uncertainties.

Figure 4.20 Illustration of the jitter effect on the feedback signal of a CT‐

M with an SC DAC. The gray shaded areas represent the timing uncertainties. A pulse sequence of

is considered.

Figure 4.21 Effect of sampling frequency on the various terms affecting the IBN due to clock jitter in a 5‐bit third‐order CT‐

M [38].

Figure 4.22 Illustrating the effect of signal frequency on the IBN due to clock jitter in a third‐order CT‐

M, for

MHz and: (a)

; (b)

[38].

Figure 4.23 FIR‐DAC based single‐bit CT‐

Ms [45].

Figure 4.24 Sine‐shaped feedback DACs to attenuate the effect of clock jitter error [49].

Figure 4.25 Illustration of excess loop delay in a second‐order CT‐

M: (a) effect on an NRZ DAC pulse; (b) equivalent diagram with an explicit delay block between the ADC and the DAC.

Figure 4.26 Unstable behavior in the front‐end integrator of a second‐order LP CT‐

M due to ELD for: (a)

(ideal case); (b)

(stability condition limit); (c)

(unstable behavior).

Figure 4.27 Effect of ELD in a fourth‐order BP CT‐

M with multi‐feedback DAC path [25]: (a) block diagram of the modulator; (b) transient response of the front‐end resonator; (b) output spectrum of the modulator.

Figure 4.28 Classical approach for compensating ELD in a second‐order CT‐

M.

Figure 4.29 ELD compensation techniques proposed by: (a) Pavan [59]; (b) Fontaine

et al

. [61].

Figure 4.30 Illustrating the signal‐dependent delay in a regenerative‐latch comparator when considering the model in [66] for

and

varying within (

–

)

.

Figure 4.31 Quantizer delay versus input level: (a) ideal characteristic; (b) real characteristic as the addition of components due to constant excess delay, metastability, and hysteresis [26].

Figure 4.32 Effect of quantizer metastability in a fifth‐order single‐loop CT‐

M with feedforward summation ( 

MHz, OSR 

) [67].

Figure 4.33 Towards the architectural compensation of timing errors in CT‐

Ms: (a) conventional architecture suffering from signal‐dependent loop delay; (b) alternative architecture with extra half‐clock delay and tuning of loop coefficients [26]; (c) alternative architecture for compensating both excess loop delay and quantizer metastability [9].

Figure 4.34 Second‐order CT‐

M with additional latches in the quantizer to reduce metastability [68].

Chapter 5

Figure 5.1 Hierarchical synthesis methodology: (a) conceptual block diagram; (b) system partitioning commonly used in

Ms [1].

Figure 5.2 Iterative procedure usually followed for high‐level and cell‐level sizing.

Figure 5.3 Comparison of simulation approaches in terms of CPU time and accuracy.

Figure 5.4 Conceptual block diagram of the behavioral modeling and simulation process.

Figure 5.5 Conceptual schematic of: (a) SC FE integrator; (b) Gm‐C integrator.

Figure 5.6 Flow chart used for computing behavioral Equation 5.1.

Figure 5.7 Ideal SIMULINK models of the integrators shown in Figure 5.5.

Figure 5.8 Modeling OTA finite DC gain in: (a) SC FE integrators; (b) Gm‐C integrators.

Figure 5.9 Modeling the effect of finite DC gain on the integrators transfer function in SIMULINK.

Figure 5.10 MATLAB code for the behavioral model of the SC FE integrator in Figure 5.8a including the effect of the amplifier gain nonlinearity.

Figure 5.11 Meaning of count in the behavioral model of an SC FE integrator, considering that the input switch clock phase is: (a)

. (b)

.

Figure 5.12 SIMULINK model of the SC FE integrator shown in Figure 5.8a: (a) SIMULINK mask; (b) SIMULINK block diagram including a MATLAB function; (c) associated dialogue window.

Figure 5.13 SIMULINK model of a cascade 2‐1‐1 SC‐

M with nonlinear DC gain modeled using the M‐file shown in Figure 5.10.

Figure 5.14 SIMULINK model of a cascade 2‐1‐1 SC‐

M using Brigatti's toolbox (34].

Figure 5.15 Procedure to incorporate a behavioral model into the MATLAB/SIMULINK environment using C‐MEX S‐functions: (a) Conceptual step‐by‐step flow. (b) Illustrating the process for an SC FE integrator with finite nonlinear DC gain.

Figure 5.16 MATLAB C‐coded S‐function file of the integrator in Figure 5.10.

Figure 5.17 C code included in the

mdlOutputs

section of the S‐function file in Figure 5.16.

Figure 5.18 Illustrating the implementation of the S‐function of Figure 5.16 in SIMULINK.

Figure 5.19 Illustrating the behavioral model of a second‐order

M using S‐functions: (a) SC implementation; (b) Gm‐C implementation.

Figure 5.20 Flow chart of the SC FE integrator computational model.

Figure 5.21 Excerpt of the MATLAB C‐coded S‐function file of an SC FE integrator considering all circuit errors: Model parameters, definition of clock‐phase timing, and calculation of integrator weight including mismatch (Part 1 of 3).

Figure 5.22 Excerpt of MATLAB C‐coded S‐function file of an SC FE integrator considering all circuit errors: calculation of equivalent load capacitances, input‐referred thermal noise, capacitor nonlinearity, incomplete settling during sampling phase, nonlinear finite opamp DC gain, and output swing (Part 2 of 3).

Figure 5.23 Excerpt of MATLAB C‐coded S‐function file of an SC FE integrator considering all circuit errors: calculation of incomplete settling during integration phase, capacitor nonlinearity, nonlinear finite opamp DC gain, and output swing (Part 3 of 3).

Figure 5.24 Front‐end part of a fully‐differential SC integrator during the sampling phase.

Figure 5.25 Excerpt of the C‐coded S‐function file including the model of finite (nonlinear) switch on‐resistance.

Figure 5.26 Modeling the nonlinear switch on‐resistance as a polynomial function of the input signal: (a) equivalent circuit. (b) flow chart.

Figure 5.27 Illustrating the use of

From

and

Goto

SIMULINK blocks to transmit information between the models of two SC FE integrators in a second‐order

M.

Figure 5.28 Equivalent circuit of a Gm‐C integrator considering a single‐pole model.

Figure 5.29 Flow chart of the Gm‐C integrator computational model.

Figure 5.30 C‐coded S‐function file of a Gm‐C integrator with a single‐pole dynamic.

Figure 5.31 Illustrating the incorporation of the Gm‐C integrator S‐function in SIMULINK.

Figure 5.32 Equivalent circuit of a Gm‐C integrator considering a two‐pole model [6].

Figure 5.33 Excerpt of the S‐function of a Gm‐C integrator considering a two‐pole model.

Figure 5.34 Gm‐C integrator implemented as a transconductor and an output impedance circuit: (a) conceptual schematic. (b) implementation in SIMULINK.

Figure 5.35 Illustrating the behavioral model of multi‐level ADCs: (a) S‐function block; (b) excerpt of the C code.

Figure 5.36 Conceptual block diagram of the behavioral model used for the quantizer embedded in

Ms [13]: (a) ADC; (b) DAC.

Figure 5.37 Illustrating the behavioral model of multi‐bit DACs: (a) S‐function block; (b) excerpts of the C code, including the model of DAC transient response delay, clock jitter, and waveform selection.

Figure 5.38 Classification of SIMSIDES model libraries.

Figure 5.39 Illustrating some SIMSIDES model libraries.

Figure 5.40 SIMSIDES library including different SC FE integrator model approaches.

Figure 5.41 General structure of SIMSIDES.

Figure 5.42 Illustrating some parts of the SIMSIDES GUI.

Figure 5.43 Creating the block diagram of a cascade 2‐1 SC‐

M in SIMSIDES.

Figure 5.44 Computing IBN in SIMSIDES: (a) user window; (b) in‐band output spectrum.

Figure 5.45 Computing SNDR versus input amplitude in SIMSIDES: (a) user window; (b) SNDR versus input amplitude.

Figure 5.46 Second‐order SC‐

M case study: (a)

‐domain block diagram; (b) SIMSIDES implementation; (c) symbol of a two‐branch SC integrator in SIMSIDES and its equivalent circuit.

Figure 5.47 (a) Ideal output spectrum of the modulator in Figure 5.46; (b) IBN for

.

Figure 5.48 SNDR versus

of the

M in Figure 5.46 for different values of OSR.

Figure 5.49 Effect of thermal noise sources on the

M in Figure 5.46: (a) SNR versus

; (b) SNR versus

.

Figure 5.50 Effect of incomplete settling on the

M in Figure 5.46 for

kHz: (a) SNDR versus

for

mA; (b) SNR versus

for

5 mA/V.

Figure 5.51 Illustrating the cumulative and isolated effect of the amplifier output current

.

Figure 5.52 Output spectrum of the

M in Figure 5.46 considering the effect of all circuit errors.

Figure 5.53 SNDR versus input signal level for

kHz considering all circuit errors.

Figure 5.54 Information provided by the SIMSIDES SC FE integrator model when the effect of switch on‐resistance is taken into account in the transient response.

Figure 5.55 Gm‐C fifth‐order cascade 3‐2

M with 4‐bit quantization in both stages: (a) conceptual schematic; (b) SIMSIDES implementation.

Figure 5.56 Ideal simulation results of the modulator in Figure 5.55: (a) output spectrum; (b) SNDR versus input signal level for

(

20 MHz,

240 MHz), considering a full‐scale reference of 0.5 V.

Figure 5.57 Effect of finite DC gain of loop‐filter transconductors on the SNDR of Figure 5.55 for different values of OSR.

Figure 5.58 Effect of transconductance nonlinearity on the performance of the CT‐

M in Figure 5.55: (a) output spectrum assuming that

and

are ideal and that all loop‐filter transconductors have an IIP3

dBm; (b) output spectrum considering that all transconductors are ideal, except for

that has an IIP3

dBm; (c) SNDR versus IIP3 for the different transconductors.

Figure 5.59 Illustrating the effect of mismatch on the SNR of the

M in Figure 5.55.

Figure 5.60 SNDR versus input signal level considering all nonideal effects in Figure 5.55.

Chapter 6

Figure 6.1 Block diagram of CRFF

M with the loop‐filter coefficients used in Schreier's MATLAB toolbox (1].

Figure 6.2 State‐space representation of a

M [1].

Figure 6.3 MATLAB script with Schreier's toolbox functions used for the loop‐filter synthesis of a CRFF SC‐

M with reconfigurable notch frequency [6].

Figure 6.4 Ideal NTF of the CRFF reconfigurable LP/BP

M synthesized with the script shown in Figure 6.3 for

,

, and

.

Figure 6.5 NTF and loop‐filter coefficients of the CRFF LP/BP SC‐

M (

).

Figure 6.6 Conceptual schematic of the synthesized LP/BP CRFF SC‐

M.

Figure 6.7 Ideal output spectra of the synthesized CRFF LP/BP SC‐

M for: (a) LP case (

); (b)

; (c)

.

Figure 6.8 Block diagram of a fourth‐order BP CT‐

M with tunable notch [7].

Figure 6.9 MATLAB script with Schreier's toolbox functions used for the loop‐filter synthesis of the BP CT‐

M [7].

Figure 6.10 Conceptual Gm‐LC realization of the synthesized BP CT‐

M [8].

Figure 6.11 Flow diagram of the optimization‐based synthesis of

Ms [11].

Figure 6.12 SIMSIDES diagram of a cascade 2‐1 SC‐

M used as an example for an optimization‐based synthesis.

Figure 6.13 MATLAB script used to define model parameters required for the simulation of Figure 6.12.

Figure 6.14 Illustrating the use of SIMSIDES to set the optimization of

Ms: (a) launching optimization menu; (b) setting variables and model parameters; (c) setting design variables; (d) optimization targets and objectives; (e) setting main (global) optimization algorithm; (f) setting local optimization algorithm.

Figure 6.15 Example of FRIDGE input netlist.

Figure 6.16 Evolution of temperature and cost function of the synthesis procedure of a cascade 2‐1 SC‐

M using simulated annealing optimization [11].

Figure 6.17 Result of the high‐level synthesis of a cascade 2‐1 SC‐

M combining simulated annealing and SIMSIDES.

Figure 6.18 Output spectrum of the cascade 2‐1‐1 SC‐

M synthesized in Table 6.1. Experimental measurement matches behavioral simulations obtained from the optimization‐based synthesis process [11].

Figure 6.19 Combining SIMSIDES and SIMULINK optimization toolbox: (a) SIMSIDES optimization main menu; (b) launching SIMULINK optimization toolbox from a SIMSIDES model; (c) optimization toolbox main window.

Figure 6.20 SIMSIDES optimization interface.

Figure 6.21 Result of the high‐level synthesis of a cascade 2‐1 SC‐

M by combining SIMSIDES and genetic algorithms available in MATLAB. Two main design objectives are considered: (a) maximize SNR; (b)

dB.

Figure 6.22 CT state‐space representation of a CT‐

M.

Figure 6.23 DT state‐space representation of a CT‐

M with lifting method [17].

Figure 6.24 Emulation of CT‐

Ms on FPGAs for synthesis purposes [18].

Figure 6.25 Web‐based user interface of the synthesis tool for CT‐

Ms developed by Ortmanns' group (www.sigma‐delta.de] [20].

Figure 6.26 Outcome of the optimization process of a fourth‐order CRFF CT‐

M using the web‐based synthesis tool for CT‐

Ms (www.sigma‐delta.de] [20]: (a) block diagram and synthesized loop‐filter coefficients; (b) optimized values of

and GBW and STF specifications; (c) output spectrum; (d) SNR versus input signal.

Figure 6.27 An illustration of the evolution towards the Pareto‐optimal front [13].

Figure 6.28 Conceptual diagram of the MOAE‐based optimization of

Ms.

Figure 6.29 Illustrating the use of SIMSIDES with NGSA‐II optimization engine: (a) launching optimization menu; (b) selecting the optimization script; (c) example of optimization script; (d) intermediate results of the optimization process displayed at the MATLAB workspace;(e) progress bar showing the status of the optimization; (f) final results plotted as a PoF.

Figure 6.30 Excerpt of MATLAB script used for the optimization of SIMSIDES with NSGA‐II (Part 1). The interested reader can see also more details about NSGA‐II code at www.mathworks.com/matlabcentral/fileexchange.

Figure 6.31 Excerpt of MATLAB script used for the optimization of SIMSIDES with NSGA‐II (Part 2). The interested reader can see also more details about NSGA‐II code at www.mathworks.com/matlabcentral/fileexchange.

Figure 6.32 Pareto fronts obtained for three different operation modes of Figure 6.10.

Figure 6.33 Comparison of the MOEA-based optimization methodology with conventional design procedure and exhaustive search, for the three operation modes [13].

Figure 6.34 Output spectra of the conventional and selected designs for the Mode‐1 POF plot of Figure 6.10 [13].

Figure 6.35 SNDR versus input signal amplitude for the conventional and the selected design for the Mode‐1 POF plot of Figure 6.10.

Chapter 7

Figure 7.1 Conceptual step‐by‐step design flow of

Ms.

Figure 7.2 Macromodel of a single‐ended FE SC integrator.

Figure 7.3 Macromodel of a fully‐differential FE SC integrator.

Figure 7.4 Macromodel of a CMOS switch.

Figure 7.5 Active‐RC integrator macromodel: (a) single‐ended schematic; (b) fully‐differential schematic.

Figure 7.6 Gm‐C integrator macromodel: (a) two‐pole linear model; (b) one‐pole weakly nonlinear model.

Figure 7.7 Macromodeling multi‐level flash ADCs: (a) conceptual schematic of a trilevel flash ADC; (b) static differential transfer characteristic.

Figure 7.8 Verilog‐A code for simulating comparators in quantizer macromodels [10, 11].

Figure 7.9 Macromodel of a trilevel SC DAC connected to an SC FE integrator within a

M loop filter. Note that different SC branches, using two different sampling capacitors

and

, are used in this model. However, there are many situations in practice where a single SC branch is shared by both the input signal and the feedback DAC, as will be shown later in this chapter.

Figure 7.10 Illustrating the macromodel of a trilevel current‐steering DAC connected to a Gm‐C integrator within a

M loop filter.

Figure 7.11 Conceptual schematic of a second‐order SC‐

M with a trilevel embedded quantizer.

Figure 7.12 Implementation of the modulator in Figure 7.11 using Cadence Virtuoso schematics.

Figure 7.13 Schematic of the SC first integrator of Figure 7.12.

Figure 7.14 Selection of a circuit view name in the Cadence IC Design environment for the operational amplifier shown in Figure 7.13.

Figure 7.15 Illustrating the macromodel implementation of different circuit elements of SC integrators in the Cadence Design Framework: (a) fully‐differential amplifier; (b) switch.

Figure 7.16 Conceptual schematic of a second‐order active‐RC

M with a trilevel embedded quantizer and CS feedback DACs.

Figure 7.17 Schematic of the modulator in Figure 7.16 implemented in the Cadence Virtuoso schematic editor: (a) modulator; (b) active‐RC integrator.

Figure 7.18 Illustrating the macromodel implementation of a trilevel quantizer in the Cadence Virtuoso schematic editor: (a) flash ADC; (b) current‐steering DAC.

Figure 7.19 Injecting noise data sequences in transient HSPICE simulations: (a) sampling circuit example; (b) SPICE netlist.

Figure 7.20 MATLAB code used for generating a

‐point data sequence derived from Equation 7.9.

Figure 7.21 Illustrating the effect of sampling noise in HSPICE transient simulations. Output spectrum of the voltage stored in

in Figure 7.19a, considering the following simulation data:

,

pF,

1 MHz.

Figure 7.22 Equivalent single‐ended circuits used for simulating the effect of the main noise sources in SC integrators: (a) noise contribution of switches controlled by

; (b) noise contribution of switches controlled by

; (c) noise contribution of the amplifier.

Figure 7.23 HSPICE netlist of the circuits shown in Figure 7.22.

Figure 7.24 MATLAB code used for generating colored noise data sequence extracted from HSPICE

.NOISE

simulation.

Figure 7.25 MATLAB code used for generating colored noise data sequence extracted from HSPICE

.NOISE

simulation.

Figure 7.26 Test‐bench example to inject noise in transient simulations of

Ms using the Cadence Spectre simulator: (a) schematic in the Virtuoso editor environment; (b) object properties windows highlighting how to load the noise data sequence file.

Figure 7.27 MATLAB code used for generating an

‐point data sequence derived from Equation 7.11.

Figure 7.28 Output spectrum of a fourth‐order cascade 2‐2 SC‐

M. The simulation was carried out in Cadence Spectre, considering macromodels for all building blocks and injecting the input‐referred noise source, as illustrated in Figure 7.26.

Figure 7.29 Step‐by‐step procedure to process electrical simulation outputs.

Figure 7.30 Collecting and storing the output bitstreams of a

M in an electrical simulation: (a) test‐bench schematic in Cadence Design FrameWork; (b) Verilog‐A code to capture simulation output results; (c) excerpt of the generated output file (text format).

Figure 7.31 MATLAB routine used for processing

M outputs from electrical simulations: (a) MATLAB code; (b) DCL block diagram implemented in SIMULINK.

Chapter 8

Figure 8.1 Switch symbol and its equivalent CMOS circuit.

Figure 8.2 Characterizing nonlinear switch on‐resistance: (a) test‐bench circuit; (b) HSPICE netlist; (c)

versus

considering a 90‐nm CMOS technology with 1.2‐V supply voltage.

Figure 8.3

versus

for minimum channel length and different values of

, considering a 90‐nm CMOS technology with 1.2‐V supply voltage.

Figure 8.4 Illustrating the effect of technology downscaling on

.

Figure 8.5 Characterizing harmonic distortion caused by nonlinear sampling: (a) test‐bench equivalent circuit; (b) practical (simplified) version of the test‐bench circuit; (c) HSPICE netlist. A test‐bench circuit with

and

can be used as well.

Figure 8.6 Impact of increasing the input signal frequency on the variation of

over the sampling period. A fully‐differential sinewave input signal of frequency

is considered with

MHz. This figure plots both positive and negative single‐ended inputs.

Figure 8.7 Illustrating the impact of increasing the input signal frequency on the harmonic distortion caused by nonlinear sampling process. Three cases of

are considered:

,

, and

, where

MHz.

Figure 8.8 Intermodulation distortion caused by the nonlinear sampling operation. Data used in the simulation: 90‐nm CMOS technology,

V,

m,

m,

nm,

.

Figure 8.9 Amplifier topologies commonly employed in

modulators: (a) telescopic amplifier; (b) folded cascode amplifier; (c) folded cascode amplifier with gain boosting; (d) two‐stage amplifier with Miller compensation.

Figure 8.10 Conceptual schematic of a third‐stage feedforward amplifier used in wideband CT‐

Ms [9].

Figure 8.11 Folded cascode amplifier: (a) core circuit; (b) bias circuit.

Figure 8.12 Alternative implementations of the common‐mode feedback: (a) SC circuit; (b) CT circuit; (c) ideal circuit for simulation purposes.

Figure 8.13 HSPICE netlist for the AC characterization of the folded cascode amplifier in Figure 8.11.

Figure 8.14 Amplifier simulation results obtained from an AC analysis: (a) test‐bench circuit; (b) open‐loop amplifier frequency response; (c) input‐referred noise PSD.

Figure 8.15 Amplifier simulation results obtained from a DC analysis: (a) test‐bench circuit. (b) I–V transfer characteristic; (c) transconductance versus input voltage.

Figure 8.16 Amplifier simulation results obtained from a DC analysis: (a) test‐bench circuit; (b) open‐loop voltage transfer characteristic; (c) amplifier gain versus output voltage.

Figure 8.17 Illustrating the use of transconductors in a third‐order single‐loop CT‐

M, considering: (a) active‐RC front‐end integrator; (b) Gm‐C front‐end integrator.

Figure 8.18 Example of

M front‐end transconductor with enhanced linearity [13].

Figure 8.19 Example of

M loop‐filter transconductor with quadratic‐term cancellation technique [13].

Figure 8.20 Illustrating the electrical performance of

M loop‐filter transconductors: (a) output current versus input voltage for different values of the tuning current

; (b) transconductance versus input voltage.

ranges from

A to

A.

Figure 8.21 Cadence Virtuoso test‐bench schematic used for characterizing the

M loop‐filter transconductors. Note that this test bench can be used for DC, AC, and transient analysis. Alternatively, a load circuit can be connected at the output of the transconductor in order to emulate a circuit environment closer to the actual situation of loop‐filter transcondutors embedded in a CT‐

M.

Figure 8.22 Frequency response of the loop‐filter (unit) transconductor in Figure 8.19.