Computer Principles and Design in Verilog HDL E-Book

Yamin Li

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 849

Veröffentlichungsjahr: 2015

Beschreibung

Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills * Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design * Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation * Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques * A companion website includes color figures, Verilog HDL codes, extra test benches not found in the book, and PDFs of the figures and simulation waveforms for instructors

Leseprobe

Table of Contents

Cover

Title Page

Copyright

List of Figures

List of Tables

Preface

Chapter 1: Computer Fundamentals and Performance Evaluation

1.1 Overview of Computer Systems

1.2 Basic Structure of Computers

1.3 Improving Computer Performance

1.4 Hardware Description Languages

Exercises

Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL

2.1 Logic Gates

2.2 Logic Circuit Design in Verilog HDL

2.3 CMOS Logic Gates

2.4 Four Levels/Styles of Verilog HDL

2.5 Combinational Circuit Design

2.6 Sequential Circuit Design

Exercises

Chapter 3: Computer Arithmetic Algorithms and Implementations

3.1 Binary Integers

3.2 Binary Addition and Subtraction

3.3 Binary Multiplication Algorithms

3.4 Binary Division Algorithms

3.5 Binary Square Root Algorithms

Exercises

Chapter 4: Instruction Set Architecture and ALU Design

4.1 Instruction Set Architecture

4.2 MIPS Instruction Format and Registers

4.3 MIPS Instructions and AsmSim Tool

4.4 ALU Design

Exercises

Chapter 5: Single-Cycle CPU Design in Verilog HDL

5.1 The Circuits Required for Executing an Instruction

5.2 Register File Design

5.3 Single-Cycle CPU Datapath Design

5.4 Single-Cycle CPU Control Unit Design

5.5 Test Program and Simulation Waveform

Exercises

Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL

6.1 Exceptions and Interrupts

6.2 Design of CPU with Exception and Interrupt Mechanism

6.3 The CPU Exception and Interrupt Tests

Exercises

Chapter 7: Multiple-Cycle CPU Design in Verilog HDL

7.1 Dividing Instruction Execution into Several Clock Cycles

7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes

7.3 Multiple-Cycle CPU Control Unit Design

7.4 Memory and Test Program

Exercises

Chapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL

8.1 Pipelining

8.2 Pipeline Hazards and Solutions

8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes

8.4 Precise Interrupts/Exceptions in Pipelined CPU

8.5 Design of Pipelined CPU with Precise Interrupt/Exception

Exercises

Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL

9.1 IEEE 754 Floating-Point Data Formats

9.2 Converting between Floating-Point Number and Integer

9.3 Floating-Point Adder (FADD) Design

9.4 Floating-Point Multiplier (FMUL) Design

9.5 Floating-Point Divider (FDIV) Design

9.6 Floating-Point Square Root (FSQRT) Design

Exercises

Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL

10.1 CPU/FPU Pipeline Model

10.2 Design of Register File with Two Write Ports

10.3 Data Dependency and Pipeline Stalls

10.4 Pipelined CPU/FPU Design in Verilog HDL

10.5 Memory Modules and Pipelined CPU/FPU Test

Exercises

Chapter 11: Memory Hierarchy and Virtual Memory Management

11.1 Memory

11.2 Cache Memory

11.3 Virtual Memory Management and TLB Design

11.4 Mechanism of TLB-Based MIPS Memory Management

Exercises

Chapter 12: Design of Pipelined CPU with Caches and TLBs in Verilog HDL

12.1 Overall Structure of Caches and TLBs

12.2 Design of Circuits Related to Caches

12.3 Design of Circuits Related to TLB

12.4 Design of CPU with Caches and TLBs

12.5 Simulation Waveforms of CPU with Caches and TLBs

Exercises

Chapter 13: Multithreading CPU and Multicore CPU Design in Verilog HDL

13.1 Overview of Multithreading CPUs

13.2 Multithreading CPU Design

13.3 Overview of Multicore CPUs

13.4 Multicore CPU Design

Exercises

Chapter 14: Input/Output Interface Controller Design in Verilog HDL

14.1 Overview of Input/Output Interface Controllers

14.2 Error Detection and Correction

14.3 Universal Asynchronous Receiver Transmitter

14.4 PS/2 Keyboard/Mouse Interface Design

14.5 Video Graphics Array (VGA) Interface Design

14.6 Input/Output Buses

Exercises

Chapter 15: High-Performance Computers and Interconnection Networks

15.1 Category of High-Performance Computers

15.2 Shared-Memory Parallel Multiprocessor Systems

15.3 Inside of Interconnection Networks

15.4 Topological Properties of Interconnection Networks

15.5 Some Popular Topologies of Interconnection Networks

15.6 Collective Communications

15.7 Low-Node-Degree Short-Diameter Interconnection Networks

Exercises

Bibliography

Index

End User License Agreement

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Guide

Cover

Table of Contents

Preface

Begin Reading

List of Illustrations

Chapter 1: Computer Fundamentals and Performance Evaluation

Figure 1.1 Computer system organization

Figure 1.2 Simplified structure of RISC CPU

Figure 1.3 Simplified structure of pipelined CPU

Figure 1.4 On-chip dedicated instruction cache and data cache

Figure 1.5 Simplified structure of a multithreading CPU

Figure 1.6 Simplified structure of a multicore CPU

Figure 1.7 Memory hierarchy

Figure 1.8 TLB maps virtual address to physical address

Figure 1.9 I/O interfaces in a computer system

Figure 1.10 Amdahl's Law examples

Figure 1.11 Trace-driven simulation

Figure 1.12 Execution-driven simulation

Figure 1.13 Supercomputer and interconnection network

Figure 1.14 Waveform of time counter

Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL

Figure 2.1 Three basic gates and four common gates

Figure 2.2 Karnaugh map for a 2-to-1 multiplexer

Figure 2.3 Schematic diagram of a 2-to-1 multiplexer

Figure 2.4 Waveform of a 2-to-1 multiplexer

Figure 2.5 Schematic diagram of a CMOS inverter

Figure 2.6 Schematic diagram of NAND and NOR gates

Figure 2.7 Schematic diagram of AND and OR gates

Figure 2.8 Implementing a multiplexer using only NAND gates

Figure 2.9 Implementing a multiplexer using CMOS transistors

Figure 2.10 Schematic diagram of multiplexer using tri-state and ordinary gates

Figure 2.11 Schematic diagram of decoder with enable control

Figure 2.12 Decoder and encoder

Figure 2.13 Waveform of a 8-3 priority encoder

Figure 2.14 A 1-to-8 demultiplexer

Figure 2.15 Schematic diagram of 32-bit left shifter

Figure 2.16 Schematic diagram of 32-bit barrel shifter

Figure 2.17 Schematic diagram of a D latch

Figure 2.18 Waveform of a D latch

Figure 2.19 Schematic diagram of an academic D flip-flop

Figure 2.20 Waveform of an academic D flip-flop

Figure 2.21 Schematic diagram of an industry D flip-flop

Figure 2.22 Waveform of an industry D flip-flop

Figure 2.23 Schematic diagram of a D flip-flop with enable control

Figure 2.24 Schematic diagram of the JK latch

Figure 2.25 Schematic diagram of the JK flip-flop

Figure 2.26 Waveform of the JK flip-flop

Figure 2.27 Schematic diagram of the T latch