Computer System Design E-Book

Michael J. Flynn

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 484

Veröffentlichungsjahr: 2011

Beschreibung

The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses the issues mentioned above. It begins with a global introduction, from the high-level view to the lowest common denominator (the chip itself), then moves on to the three main building blocks of an SOC (processor, memory, and interconnect). Next is an overview of what makes SOC unique (its customization ability and the applications that drive it). The final chapter presents future challenges for system design and SOC possibilities.

Leseprobe

Table of Contents

Cover

Title page

Copyright page

PREFACE

LIST OF ABBREVIATIONS AND ACRONYMS

1  Introduction to the Systems Approach

1.1 SYSTEM ARCHITECTURE: AN OVERVIEW

1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS

1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE

1.4 PROCESSOR ARCHITECTURES

1.5 MEMORY AND ADDRESSING

1.6 SYSTEM-LEVEL INTERCONNECTION

1.7 AN APPROACH FOR SOC DESIGN

1.8 SYSTEM ARCHITECTURE AND COMPLEXITY

1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC

1.10 DEALING WITH DESIGN COMPLEXITY

1.11 CONCLUSIONS

2  Chip Basics: Time, Area, Power, Reliability, and Configurability

2.1 INTRODUCTION

2.2 CYCLE TIME

2.3 DIE AREA AND COST

2.4 IDEAL AND PRACTICAL SCALING

2.5 POWER

2.6 AREA–TIME–POWER TRADE-OFFS IN PROCESSOR DESIGN

2.7 RELIABILITY

2.8 CONFIGURABILITY

2.9 CONCLUSION

3  Processors

3.1 INTRODUCTION

3.2 PROCESSOR SELECTION FOR SOC

3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE

3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE

3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING

3.6 BUFFERS: MINIMIZING PIPELINE DELAYS

3.7 BRANCHES: REDUCING THE COST OF BRANCHES

3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR

3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS

3.10 VLIW PROCESSORS

3.11 SUPERSCALAR PROCESSORS

3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES

3.13 CONCLUSIONS

4  Memory Design: System-on-Chip and Board-Based Systems

4.1 INTRODUCTION

4.2 OVERVIEW

4.3 SCRATCHPADS AND CACHE MEMORY

4.4 BASIC NOTIONS

4.5 CACHE ORGANIZATION

4.6 CACHE DATA

4.7 WRITE POLICIES

4.8 STRATEGIES FOR LINE REPLACEMENT AT MISS TIME

4.9 OTHER TYPES OF CACHE

4.10 SPLIT I- AND D-CACHES AND THE EFFECT OF CODE DENSITY

4.11 MULTILEVEL CACHES

4.12 VIRTUAL-TO-REAL TRANSLATION

4.13 SOC (ON-DIE) MEMORY SYSTEMS

4.14 BOARD-BASED (OFF-DIE) MEMORY SYSTEMS

4.15 SIMPLE DRAM AND THE MEMORY ARRAY

4.16 MODELS OF SIMPLE PROCESSOR–MEMORY INTERACTION

4.17 CONCLUSIONS

5  Interconnect

5.1 INTRODUCTION

5.2 OVERVIEW: INTERCONNECT ARCHITECTURES

5.3 BUS: BASIC ARCHITECTURE

5.4 SOC STANDARD BUSES

5.5 ANALYTIC BUS MODELS

5.6 BEYOND THE BUS: NOC WITH SWITCH INTERCONNECTS

5.7 SOME NOC SWITCH EXAMPLES

5.8 LAYERED ARCHITECTURE AND NETWORK INTERFACE UNIT

5.9 EVALUATING INTERCONNECT NETWORKS

5.10 CONCLUSIONS

6  Customization and Configurability

6.1 INTRODUCTION

6.2 ESTIMATING EFFECTIVENESS OF CUSTOMIZATION

6.3 SOC CUSTOMIZATION: AN OVERVIEW

6.4 CUSTOMIZING INSTRUCTION PROCESSORS

6.5 RECONFIGURABLE TECHNOLOGIES

6.6 MAPPING DESIGNS ONTO RECONFIGURABLE DEVICES

6.7 INSTANCE-SPECIFIC DESIGN

6.8 CUSTOMIZABLE SOFT PROCESSOR: AN EXAMPLE

6.9 RECONFIGURATION

6.10 CONCLUSIONS

7  Application Studies

7.1 INTRODUCTION

7.2 SOC DESIGN APPROACH

7.3 APPLICATION STUDY: AES

7.4 APPLICATION STUDY: 3-D GRAPHICS PROCESSORS

7.5 APPLICATION STUDY: IMAGE COMPRESSION

7.6 APPLICATION STUDY: VIDEO COMPRESSION

7.7 FURTHER APPLICATION STUDIES

7.8 CONCLUSIONS

8  What’s Next: Challenges Ahead

8.1 INTRODUCTION

I. THE FUTURE SYSTEM: AUTONOMOUS SYSTEM-ON-CHIP

8.2 OVERVIEW

8.3 TECHNOLOGY

8.4 POWERING THE ASOC

8.5 THE SHAPE OF THE ASOC

8.6 COMPUTER MODULE AND MEMORY

8.7 RF OR LIGHT COMMUNICATIONS

8.8 SENSING

8.9 MOTION, FLIGHT, AND THE FRUIT FLY

II. THE FUTURE DESIGN PROCESS: SELF-OPTIMIZATION AND SELF-VERIFICATION

8.10 MOTIVATION

8.11 OVERVIEW

8.12 PRE-DEPLOYMENT

8.13 POST-DEPLOYMENT

8.14 ROADMAP AND CHALLENGES

8.15 SUMMARY

APPENDIX: Tools for Processor Evaluation

REFERENCES

Index

Copyright © 2011 by John Wiley & Sons, Inc. All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.

Published simultaneously in Canada.

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Library of Congress Cataloging-in-Publication Data:

Flynn, M. J. (Michael J.), 1934–

 Computer system design : system-on-chip / Michael J. Flynn, Wayne Luk.

p. cm.

Includes bibliographical references and index.

 ISBN 978-0-470-64336-5 (hardback)

 1. Systems on a chip. I. Luk, Wayne. II. Title.

 TK7895.E42F65 2011

 004.1–dc22

2010040981

oBook ISBN: 9781118009925

ePDF ISBN: 9781118009901

ePub ISBN: 9781118009918

PREFACE

The next generation of computer system designers will be concerned more about the elements of a system tailored to particular applications than with the details of processors and memories.

Such designers would have rudimentary knowledge of processors and other elements in the system, but the success of their design would depend on their skills in making system-level trade-offs that optimize the cost, performance, and other attributes to meet application requirements.

This text is organized to introduce issues in computer system design, particularly for system-on-chip (SOC). Managing such design requires knowledge of a number of issues, as shown in Figure 1.

Figure 1 An approach to SOC system design described in this book.

After Chapter 1, the introduction chapter, Chapter 2 looks at issues that define the design space: area, speed, power consumption, and configurability. Chapters 3–5 provide background knowledge of the basic elements in a system: processor, memory, and interconnect.

The succeeding chapters focus on computer systems tailored to specific applications and technologies. Chapter 6 covers issues in customizing and configuring designs. Chapter 7 addresses system-level trade-offs for various applications, bringing together earlier material in this study. Finally, Chapter 8 presents future challenges for system design and SOC possibilities.

The tools that illustrate the material in the text are still being developed. The Appendix provides an overview of one such tool. Since our tools are evolving, please check from time to time to see what is available at the companion web site: www.soctextbook.com.

Moreover, material useful for teaching, such as slides and answers to exercises, is also being prepared.

This book covers a particular approach to computer system design, with emphasis on fundamental ideas and analytical techniques that are applicable to a range of applications and architectures, rather than on specific applications, architectures, languages, and tools. We are aware of complementary treatments on these and also on other topics, such as electronic system-level design, embedded software development, and system-level integration and test. We have included brief descriptions and references to these topics where appropriate; a more detailed treatment can be covered in future editions or in different volumes.

SOC is a quickly developing field. Although we focused on funda­mental material, we were forced to draw a line on the inclusion of the latest technological advances for the sake of completing the book. Such advances, instead, are captured as links to relevant sources of information at the companion web site described above.

Many colleagues and students, primarily at Imperial College London and Stanford University, have contributed to this book. We are sorry that we are not able to mention them all by name here. However, a number of individuals deserve special acknowledgment. Peter Cheung worked closely with us from the beginning; his contributions shaped the treatment of many topics, particularly those in Chapter 5. Tobias Becker, Ray Cheung, Rob Dimond, Scott Guo, Shay Ping Seng, David Thomas, Steve Wilton, Alice Yu, and Chi Wai Yu contributed significant material to various chapters. Philip Leong and Roger Woods read the manuscript many times carefully and provided many excellent suggestions for improvement. We also greatly benefited from comments by Jeffrey Arnold, Peter Boehm, Don Bouldin, Geoffrey Brown, Patrick Hung, Sebastian Lopez, Oskar Mencer, Kevin Rudd, and several anonymous reviewers. We thank Kubilay Atasu, Peter Collingbourne, James Huggett, Qiwei Jin, Adrien Le Masle, Pete Sedcole, and Tim Todman, as well as those who prefer to remain anonymous, for their invaluable assistance.

Last, but not least, we thank Cassie Strickland, of Wiley, and Janet Hronek, of Toppan Best-set, for their help in the timely completion of this text.

LIST OF ABBREVIATIONS AND ACRONYMS

AC

Autonomous chip

A/D

Analog to digital

AES

Advanced Encryption Standard

AG

Address generation

ALU

Arithmetic and logic unit

AMBA

Advanced Microcontroller Bus Architecture

ASIC

Application-specific integrated circuit

ASIP

Application-specific instruction processor

ASOC

Autonomous system-on-chip

AXI

Advanced eXtensible Interface

BC

Branch conditional

BIST

Built-in-self-test

BRAM

Block random access memory

BTB

Branch target buffer

CAD

Computer aided design

CBWA

Copy-back write allocate cache

CC

Condition codes

CFA

Color filter array

CGRA

Coarse-grained reconfigurable architecture

CIF

Common Intermediate Format

CISC

Complex instruction set computer

CLB

Configurable Logic Block

CMOS

Complementary metal oxide semiconductor

CORDIC

COordinate Rotation Digital Computer

CPI

Cycles per instruction

CPU

Central processing unit

DCT

Discrete Cosine Transform

DDR

Double data rate

DES

Data Encryption Standard

3DES

Triple Data Encryption Standard

DF

Data fetch

DMA

Direct memory access

DRAM

Dynamic random access memory

DSP

Digital signal processing (or processor)

DTMR

Design Target Miss Rates

ECC

Error correcting code

eDRAM

Embedded dynamic random access memory

EX

Execute

FIFO

First in first out

FIR

Finite impulse response

FO4

Fan-out of four

FP

Floating-point

FPGA

Field programmable gate array

FPR

Floating-point register

FPU

Floating-point unit

GB

Giga bytes, a billion (109) bytes

GIF

Graphics interface

GPP

General-purpose processor

GPR

General-purpose register

GPS

Global Positioning System

GSM

Global System for Mobile Communications

HDTV

High definition television

HPC

High performance computing

IC

Integrated circuit

ICU

Interconnect interface unit

ID

Instruction decode

IF

Instruction fetch

ILP

Instruction-level parallelism

I/O

Input/output

IP

Intellectual property

IR

Instruction register

ISA

Instruction set architecture

JPEG

Joint Photographic Experts Group (image compression standard)

Kb

Kilo bits, one thousand (103) bits

KB

Kilo bytes, one thousand bytes

L1

Level 1 (for cache)

L2

Level 2 (for cache)

LE

Logic Element

LRU

Least recently used

L/S

Load-store

LSI

Large scale integration

LUT

Lookup table

Mb

Mega bits, one million (106) bits

MB

Mega bytes, one million bytes

MEMS

Micro electro mechanical systems

MIMD

Multiple instruction streams, multiple data streams

MIPS

Million instructions per second

MOPS

Million operations per second

MOS

Metal oxide semiconductor

MPEG

Motion Picture Experts Group (video compression standard)

MTBF

Mean time between faults

MUX

Multiplexor

NOC

Network on chip

OCP

Open Core Protocol

OFDM

Orthogonal Frequency-Division Multiplexing

PAN

Personal area network

PCB

Printed circuit board

PLCC

Plastic leaded chip carrier

PROM

Programmable read only memory

QCIF

Quarter Common Intermediate Format

RAM

Random access memory

RAND

Random

RAW

Read-after-write

rbe

Register bit equivalent

RF

Radio frequency

RFID

Radio frequency identification

RISC

Reduced instruction set computer

R/M

Register-memory

ROM

Read only memory

RTL

Register transfer language

SAD

Sum of the absolute differences

SDRAM

Synchronous dynamic random access memory

SECDED

Single error correction, double error detection

SER

Soft error rate

SIA

Semiconductor Industry Association

SIMD

Single instruction stream, multiple data streams

SMT

Simultaneous multithreading

SOC

System on chip

SRAM

Static random access memory

TLB

Translation look-aside buffer

TMR

Triple modular redundancy

UART

Universal asynchronous receiver/transmitter

UMTS

Universal mobile telecommunications system

UV

Ultraviolet

VCI

Virtual Component Interface

VLIW

Very long instruction word

VLSI

Very large scale integration

VPU

Vector processing unit

VR

Vector register

VSIA

Virtual Socket Interface Alliance

WAR

Write after read

WAW

Write after write

WB

Write back

WTNWA

Write-through cache, no write allocate

1

Introduction to the Systems Approach

1.1 SYSTEM ARCHITECTURE: AN OVERVIEW

The past 40 years have seen amazing advances in silicon technology and resulting increases in transistor density and performance. In 1966, Fairchild Semiconductor [84] introduced a quad two input NAND gate with about 10 transistors on a die. In 2008, the Intel quad-core Itanium processor has 2 billion transistors [226]. Figures 1.1 and 1.2 show the unrelenting advance in improving transistor density and the corresponding decrease in device cost.

Figure 1.1 The increasing transistor density on a silicon die.

Figure 1.2 The decrease of transistor cost over the years.

The aim of this book is to present an approach for computer system design that exploits this enormous transistor density. In part, this is a direct extension of studies in computer architecture and design. However, it is also a study of system architecture and design.

About 50 years ago, a seminal text, Systems Engineering—An Introduction to the Design of Large-Scale Systems [111], appeared. As the authors, H.H. Goode and R.E. Machol, pointed out, the system’s view of engineering was created by a need to deal with complexity. As then, our ability to deal with complex design problems is greatly enhanced by computer-based tools.

A system-on-chip (SOC) architecture is an ensemble of processors, memories, and interconnects tailored to an application domain. A simple example of such an architecture is the Emotion Engine [147, 187, 237] for the Sony PlayStation 2 (Figure 1.3), which has two main functions: behavior simulation and geometry translation. This system contains three essential components: a main processor of the reduced instruction set computer (RISC) style [118] and two vector processing units, VPU0 and VPU1, each of which contains four parallel processors of the single instruction, multiple data (SIMD) stream style [97]. We provide a brief overview of these components and our overall approach in the next few sections.

Figure 1.3 High-level functional view of a system-on-chip: the Emotion Engine of the Sony PlayStation 2 [147, 187].

While the focus of the book is on the system, in order to understand the system, one must first understand the components. So, before returning to the issue of system architecture later in this chapter, we review the components that make up the system.

1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS

The term architecture denotes the operational structure and the user’s view of the system. Over time, it has evolved to include both the functional specification and the hardware implementation. The system architecture defines the system-level building blocks, such as processors and memories, and the interconnection between them. The processor architecture determines the processor’s instruction set, the associated programming model, its detailed implementation, which may include hidden registers, branch prediction circuits and specific details concerning the ALU (arithmetic logic unit). The implementation of a processor is also known as (Figure ).