Design of Power Management Integrated Circuits E-Book

Bernhard Wicht

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: Wiley - IEEE
• Sprache: Englisch

Seitenzahl: 929

Veröffentlichungsjahr: 2024

Beschreibung

Design of Power Management Integrated Circuits

Comprehensive resource on power management ICs affording new levels of functionality and applications with cost reduction in various fields

Design of Power Management Integrated Circuits is a comprehensive reference for power management IC design, covering the circuit design of main power management circuits like linear and switched-mode voltage regulators, along with sub-circuits such as power switches, gate drivers and their supply, level shifters, the error amplifier, current sensing, and control loop design. Circuits for protection and diagnostics, as well as aspects of the physical design like lateral and vertical power delivery, pin-out, floor planning, grounding/supply guidelines, and packaging, are also addressed. A full chapter is dedicated to the design of integrated passives. The text illustrates the application of power management integrated circuits (PMIC) to growth areas like computing, the Internet of Things, mobility, and renewable energy.

Includes numerous real-world examples, case studies, and exercises illustrating key design concepts and techniques.

Offering a unique insight into this rapidly evolving technology through the author’s experience developing PMICs in both the industrial and academic environment, Design of Power Management Integrated Circuits includes information on:

• Capacitive, inductive and hybrid DC-DC converters and their essential circuit blocks, covering error amplifiers, comparators, and ramp generators
• Sensing, protection, and diagnostics, covering thermal protection, inductive loads and clamping structures, under-voltage, reference and power-on reset generation
• Integrated MOS, MOM and MIM capacitors, integrated inductors
• Control loop design and PWM generation ensuring stability and fast transient response; subharmonic oscillations in current mode control (analysis and circuit design for slope compensation)
• DC behavior and DC-related circuit design, covering power efficiency, line and load regulation, error amplifier, dropout, and power transistor sizing
• Commonly used level shifters (including sizing rules) and cascaded (tapered) driver sizing and optimization guidelines
• Optimizing the physical design considering packaging, floor planning, EMI, pinout, PCB design and thermal design

Design of Power Management Integrated Circuits is an essential resource on the subject for circuit designers/IC designers, system engineers, and application engineers, along with advanced undergraduate students and graduate students in related programs of study.

Leseprobe

Table of Contents

Cover

Table of Contents

Title Page

Copyright

Dedication

Preface

1 Introduction

1.1 What Is a Power Management IC and What Are the Key Requirements?

1.2 The Smartphone as a Typical Example

1.3 Fundamental Concepts

1.4 Power Management Systems

1.5 Applications

1.6 IC Supply Voltages

1.7 Power Delivery

1.8 Technology, Components, and Co-integration

1.9 A Look at the Market

References

2 The Power Stage

2.1 Introduction

2.2 On-Resistance and Dropout

2.3 Parasitic Capacitances

2.4 The Body Diode

2.5 Switching Behavior

2.6 Gate Current and Gate Charge

2.7 Losses

2.8 Dead Time Generation

2.9 Soft-Switching

2.10 Switch Stacking

2.11 Back-to-Back Configuration

References

3 Semiconductor Devices

3.1 Discrete Power Transistors

3.2 Power Transistors in Integrated Circuits

3.3 Parasitic Effects

3.4 Safe Operating Area (SOA)

3.5 Integrated Diodes

References

4 Integrated Passives

4.1 Capacitors

4.2 Inductors

References

5 Gate Drivers and Level Shifters

5.1 Introduction

5.2 Gate Driver Configurations

5.3 Driver Circuits

5.4 DC Characteristics

5.5 Driving Strength

5.6 The CMOS Inverter as a Gate Driver

5.7 Gate Driver with a Single-Stage Inverter

5.8 Cascaded Gate Drivers

5.9 External Gate Resistor

5.10 d/d Triggered Turn-On

5.11 Bootstrap Gate Supply

5.12 Level Shifters

5.13 Common-Mode Transient Immunity

References

6 Protection and Sensing

6.1 Overvoltage Protection

6.2 Overvoltage Protection for Inductive Loads

6.3 Temperature Sensing and Thermal Protection

6.4 Bandgap Voltage and Current Reference

6.5 Short Circuits and Open Load

6.6 Current Sensing

6.7 Zero-Crossing Detection

6.8 Under-Voltage Lockout

6.9 Power-on Reset

References

7 Linear Voltage Regulators

7.1 Fundamental Circuit and Control Concept

7.2 Dropout Voltage

7.3 DC Parameters

7.4 The Error Amplifier

7.5 Frequency Behavior and Stability

7.6 Transient Behavior

7.7 Noise in Linear Regulators

7.8 Power Supply Rejection

7.9 Soft-Start

7.10 Capacitor-Less LDO

7.11 Flipped Voltage Follower LDO

7.12 The Shunt Regulator

7.13 Digital LDOs

References

8 Charge Pumps

8.1 Introduction

8.2 Analysis of the Fundamental Charge Pump

8.3 Influence of Parasitics

8.4 Charge Pump Implementation

8.5 Power Efficiency

8.6 Cascading of Pumping Stages

8.7 Other Charge Pump Configurations

8.8 Current-Source Charge Pumps

8.9 Charge Pumps Suitable as a Floating Gate Supply

8.10 Closed-loop Control

References

9 Capacitive DC–DC Converters

9.1 Introduction

9.2 Realizable Ratios

9.3 Switched-Capacitor Topologies

9.4 Gate Drive Techniques

9.5 Charge Flow Analysis

9.6 Output Voltage Ripple

9.7 Topology Selection

9.8 Capacitor and Switch Sizing

9.9 Loss Analysis and Efficiency

9.10 Multi-phase SC Converters

9.11 Multi-ratio SC Converters

9.12 Multi-phase Interleaving

9.13 Control Methods

References

10 Inductive DC–DC Converters

10.1 The Fundamental Buck Converter

10.2 Losses and Power Conversion Efficiency

10.3 Closing the Loop

10.4 Hysteretic Control

10.5 Voltage-Mode Control (VMC)

10.6 Current-Mode Control (CMC)

10.7 Constant On-Time Control

10.8 Frequency Compensation

10.9 Discontinuous Conduction Mode (DCM)

10.10 The Boost Converter

10.11 The Buck-Boost Converter

10.12 The Flyback Converter

10.13 Rectifier Circuits

10.14 Multi-phase Converters

10.15 Single-Inductor Multiple-Output Converters (SIMO)

References

11 Hybrid DC–DC Converters

11.1 Hybridization of Capacitive and Inductive Concepts

11.2 The Benefit of Soft-Charging

11.3 Basic Resonant SC Converter Stages

11.4 Frequency Generation and Tuning

11.5 Equivalent Output Resistance

11.6 Control of Hybrid Converters

11.7 From SC to Hybrid Converters

11.8 Multi-phase Converters

11.9 Multi-Ratio Converters

11.10 The Three-Level Buck Converter

11.11 The Flying-Capacitor Multi-Level Converter (FCML)

11.12 The Double Step-Down (DSD) Converter

11.13 Inductor-First Topologies

References

12 Physical Implementation

12.1 Layout Floor Planning

12.2 Packaging

12.3 Electromagnetic Interference (EMI)

12.4 Interconnections

12.5 Pinout

12.6 IC-Level Wiring

12.7 PCB Layout Design

12.8 Power Delivery

12.9 Thermal Design

References

Index

End User License Agreement

List of Tables

Chapter 2

Table 2.1 Typical gate charge values.

Table 2.2 Parameters of Example 2.5.

Table 2.3 Losses of Example 2.5.

Table 2.4 Losses of Example 2.7.

Table 2.5 Losses of Example 2.8.

Chapter 3

Table 3.1 Key parameters of discrete 100 V power transistors.

Table 3.2 Key parameters of discrete 600 V power transistors.

Table 3.3 Key parameters of discrete 1200 V power transistors.

Table 3.4 Typical data sheet for an integrated LDMOS.

Chapter 4

Table 4.1 Key parameters of integrated capacitors.

Table 4.2 Coefficients for the compact expression in Eqn. (4.13).

Chapter 5

Table 5.1 Gate driver design parameters. Values for external (discrete) powe...

Table 5.2 Driver sizing for and (Example 5.12).

Table 5.3 Overview of typical transition slopes of the switching node for va...

Table 5.4 Comparison of three classes of level shifters, resistor-based leve...

Chapter 8

Table 8.1 Analysis of the charge pump efficiency in Example 8.4. Except for

Chapter 9

Table 9.1 Realizable ideal step-down voltage conversion ratios for flying ...

Table 9.2 All realizable ideal voltage conversion ratios for flying capa...

Table 9.3 Charge flow vectors of common 3:1 SC topologies (referred to Fig. ...

Table 9.4 Parameters of common 3:1 SC topologies.

Chapter 11

Table 11.1 Hybrid converters combine the advantages and solve the drawbacks ...

Table 11.2 Voltage-change analysis of common 3:1 hybrid SC topologies (refer...

Table 11.3 Switching sequences of the 4L-buck converter.

Chapter 12

Table 12.1 Bond wire maximum current and resistance [1, 2].

Table 12.2 Parameters of standard IC packages with an exposed pad [4–9].

List of Illustrations

Chapter 1

Figure 1.1 The role of power management: placed between the energy source ...

Figure 1.2 a) The mobile phone in the early 1990s, b) the smartphone today...

Figure 1.3 Conversion of 12 to 2 V by a simple resistor. This is the conce...

Figure 1.4 Voltage conversion using switches and an inductor achieving h...

Figure 1.5 Voltage conversion using capacitors: a) the fundamental switche...

Figure 1.6 A hybrid converter formed by adding an inductor to an SC conv...

Figure 1.7 Point-of-load (PoL) power management systems: a) handheld devic...

Figure 1.8 The system voltages in various applications define the input vo...

Figure 1.9 Miniaturized DC–DC converters for wearables: a) a fully integra...

Figure 1.10 A 5G base station with the transmit and receive path (, ). T...

Figure 1.11 The automotive 12 V/48 V/HV boardnet.

Figure 1.12 Data center 48 V power distribution architecture.

Figure 1.13 IC supply voltages versus technology node and year of introduc...

Figure 1.14 Power delivery in a desktop PC: a) for a conventional CPU and ...

Figure 1.15 Dynamic voltage and frequency scaling: processor power dissipa...

Figure 1.16 Component set of a typical BCD technology.

Figure 1.17 Power transistor technologies: output power versus switching f...

Figure 1.18 Size impact of passive components in DC–DC converters: a) the ...

Figure 1.19 A step-down converter consisting of an IC with a package-integ...

Figure 1.20 Market for PMICs by a) segment and b) by type [21]. The market...

Chapter 2

Figure 2.1 Power stage configurations: (a) low-side switch, (b) high-side ...

Figure 2.2 a) Definition of the dropout as the minimum source–drain voltag...

Figure 2.3 Parasitic capacitances in a power transistor.

Figure 2.4 Transistor capacitances versus drain–source voltage for a dis...

Figure 2.5 Body diodes in half-bridge configurations. The body diode appea...

Figure 2.6 a) Half-bridge with an inductive load indicating the body diode...

Figure 2.7 Turn-on switching behavior: a) resistive load; b) inductive loa...

Figure 2.8 Turn-off switching behavior: a) resistive load; b) inductive lo...

Figure 2.9 Turn-on switching behavior for an inductive load including reve...

Figure 2.10 Power stage with parasitics.

Figure 2.11 Turn-off switching behavior including power loop parasitics fo...

Figure 2.12 Switching behavior of a half-bridge with an inductive load: a)...

Figure 2.13 a) Switching trajectories for b) resistive switching, c) ideal...

Figure 2.14 Turn-on transition with gate currents for a hard-switching and...

Figure 2.15 a) Test and simulation setup for gate charge extraction; b) ga...

Figure 2.16 Conduction and switching losses at a power transistor for an i...

Figure 2.17 Current ripple increases the conduction losses in a power tr...

Figure 2.18 Loss energy versus on-resistance. The plot shows the loss co...

Figure 2.19 Gate signals with dead time. The active device turns off befor...

Figure 2.20 Circuits for fixed dead time generation.

Figure 2.21 Adaptive dead time control.

Figure 2.22 Predictive dead time control: a) block diagram; b) low-side/hi...

Figure 2.23 Switching losses of a) a hard-switching setup are eliminated b...

Figure 2.24 Switch stacking of a) two and b) three low-voltage transistors...

Figure 2.25 Back-to-back configuration.

Chapter 3

Figure 3.1 Discrete and integrated power transistors: a) discrete power tr...

Figure 3.2 Cross section of power transistors and electrical field strengt...

Figure 3.3 The IGBT: a) Cross section of a conventional IGBT; b) its equiv...

Figure 3.4 Cross section of a GaN power transistor.

Figure 3.5 Cross section of a drain-extended MOSFET (DEMOS): a) n-type and...

Figure 3.6 Lateral DMOS transistor cross section.

Figure 3.7 DMOS transistor equivalent circuit.

Figure 3.8 DMOS transistor layout.

Figure 3.9 Power transistor in an SOI technology, isolated by deep-trench ...

Figure 3.10 MOS transistor with parasitic bipolar NPN transistor in case o...

Figure 3.11 Guard ring characteristics.

Figure 3.12 Guard ring types: a) guard ring with high efficiency, b) guard...

Figure 3.13 DMOS transistor with parasitic bipolar PNP transistor. The equ...

Figure 3.14 Cross section with parasitic PNP and NPN structures that can c...

Figure 3.15 Capacitive coupling inside isolation for a) a capacitive level...

Figure 3.16 Parasitic substrate coupling due to parasitic capacitances of ...

Figure 3.17 Safe operating area (SOA): a) SOA graph; b) power transistor e...

Figure 3.18 A PN diode formed by a shallow p-area inside a deep n-well. Th...

Figure 3.19 a) A PN diode formed by a shallow n-area inside an isolated p-...

Figure 3.20 DMOS transistor forming a power diode.

Figure 3.21 Integrated Zener diodes: a) cross section; b) symbol; c) colle...

Chapter 4

Figure 4.1 MOS capacitor: a) Symbol with parasitic top- and bottom-plate c...

Figure 4.2 MOM capacitor: a) Typical interdigitated multi-layer structure;...

Figure 4.3 MIM capacitor: a) Capacitor cross-section with p-well and deep ...

Figure 4.4 a) Ampere's law applied to a cylindrical wire; b) solenoid indu...

Figure 4.5 Bondwire inductors: a) Square shape, , four turns, outer segme...

Figure 4.6 Bondwire inductor in triangular and square shape: a) inductance...

Figure 4.7 Package layer inductor. a) The bottom of an Intel

®

4th gen...

Figure 4.8 On-chip spiral inductor in the square, hexagonal, and octagonal...

Figure 4.9 Equivalent circuit of a planar metal-layer inductor.

Figure 4.10 Square spiral inductor.Top view and cross-section showing ...

Figure 4.11 Square planar coil with dimensions and mutual inductances ac...

Figure 4.12 a) Inductance and b) series DC resistance versus winding w...

Figure 4.13 Inductors with magnetic core: a) Inductance and quality factor...

Chapter 5

Figure 5.1 Gate driver: a) circuit principle; b) using a CMOS inverter.

Figure 5.2 Gate driver block diagram.

Figure 5.3 Gate driver configurations: a) and b) with p-channel high-side ...

Figure 5.4 Low-side gate driver with a level shifter.

Figure 5.5 High-side gate driver with a level shifter.

Figure 5.6 Gate driver circuits: a) CMOS inverter, b) two NMOS transistors...

Figure 5.7 CMOS inverter: a) Symbol; b) circuit; c) output current versus ...

Figure 5.8 Gate driver DC characteristics with the two basic driver parame...

Figure 5.9 Influence of the driver strength: a) setup; b) DC and c) transi...

Figure 5.10 Inverter stage a) with parasitic capacitances that are merged ...

Figure 5.11 Rise-fall time and average propagation delay .

Figure 5.12 Short-circuit losses: a) short-circuit current versus rise-fal...

Figure 5.13 Dynamic losses: a) loss scenario with ; equivalent circuits d...

Figure 5.14 Single stage driver transient behavior: a) setup; b) voltage, ...

Figure 5.15 Propagation delay of a single-stage gate driver versus scali...

Figure 5.16 Combined driver and switching loss of a single-stage gate dr...

Figure 5.17 Switching transition for a) a single-stage driver according to...

Figure 5.18 Cascaded gate driver.

Figure 5.19 Switching transitions for a) two, b) four, and c) six driver s...

Figure 5.20 Optimization for speed: a) ratio as a function of the scalin...

Figure 5.21 Combined driver and switching loss of a cascaded gate driver...

Figure 5.22 Splitting up the gate driver into separate branches.

Figure 5.23 Gate driver with a break-before-make circuit.

Figure 5.24 Gate driver with asymmetrical device sizing.

Figure 5.25 Influence of an external gate resistor : a) gate current vers...

Figure 5.26 d/d triggered turn-on: a) general case; b) at start-up.

Figure 5.27 a) Bootstrap gate supply; b) with currents and charge supplied...

Figure 5.28 Bootstrap supply with a) recharge path from , b) pull-down tr...

Figure 5.29 Active bootstrapping: a) circuit; b) timing diagram.

Figure 5.30 Resistor-based level shifters: a) basic configuration; b) puls...

Figure 5.31 Level shifter with diode-connected pull-up transistors (M3, M5...

Figure 5.32 Cross-coupled level shifter: a) general circuit; b) high-volta...

Figure 5.33 Cross-coupled level shifter: equivalent circuit of Fig. 5.32a)...

Figure 5.34 Cross-coupled level shifter: equivalent circuit of Fig. 5.32b)...

Figure 5.35 Cross-coupled level shifter with full logic level output swing...

Figure 5.36 Cross-coupled level shifter with full logic level output swing...

Figure 5.37 Capacitive level shifter.

Figure 5.38 a) Open-loop circuit model of the capacitive level shifter wit...

Figure 5.39 Transient behavior of the capacitive level shifter for , ,

Figure 5.40 Capacitive level shifter with dedicated pull-up resistors an...

Figure 5.41 a) Resistor-based and b) cross-coupled level-down shifters; c)...

Figure 5.42 Level shifter with diode-connected pull-up transistors (M3, M5...

Figure 5.43 A capacitive level shifter with blanking and protection for co...

Chapter 6

Figure 6.1 Power stage block diagram with protection.

Figure 6.2 Overvoltage protection of a low-voltage transistor (LV) by a hi...

Figure 6.3 Active Zener diode.

Figure 6.4 Overvoltage protection for inductive loads: a) low-side switch;...

Figure 6.5 Drain–gate clamp example for a high-side power stage.

Figure 6.6 Thermal shutdown circuit based on an IPTAT generation.

Figure 6.7 Temperature behavior of and in the thermal shutdown circuit...

Figure 6.8 a) Bandgap voltage and current reference including start-up cir...

Figure 6.9 A bandgap voltage reference that can be trimmed and maintains a...

Figure 6.10 Short circuit to ground (SCG) and open load (OL) detection.

Figure 6.11 Typical current sensing locations.

Figure 6.12 Replica current sensing with the sense transistor MS implement...

Figure 6.13 Replica current sensing: a) schematic; b) block diagram.

Figure 6.14 Replica current sensing: a) practical implementation; b) DC er...

Figure 6.15 Replica current sensing with compensation.

Figure 6.16 Replica current sensing at the low-side transistor for an indu...

Figure 6.17 Shunt current sensing: typical shunt resistor locations at a) ...

Figure 6.18 DCR current sensing: a) basic setup with the inductor modeled ...

Figure 6.19 Current limiting: a) setup with power supply and load; b) cons...

Figure 6.20 A linear voltage regulator with a current limit based on repli...

Figure 6.21 A linear voltage regulator (LDO) with foldback current limit: ...

Figure 6.22 Zero-crossing detection circuits: a) R-C voltage divider at th...

Figure 6.23 a) Under-voltage lockout circuit; b) transfer behavior with hy...

Figure 6.24 Power-on reset (POR): a) transient behavior in comparison to u...

Figure 6.25 Simulated transient behavior of the power-on reset circuit for...

Chapter 7

Figure 7.1 a) Fundamental circuit of a linear voltage regulator; b) block ...

Figure 7.2 Fundamental LDO with a) PMOS and b) NMOS power transistor; c) d...

Figure 7.3 Relationship between input and output voltage of the LDO, dropo...

Figure 7.4 Efficiency of the linear voltage regulator for , and two dif...

Figure 7.5 Small-signal equivalent circuits to derive the load regulation ...

Figure 7.6 Small-signal equivalent circuits to derive the line regulation ...

Figure 7.7 The symmetrical amplifier is used as a typical error amplifier....

Figure 7.8 Equivalent circuit for the frequency behavior of the PMOS-type ...

Figure 7.9 Bode plot of the LDO loop gain.

Figure 7.10 Bode plots of the loop gain with options for improving the dyn...

Figure 7.11 Inserting a buffer: a) concept indicating the influence on the...

Figure 7.12 Equivalent circuit for the frequency behavior of the NMOS-type...

Figure 7.13 Adding a buffer stage in the NMOS-type LDO allows connecting t...

Figure 7.14 LDO transient behavior for a positive and a negative load step...

Figure 7.15 LDO with a secondary fast-transient loop to enhance the transi...

Figure 7.16 Transient enhancement techniques: a) adaptive biasing: the bia...

Figure 7.17 LDO with equivalent noise sources.

Figure 7.18 -transition of the LDO without and with soft-start.

Figure 7.19 Soft-start: a) error amplifier with soft-start function; b) nA...

Figure 7.20 Capacitor-less LDO: a) multi-stage feedback with Miller compen...

Figure 7.21 LDO with flipped voltage follower (FVF): a) concept; b) with i...

Figure 7.22 a) Basic shunt regulator circuit and b) modified version with

Figure 7.23 The shunt regulator as a start-up supply.

Figure 7.24 Block diagram of a digital linear regulator (DLDO).

Figure 7.25 DLDO techniques: a) adaptive clocking; b) feedforward power su...

Chapter 8

Figure 8.1 Voltage doubler charge pump: a) Concept and equivalent circuit ...

Figure 8.2 Start-up transients of the charge pump output voltage for , ,...

Figure 8.3 Output resistance of the charge pump.

Figure 8.4 Fundamental charge pump with parasitic capacitance and switch...

Figure 8.5 Charge pump of Fig. 8.1e) with the switches implemented by diod...

Figure 8.6 Charge pumps with transistor switches: Replacing diode D1 in Fi...

Figure 8.7 A dual-phase charge pump.

Figure 8.8 a) Layout cross-section of the inverters in Fig. 8.7 with the b...

Figure 8.9 Major losses in a Dickson-type charge pump.

Figure 8.10 Cascading of charge pump stages. The node voltages scale up to...

Figure 8.11 a) An inverting charge pump; b) transient behavior at start-up...

Figure 8.12 Charge pump with two input voltages ( and ) and tied to ....

Figure 8.13 Current-source charge pump: Limited inrush current reduces str...

Figure 8.14 Charge pump to provide a floating gate supply referred to :...

Figure 8.15 High-voltage floating gate supplies: a) Self-boosted charge pu...

Figure 8.16 Charge pump with closed-loop control. Ways to control the char...

Chapter 9

Figure 9.1 a) Basic 2:1 SC converter. The equivalent circuits during phase...

Figure 9.2 SC converter model with the ideal voltage conversion ratio , t...

Figure 9.3 Series–parallel converters with two flying capacitors and equiv...

Figure 9.4 3:1 SC topologies: a) series–parallel; b) Dickson; c) ladder; d...

Figure 9.5 Gate drive techniques for SC converters: a) direct gate control...

Figure 9.6 Charge flow analysis: a) the 2:1 SC converter of Fig. 9.1 with ...

Figure 9.7 Charge flow analysis of common 3:1 topologies: a) series–parall...

Figure 9.8 Equivalent output resistance of an SC converter with its asym...

Figure 9.9 SC converter equivalent circuit in any phase .

Figure 9.10 Equivalent output resistance for the Dickson and ladder topolo...

Figure 9.11 a) 2:1 SC converter with parasitic top-plate and bottom-plate ...

Figure 9.12 Total power loss and loss components in a 3:1 Dickson SC conve...

Figure 9.13 Power efficiency versus load current of the 3:1 Dickson SC con...

Figure 9.14 A three-phase 4:1 SC converter based on a) the Fibonacci topol...

Figure 9.15 A three-phase 4:1 SC converter based on a) the Fibonacci topol...

Figure 9.16 General approach to develop multi-phase SC converters: capacit...

Figure 9.17 Theoretical power efficiency of an SC converter with flying ...

Figure 9.18 A multi-ratio SC converter with two flying capacitors supports...

Figure 9.19 The folding Dickson topology in different conversion ratios: a...

Figure 9.20 A 4-bit successive approximation SC converter (SAR SC converte...

Figure 9.21 Recursive switched-capacitor converter: by reconfiguring multi...

Figure 9.22 Cascading options for 2:1 SC stages: a) with an intermediate b...

Figure 9.23 Capacitor sizing: to allow for recursive reconfiguration with ...

Figure 9.24 Die photo of a multi-ratio SC converter.The chip contains ...

Figure 9.25 Capacitor allocation for a 4-bit RSC converter proportional to...

Figure 9.26 Recursive implementation: a) block diagram with 3-bit resoluti...

Figure 9.27 Multiphase interleaving: a) output voltage ripple for a sing...

Figure 9.28 Scaling of the flying capacitors and switches for 4-phase inte...

Figure 9.29 SC converter with a ring-oscillator-based control loop.

Chapter 10

Figure 10.1 a) Basic switched-mode DC–DC converter with b) waveforms of th...

Figure 10.2 Waveforms of the inductor and capacitor currents and the outpu...

Figure 10.3 a) DC–DC converter with synchronous rectification: ML is contr...

Figure 10.4 a) Losses in a DC–DC converter and b) power conversion efficie...

Figure 10.5 The fundamental step-down DC–DC converter with closed-loop con...

Figure 10.6 The DC–DC converter with hysteretic control.

Figure 10.7 Voltage-mode control.

Figure 10.8 Pulse-width modulation in voltage-mode control: a) direct duty...

Figure 10.9 Sawtooth generation using a) a capacitor, b) an active integra...

Figure 10.10 Sawtooth generation: a) impact of finite settling; b) time-in...

Figure 10.11 Sawtooth generator with comparator and logic delay compensati...

Figure 10.12 a) Basic error amplifier, and b) its transfer function.

Figure 10.13 Comparator with hysteresis and positive feedback.

Figure 10.14 Bode plot of the control-to-output transfer function of the...

Figure 10.15 Current-mode control consists of two control loops, an inner ...

Figure 10.16 Current-mode control: Pulse-width modulation is achieved by c...

Figure 10.17 Current-mode control: Block diagram.

Figure 10.18 Current-mode control: Simplified block diagram with the inner...

Figure 10.19 Current-mode control: Blanking of the initial spike.

Figure 10.20 Subharmonic oscillations in case of an initial perturbation

Figure 10.21 Slope compensation.

Figure 10.22 Measured transient behavior a) with and b) without slope comp...

Figure 10.23 Options for slope compensation: a) is subtracted from the e...

Figure 10.24 Slope compensation circuits: a) Concept according to Fig. 10....

Figure 10.25 Constant on-time current-mode control: a) circuit implementat...

Figure 10.26 Constant on-time control: a) and for two different values...

Figure 10.27 Compensator circuits: (a) type I, (b) type II, and (c) type I...

Figure 10.28 Bode plot of the plant and controller transfer functions an...

Figure 10.29 Capacitance multiplier circuits: a) voltage mode (Miller effe...

Figure 10.30 a) Waveforms in CCM for small load current: the inductor curr...

Figure 10.31 a) Inductor current for CCM (top) and DCM (middle) in PWM ope...

Figure 10.32 By adding PFM control, the current-mode controlled DC–DC conv...

Figure 10.33 Measured waveforms of a DC–DC buck converter in PFM mode (fro...

Figure 10.34 a) Basic boost converter with b) waveforms of the inductor cu...

Figure 10.35 Boost converter with PWM switch model: a) large-signal model;...

Figure 10.36 Voltage conversion ratio of the boost converter as a functi...

Figure 10.37 a) The inverting buck-boost converter with b) typical wavefor...

Figure 10.38 Absolute value of the voltage conversion ratio of the inv...

Figure 10.39 The four-switch buck-boost converter: a) topology; b) control...

Figure 10.40 The flyback converter: The transformer provides isolated DC–D...

Figure 10.41 Transient waveforms of a) the passive (PCF) and b) the active...

Figure 10.42 Full-wave rectifier: a) schematic; b) waveforms; c) rectifier...

Figure 10.43 Low-voltage rectifier circuits: a) CMOS full-wave rectifier f...

Figure 10.44 A multiphase buck converter in voltage-mode control: power ...

Figure 10.45 Phase currents and output current for a four-phase buck c...

Figure 10.46 Current ripple as a function of the DC–DC converter's duty cy...

Figure 10.47 Conversion efficiency of a multiphase DC–DC converter with ...

Figure 10.48 Influence of phase duty cycle mismatch on the average phase...

Figure 10.49 A multi-phase DC–DC converter with phase balancing: DCR sensi...

Figure 10.50 Single-Inductor Multiple Output (SIMO) converters: a) buck; b...

Figure 10.51 SIMO converter with a single energizing cycle per switching p...

Figure 10.52 A single-inductor multiple output (SIMO) converter operated i...

Chapter 11

Figure 11.1 Inductor current at different switching frequency : At the ...

Figure 11.2 “Hybridization” can be applied to a) an SC converter by b) add...

Figure 11.3 a) Charge redistribution between two capacitors; b) hard-charg...

Figure 11.4 a) Charge transfer between two capacitors via an inductor; b) ...

Figure 11.5 Fundamental 2:1 converter stages: a) capacitive (SC); b) direc...

Figure 11.6 Frequency generation: a) relaxation ocscillator.b) frequen...

Figure 11.7 a) Equivalent output resistance ; b) hybrid converter equival...

Figure 11.8 Inductor current during dynamic off-time modulation (DOTM)....

Figure 11.9 Equivalent output resistance versus switching frequency of...

Figure 11.10 Multimode operation at constant load current including DOTM...

Figure 11.11 a) Implementation of DOTM control; b) timing diagram.

Figure 11.12 Switch conductance regulation (SwCR): a) inductor current f...

Figure 11.13 a) A hybrid 3:1 converter based on the series-parallel SC top...

Figure 11.14 Analyzing the voltage changes across each flying capacitor of...

Figure 11.15 Soft-charging analysis of the hybrid 4:1 Dickson converter: a...

Figure 11.16 The hybrid 3:1 Dickson converter with split-phase control: Ad...

Figure 11.17 a) Two-phase hybrid converter and b) corresponding die photo ...

Figure 11.18 a) The 3L-buck converter in comparison to b) the 2L-buck conv...

Figure 11.19 Current ripple of the fundamental 2L-buck converter and the 3...

Figure 11.20 a) Voltage-mode PWM control of the 3L-buck converter and b) s...

Figure 11.21 a) Flying capacitor balancing added to the 3L-buck converter ...

Figure 11.22 Implementation example of a 3L-buck converter with two ways o...

Figure 11.23 The 4L-buck converter and its eight switching states.

Figure 11.24 a) The double step-down converter; b) the two-phase inductive...

Figure 11.25 The three switching states of the double step-down converter:...

Figure 11.26 a) Conventional inductive buck converter and b) modification ...

Figure 11.27 A bidirectional power delivery, voltage-regulating USB cable ...

Chapter 12

Figure 12.1 Floor plan of a power management IC with the three main areas ...

Figure 12.2 IC packages: a) SOIC, b) SSOP, c) QFP, d) QFN (shown approxima...

Figure 12.3 A lead frame with an IC attached in the center.

Figure 12.4 Cross-section of an IC package with an exposed pad.

Figure 12.5 Electrical model of an IC package: a) lumped T-equivalent circ...

Figure 12.6 System-in-package with a power management IC, active devices, ...

Figure 12.7 Electromagnetic interference (EMI): a) PWM waveform in the tim...

Figure 12.8 a) High-d/d loops and high-d/d nodes in a buck converter; ...

Figure 12.9 Placing two input capacitors on opposite sides between and g...

Figure 12.10 IC pinout examples for buck converters with external power sw...

Figure 12.11 An ultra-low-noise DC–DC converter IC with integrated power s...

Figure 12.12 a) Capacitive coupling between a noisy line clock line (CLK) ...

Figure 12.13 Grounding: a) Example with separated analog, digital, and pow...

Figure 12.14 Different options of supply connections: a) The digital suppl...

Figure 12.15 Top-layer layout of a 4-layer PCB that implements the DC–DC c...

Figure 12.16 Power delivery: a) Lateral power delivery; b) vertical power ...

Figure 12.17 Equivalent circuit of a typical power distribution network (P...

Figure 12.18 a) The impedance of the power delivery network (PDN) over fre...

Figure 12.19 Equivalent circuit of a typical power distribution network (P...

Figure 12.20 Electrical equivalent circuit involving the junction-to-ambie...

Figure 12.21 Temperature distribution from a thermal simulation of a power...

Guide

Cover

Table of Contents

Title Page

Copyright

Dedication

Preface

Begin Reading

Index

End User License Agreement

Pages

iii

iv

v

xvii

xviii

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423_

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

449

450

451

452

453

454

455

456

457

458

Design of Power Management Integrated Circuits

Bernhard Wicht

Leibniz University Hannover, Germany

This edition first published 2024 © 2024 John Wiley & Sons Ltd.

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by law. Advice on how to obtain permission to reuse material from this title is available at http://www.wiley.com/go/permissions.

The right of Bernhard Wicht to be identified as the author of the editorial material in this work has been asserted in accordance with law.

Registered OfficesJohn Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, USA John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, UK

For details of our global editorial offices, customer services, and more information about Wiley products visit us at www.wiley.com.

Wiley also publishes its books in a variety of electronic formats and by print-on-demand. Some content that appears in standard print versions of this book may not be available in other formats.

Trademarks: Wiley and the Wiley logo are trademarks or registered trademarks of John Wiley & Sons, Inc. and/or its affiliates in the United States and other countries and may not be used without written permission. All other trademarks are the property of their respective owners. John Wiley & Sons, Inc. is not associated with any product or vendor mentioned in this book.

Limit of Liability/Disclaimer of WarrantyWhile the publisher and authors have used their best efforts in preparing this work, they make no representations or warranties with respect to the accuracy or completeness of the contents of this work and specifically disclaim all warranties, including without limitation any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives, written sales materials or promotional statements for this work. This work is sold with the understanding that the publisher is not engaged in rendering professional services. The advice and strategies contained herein may not be suitable for your situation. You should consult with a specialist where appropriate. The fact that an organization, website, or product is referred to in this work as a citation and/or potential source of further information does not mean that the publisher and authors endorse the information or services the organization, website, or product may provide or recommendations it may make. Further, readers should be aware that websites listed in this work may have changed or disappeared between when this work was written and when it is read. Neither the publisher nor authors shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages.

Library of Congress Cataloging-in-Publication Data applied for:

Hardback ISBN: 9781119123064

Cover Design: Wiley Cover Image: © fotograzia/Getty Images

To my beloved family, Sabine, Luise, Friederike, Konstantin, and to my parents Siegrid and Eberhard.

Preface

In the March 2020 issue of the IEEE Solid-State Circuits Magazine, IEEE fellow Marcel Pelgrom writes in one of his excellent and inspiring Associate Editor's View columns entitled Standing on Shoulders about the timeless need for textbooks: “…where is the next disruptive view of our field, something that is desperately needed after this dazzling journey from 10-micron devices to nanometer electronics for quantum computing?” This book is my take on the field of power management.

The book delves into the fascinating world of power management IC design. This field has seen rapid growth in recent years, with the increasing demand for energy-efficient electronics, in particular, portable battery-operated devices. Power management integrated circuits are used for highly efficient power supplies and controlling power switches. It is incredible how these technologies have gained tremendous importance in making electronic solutions for global growth areas such as renewable energies, transportation, and communications more compact, energy-efficient, and reliable. Future machine learning and AI applications will only be possible with intelligent power management to supply complex processors and sensors.

I got into power management when I joined the industry in the early 2000s and went along a steep learning curve on all kinds of power management systems and design aspects. When I became a professor in 2010, I created a new course dedicated to power management IC design. However, no comprehensive textbook was available, and I had to rely on scientific papers and application notes.

A few years later, the idea of this book came up. Since then, I have been fascinated and challenged by the fast pace of progress and innovation in power management. The book provides a complete resource for those interested in power management IC design, covering basic concepts, advanced topics, and recent innovations in this rapidly evolving field. It is intended for students, educators, professors, and new and experienced engineers who want to learn about power management IC design, providing valuable insight and practical guidance for designing power management circuits and systems. Each chapter is organized to make it easy to find specific sub-topics, with numerous real-world examples illustrating key design concepts and techniques.

When I teach an entire course on power management IC design at a Master's or advanced Bachelor's level, I reduce the content and follow this outline: (1) Introduction (applications, challenges, physical implementation); (2) Linear Voltage Regulators; (3) Charge Pumps and Capacitive DC–DC Converters; (4) Power Transistors; (5) Gate Drivers; (6) Protection and Sensing; (7) Inductive DC–DC Converters; (8) Hybrid Converters. I also offer a design lab based on Spice simulation accompanying the lecture. Starting the class with the linear regulator right after the introduction allows the lab to begin early in the semester. I turned a lot of lab assignments and exercises into the many examples in this book (to my respected future students: I hope I'm not giving too much away.).

In his column, Marcel Pelgrom also writes about the burden of writing textbooks. And indeed, this book is the result of an investment of uncountable hours over several years. Writing a book also means that there will be missing content, on purpose but also by mistake. My fellow readers: Despite careful review, there will be mistakes, and I apologize in advance. Any feedback is highly appreciated. Please get in touch.

This book would not be in your hands without careful review, invaluable feedback, and encouragement by many people. I want to thank my former and recent Ph.D. students, in particular, Peter Renz (who read through the entire draft) and Tobias Funk, Saurabh Kale, Maik Kaufmann, Tim Kuhlmann, Jens Otten, Christoph Rindfleisch, and Jürgen Wittmann. Thanks to Markus Henriksen for his feedback on switched-capacitor (SC) and hybrid converters. Hartmut Grabinski ensured that Maxwell's equations were correctly applied to interconnections and printed circuit board (PCB) layout. Detlev Habicht and Niklas Deneke supported in capturing photographs for the book. I am grateful to the team at Wiley, in particular, to Sandra Grayson, Juliet Booker, Kavipriya Ramachandran, and Jeevaghan Devapal for their excellent support and patience. I wish to thank many more people.

Writing such a book is impossible without the support of my family. I want to thank my parents, Siegrid and Eberhard, who have supported my fascination with microelectronic circuits since I was nine. Thanks go to my children, who became real fans of my book project, even though they often had to take a back seat, especially when finalizing the manuscript over the last 1–2 years. I am indebted to my wife, Sabine. This book would not have been possible without her love and understanding.

Enjoy the exciting journey of exploring the design of power management integrated circuits!

August 2023, Gehrden

Bernhard Wicht

1Introduction

Power management integrated circuits (PMICs) are essential in today's electronic devices. They manage power delivery and consumption, provide efficient power supplies, and drive power switches that control actuators and motors, as illustrated in Fig. 1.1. PMICs can be integrated into complex integrated circuits (ICs) or implemented as dedicated ICs. In this book, the term PMIC will refer to any type of power integrated circuit.

The importance of PMICs has grown significantly in recent years, driving innovation and progress in various industries, from consumer electronics to automotive and industrial applications. With the progress of machine learning and artificial intelligence (AI), intelligent power management is critical to supplying complex processors and sensors.

PMICs have enabled the development of smaller, more energy-efficient, and reliable electronic solutions. They also play an essential role in environmental aspects and sustainability. By regulating the power supply of electronic devices, PMICs can reduce energy consumption and carbon emissions. Moreover, PMICs are crucial for the development of renewable energies, such as solar and wind power, by enabling efficient power conversion and management.

1.1 What Is a Power Management IC and What Are the Key Requirements?

A PMIC is an electronic component that delivers one or more supply voltages to other circuit blocks at a sufficient power level out of an electrical energy source, as shown in Fig. 1.1. The power conversion can happen in a linear way (usually the more straightforward method) or a switched-mode fashion, delivering energy portions at a specific frequency (usually the more energy-efficient approach).

The PMIC aims to utilize the energy source at maximum efficiency, while the input and output voltage may vary during operation. It also reacts to varying load currents from a few microamperes (standby) to several amperes (full-power operation).

The voltage conversion ratio is the relation between the output and input voltage. The input voltage can be greater or lower than the output voltage , defining a step-down converter (buck converter) or a step-up converter (boost converter). Buck-boost converters allow to vary over a wide range below and above .

Figure 1.1   The role of power management: placed between the energy source and the electronics, it provides one or multiple supply voltages at the correct power level required by the application.

Source: Brunbjorn/Adobe Stock; daniiD/Adobe Stock; Ruslan Kudrin/Adobe Stock; estionx/Adobe Stock.

The power conversion efficiency (sometimes also called ) is defined as the ratio between the output power delivered to the load and the input power dissipated from the energy source,

(1.1)

where accounts for the power dissipated within the power management circuit. It needs to be delivered from the input but does not contribute to the output power. We want to keep as low as possible. For , the efficiency reaches its maximum, . It is common to express the efficiency in percent. In that case, we multiply Eqn. (1.1) by 100%.

PMICs typically include various features like voltage regulators, battery chargers, and power management control algorithms. They may also include monitoring and protection against overcurrent, overheating, and other failure cases. In some applications such as automotive, PMICs are alternatively called smart power ICs, emphasizing the combination of power devices with smart control and monitoring features, all integrated on a single chip.

One major trend is the increasing integration of PMICs. As more functions are combined onto a single chip, the resulting system becomes smaller, more efficient, reliable, and less expensive.

To summarize, the key requirements of PMICs are

Size, volume, footprint, and weight

: The PMIC, including external passive components, must often fit into a confined space like in smartphones or wearables. In portable devices, also the weight is critical. The lower weight is also crucial in automotive as it reduces gas and energy consumption.

Power conversion efficiency

: High efficiency means low losses. The lower the power losses, the longer the battery time. It also causes reduced heat and lower cooling effort, which, in turn, reduces the size and weight of the power management solution.

Reliability, no disturbances, and low noise

: PMICs are noise sources that may impact other sensitive electronic parts due to their switching nature. Handling high voltages and currents causes stress and reliability issues at the component, package, and assembly levels.

Cost

: Like most microelectronic products, there is always some pressure to reduce the cost of the IC and the overall bill of materials at the system level. Power management is not always considered a key differentiator. At the same time, physics cannot be cheated, and PMICs are a fastly growing market with good margins.

1.2 The Smartphone as a Typical Example

Looking at Fig. 1.2a), it is impressive to see how far mobile phones have come since the early 1990s. Back then, phones could only make voice calls and had a standby time of about a day or less. The picture is not to scale, but it was bulky and about 500 g in weight. It is incredible to think about all the features and functions that modern smartphones have today, illustrated in Fig. 1.2b). It is a remarkable example of the outstanding advancements in modern microelectronics. Today's smartphones are much smaller, lighter (typically 150 g), and more powerful. They have considerable computing power, 4K video capture, high-end gaming, virtual reality functions, and higher display resolution. This achievement in performance is thanks to ultra-low-power microelectronics and dedicated power management. Additionally, it is noteworthy that making a phone call is no longer the primary use case for these advanced devices.

Now we do what we usually do not want to; we drop our precious smartphone and look at the electronics inside. Figure 1.2c) shows a printed circuit board of the iPhone 13. The entire electronics is implemented on a layered motherboard sandwich of which Fig. 1.2c) shows a major part. The white frame boxes indicate some of the many PMICs inside the phone. There are more PMICs on the reverse side and other printed circuit board (PCB) parts, including ICs for the audio amplifier and wireless charging. PMICs are a considerable part of the smartphone. Connected to the Li-ion battery with a typical cell voltage of 3.7 V, multi-phase DC–DC converters supply the application processor that comprises multicore CPU and GPU blocks. The voltage levels are dynamically scaled in the range of typically 0.25–1.5 V at load currents of more than 10 A (see dynamic voltage and frequency scaling in Section 1.7). The typical power consumption is in the range of a few watts. In comparison, desktop PC processors dissipate more than 100 W. Running at high switching frequencies of tens of MHz, the voltage converters achieve small size, ultralow profile, and near-load integration at high conversion efficiency. No active cooling is required.

Looking closely, we identify hundreds of tiny passive components surrounding the ICs, mainly capacitors and inductors. As they are energy-storing components, their size can be reduced by decreasing the storing times, in other words, by increasing the switching frequency of the power conversion. It defines one of the leading research goals of today's power management solutions – achieving faster switching while keeping the conversion efficiency high. We will continuously address this topic throughout this book.

Figure 1.2   a) The mobile phone in the early 1990s, b) the smartphone today, and c) the electronics of the iPhone 13 with PMICs marked by white boxes.

Source: a,b) aquatarkus/Adobe Stock; c) ifixit.

1.3 Fundamental Concepts

There are different ways to implement DC–DC converters that convert an input DC voltage to another voltage level. To keep it more practical, we consider a scenario of how to convert 12 to 2 V.

1.3.1 Using a Resistor – The Linear Regulator

We can use a simple resistor to convert 12 to 2 V, as shown in Fig. 1.3. For a load current of 1 A, a resistor of 10 results in . In reality, the resistor is replaced by a controlled transistor such that its conductance is adjusted depending on the operating conditions like input voltage and load current. This approach works very well. However, the voltage drop between input and output is converted into heat. That is why there is significant power dissipation in the resistor, in this example. The power loss is even larger than the output power . In terms of energy efficiency, this concept has a significant drawback.

Nevertheless, it is the fundamental principle of a linear voltage regulator and, by far, the most used power management circuit today. On the positive side, besides its simplicity, it gives a “clean” output voltage with a fast transient response.

Without the excessive losses, there would be no need for alternative power conversion concepts, as discussed in Sections 1.3.2–1.3.4 below. The lower the voltage drop across the resistor (the controlled transistor), the lower the power loss. For this reason, linear regulators are often called low-dropout regulators with the widely used short-term LDO. Chapter 7 is dedicated to linear regulators.

1.3.2 Using Switches and an Inductor – The Inductive DC–DC Converter

To overcome the limited efficiency of the linear regulator, we again ask the question, how can we convert 12 to 2 V? We now use switches as shown in Fig. 1.4a). The switches are combined with an inductor, forming an inductive DC–DC converter as a typical switched-mode power supply (SMPS) implementation. As there is no resistive element in the power path, this concept has the potential to achieve much higher power conversion efficiency compared to a linear regulator.

The operation is as follows: The two switches turn on periodically in a complementary way. They are connected to the so-called switching node. The voltage at that node sees a square wave with an amplitude equal to (12 V in this case), as shown in Fig. 1.4b). The switching node feeds into an L-C low-pass with two functions: filtering and energy storing. The filtering characteristic provides the average at the converter's output. The average corresponds to the area under the switching node transient curve. Hence, is a DC voltage; see Fig. 1.4b). By changing the on-time of S1, the area under the square wave, and, consequently, the level of can be varied. This concept is called pulse-width modulation (PWM), the most popular control method in DC–DC converters. The duty cycle defines the ratio between the on-time and the period time,

Figure 1.3   Conversion of 12 to 2 V by a simple resistor. This is the concept of a linear voltage regulator.

Figure 1.4   Voltage conversion using switches and an inductor achieving high conversion efficiency: a) the fundamental step-down converter; b) waveforms of the switching node voltage and the output voltage .

(1.2)

For the step-down converter in Fig. 1.4, the duty cycle determines the voltage conversion ratio:

(1.3)

There are other topologies of DC–DC converters that have different conversion ratios.

The energy-storing characteristic of the L-C network is required in two ways. If S1 is turned on (S2 is off), energy is brought into the system. The capacitor buffers in case of varying load currents (load transients). is called a bypass capacitor because it bypasses the actual regulator during instantaneous load steps before the control loop can respond. Alternatively, C is referred to as the output buffer capacitor. The inductor delivers the load current if S1 is active and in the second switching phase when S2 turns on (S1 is off). Due to the switching nature of the DC–DC converter, there will always be some finite output voltage ripple. It is a significant disadvantage compared to linear regulators (Section 1.3.1). The ripple can be reduced by enlarging and at the expense of larger size and reduced power density. Another way of reducing the ripple and, at the same time, increasing the output power is to use multiple parallel DC–DC converters. Such multi-phase converters operate in a time-interleave scheme, delivering multiple energy packages during each cycle.

When discussing energy efficiency, it is essential to note that in a steady state, there should be no power loss at a switch. If the voltage across the switch is and the current through the switch is , the loss is :

(1.4)

(1.5)

is the (maximum) blocking voltage of the switch, which is equal to in Fig. 1.4a). The relationship in Eqns. (1.4) and (1.5) is the fundamental reason, why switched-mode operation is widely used in power electronics. In actual designs, there will be various loss contributions, such as the finite on-resistance of the switches. There will also be switching losses and losses in the passive components. However, these losses are usually much lower compared to a linear regulator introduced in Section 1.3.1. Conversion efficiencies of more than 90% can be achieved. Chapter 10 covers inductive DC–DC converters comprehensively.

1.3.3 Switches and Capacitors – The SC Converter

Another way of voltage conversion is the combination of switches with capacitors. This concept has become very attractive for highly integrated power management designs due to the availability of high-density integrated capacitors in advanced CMOS technologies. Figure 1.5 shows a typical circuit along with the equivalent circuits in the two switching phases. During phase , both capacitors are connected in series to . The capacitors are parallel in phase . The circuit periodically changes from a series to a parallel configuration, reducing the output voltage to half of the input voltage. Interestingly, this behavior is independent of the actual capacitor values. Their values determine the amount of charge shared between switching cycles, but in steady state, will be exactly half of . Note that ideally, no losses have occurred so far.

How can we convert 12 to 2 V? We can use two conversion stages. The first results in 6 V, the second one gives 3 V. How do we get to the target value of ? We take advantage of the fact that can deliver only a limited charge. In other words, we let the load current discharge the output capacitor until reaches exactly 2 V. Most easily, this can be achieved by adjusting the clock frequency. Unfortunately, this is when the SC converter introduces power loss due to charge redistribution (). The output voltage drop from 3 to 2 V can be seen as a voltage drop across an equivalent output resistance. Significant research has been dedicated to finding improved SC converter topologies and control mechanisms that minimize these losses. SC converters are further explored in Chapter 9.

1.3.4 Switches and Capacitors and Inductors – The Hybrid Converter

This approach takes the SC converter of Fig. 1.5 and adds an inductor, as illustrated in Fig. 1.6. The combination of and leads to the name hybrid converter. It utilizes the benefits of the inductive and capacitive conversion concepts presented in Sections 1.3.2 and 1.3.3. Two mechanisms help improve conversion efficiency. The inductor ensures soft charging of the capacitor, which eliminates charge redistribution losses and minimizes the equivalent output resistance. and also form a resonant tank, which can achieve zero-current switching of the power switches. This way, the switching losses can be significantly reduced. On the downside, this concept has higher complexity than an inductive or capacitive converter. However, handling complexity is one of the great benefits of advanced microelectronics. Chapter 11 covers hybrid DC–DC converters comprehensively.

Figure 1.5   Voltage conversion using capacitors: a) the fundamental switched-capacitor voltage converter; b) the equivalent circuits in phases and , alternating between series and parallel configurations.

Figure 1.6   A hybrid converter formed by adding an inductor to an SC converter resulting in higher conversion efficiency.

1.4 Power Management Systems

Electronic systems usually do not require only one supply voltage. Instead, various functional blocks have different supply voltage and power requirements. Figure 1.7 shows two examples of power management systems. Dedicated converters are assigned to supply each block at the point of load (PoL). State-of-the-art power management systems comprise multiple PoL regulators and DC–DC converters to supply microcontroller units (MCU), processors (CPU, GPU, and DSP), as well as analog and mixed-signal circuits.

In space-constraint applications such as smartphones, multiple voltage regulators are implemented in a single IC to minimize their footprint. Known as the multirail power supply (MRPS), it is the leading PMIC type with a market share of 20% (see Section 1.9).

Figure 1.7   Point-of-load (PoL) power management systems: a) handheld devices operating from a Li-ion battery have lower step-down ratios as compared to b) automotive, industrial, and data center applications that operate from a higher supply voltage like a car battery.

For large step-down ratios, linear regulators are not efficient. However, switched-mode DC–DC converters may not fulfill strict supply ripple and noise requirements for sensitive analog circuits such as sensor front ends. Hence, various conversion stages are combined, as illustrated in Fig. 1.7.

Combining a DC–DC converter as a first conversion stage with a subsequent linear regulator (LDO) is beneficial. The DC–DC converter guarantees high efficiency, while the LDO ensures a “clean” output voltage with a fast transient response. If the intermediate voltage , provided by the DC–DC converter, is close to the target output voltage, the linear voltage regulator will also show an acceptable efficiency. We can calculate the overall efficiency by multiplying the efficiency values of each stage:

(1.6)

For a large step-down ratio, i.e., if is much greater than , achieving high efficiency will be more challenging.

As illustrated in Fig. 1.7a), a Li-ion battery typically supplies portable devices such as smartphones and wearables with a voltage range of 2.5–4.4 V. There is a moderate step-down ratio. The automotive application shown in Fig. 1.7