Emerging Nanoelectronic Devices E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 1187

Veröffentlichungsjahr: 2014

Beschreibung

Emerging Nanoelectronic Devices focuses on the future direction of semiconductor and emerging nanoscale device technology. As the dimensional scaling of CMOS approaches its limits, alternate information processing devices and microarchitectures are being explored to sustain increasing functionality at decreasing cost into the indefinite future.  This is driving new paradigms of information processing enabled by innovative new devices, circuits, and architectures, necessary to support an increasingly interconnected world through a rapidly evolving internet. This original title provides a fresh perspective on emerging research devices in 26 up to date chapters written by the leading researchers in their respective areas. It supplements and extends the work performed by the Emerging Research Devices working group of the International Technology Roadmap for Semiconductors (ITRS). 

Key features: 

• Serves as an authoritative tutorial on innovative devices and architectures that populate the dynamic world of “Beyond CMOS” technologies.
• Provides a realistic assessment of the strengths, weaknesses and key unknowns associated with each technology.
• Suggests guidelines for the directions of future development of each technology.
• Emphasizes physical concepts over mathematical development.
• Provides an essential resource for students, researchers and practicing engineers.

Leseprobe

CONTENTS

Cover

Title Page

Copyright

Dedication

Preface

List of Contributors

Acronyms

Part One: Introduction

Chapter 1: The Nanoelectronics Roadmap

1.1 Introduction

1.2 Technology Scaling: Impact and Issues

1.3 Technology Scaling: Scaling Limits of Charge-based Devices

1.4 The International Technology Roadmap for Semiconductors

1.5 ITRS Emerging Research Devices International Technology Working Group

1.6 Guiding Performance Criteria

1.7 Selection of Nanodevices as Technology Entries

1.8 Perspectives

References

Chapter 2: What Constitutes a Nanoswitch? A Perspective

2.1 The Search for a Better Switch

2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain

2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain?

2.4 Giant Spin Hall Effect: A Route to Gain

2.5 Other Possibilities for Switches with Gain

2.6 What do Alternative Switches Have to Offer?

2.7 Perspective

2.8 Summary

Acknowledgments

References

Part Two: Nanoelectronic Memories

Chapter 3: Memory Technologies: Status and Perspectives

3.1 Introduction: Baseline Memory Technologies

3.2 Essential Physics of Charge-based Memory

3.3 Dynamic Random Access Memory

3.4 Flash Memory

3.5 Static Random Access Memory

3.6 Summary and Perspective

Appendix: Memory Array Interconnects

Acknowledgments

References

Chapter 4: Spin Transfer Torque Random Access Memory

4.1 Chapter Overview

4.2 Spin Transfer Torque

4.3 STT-RAM Operation

4.4 STT-RAM with Perpendicular Anisotropy

4.5 Stack and Material Engineering for Jc Reduction

4.6 Ultra-Fast Switching of MTJs

4.7 Spin–Orbit Torques for Memory Application

4.8 Current Demonstrations for STT-RAM

4.9 Summary and Perspectives

References

Chapter 5: Phase Change Memory

5.1 Introduction

5.2 Device Operation

5.3 Material Properties

5.4 Device and Material Scaling to the Nanometer Size

5.5 Multi-Bit Operation and 3D Integration

5.6 Applications

5.7 Future Outlook

5.8 Summary

Acknowledgments

References

Chapter 6: Ferroelectric FET Memory

6.1 Introduction

6.2 Ferroelectric FET for Flash Memory Application

6.3 Ferroelectric FET for SRAM Application

6.4 System Consideration: SSD System with Fe-NAND Flash Memory

6.5 Perspectives and Summary

References

Chapter 7: Nano-Electro-Mechanical (NEM) Memory Devices

7.1 Introduction and Rationale for a Memory Based on NEM Switch

7.2 NEM Relay and Capacitor Memories

7.3 NEM-FET Memory

7.4 Carbon-based NEM Memories

7.5 Opportunities and Challenges for NEM Memories

References

Chapter 8: Redox-based Resistive Memory

8.1 Introduction

8.2 Physical Fundamentals of Redox Memories

8.3 Electrochemical Metallization Memory Cells

8.4 Valence Change Memory Cells

8.5 Performance

8.6 Summary

References

Chapter 9: Electronic Effect Resistive Switching Memories

9.1 Introduction

9.2 Charge Injection and Trapping

9.3 Mott Transition

9.4 Ferroelectric Resistive Switching

9.5 Perspectives

9.6 Summary

References

Chapter 10: Macromolecular Memory

10.1 Chapter Overview

10.2 Macromolecules

10.3 Elementary Physical Chemistry of Macromolecular Memory

10.4 Classes of Macromolecular Memory Materials and Their Performance

10.5 Perspectives

10.6 Summary

Acknowledgments

References

Chapter 11: Molecular Transistors

11.1 Introduction

11.2 Experimental Approaches

11.3 Molecular Transistors

11.4 Molecular Design

11.5 Perspectives

Acknowledgments

References

Chapter 12: Memory Select Devices

12.1 Introduction

12.2 Crossbar Array and Memory Select Devices

12.3 Memory Select Device Options

12.4 Challenges of Memory Select Devices

12.5 Summary

References

Chapter 13: Emerging Memory Devices: Assessment and Benchmarking

13.1 Introduction

13.2 Common Emerging Memory Terminology and Metrics

13.3 Redox RAM

13.4 Emerging Ferroelectric Memories

13.5 Mott Memory

13.6 Macromolecular Memory

13.7 Carbon-based Resistive Switching Memory

13.8 Molecular Memory

13.9 Assessment and Benchmarking

13.10 Summary and Conclusions

Acknowledgments

References

Part Three: Nanoelectronic Logic and Information Processing

Chapter 14: Re-Invention of FET

14.1 Introduction

14.2 Historical and Future Trend of MOSFETs

14.3 Near-term Solutions

14.4 Long-term Solutions

14.5 Summary

References

Chapter 15: Graphene Electronics

15.1 Introduction

15.2 Properties of Graphene

15.3 Graphene MOSFETs for Mainstream Logic and RF Applications

15.4 Graphene MOSFETs for Nonmainstream Applications

15.5 Graphene NonMOSFET Transistors

15.6 Perspectives

Acknowledgment

References

Chapter 16: Carbon Nanotube Electronics

16.1 Carbon Nanotubes – The Ideal Transistor Channel

16.2 Operation of the CNTFET

16.3 Important Aspects of CNTFETs

16.4 Scaling CNTFETs to the Sub-10 Nanometer Regime

16.5 Material Considerations

16.6 Perspective

16.7 Conclusion

References

Chapter 17: Spintronics

17.1 Introduction

17.2 Spin Transistors

17.3 Magnetic Logic Circuits

17.4 Summary

References

Chapter 18: NEMS Switch Technology

18.1 Electromechanical Switches for Digital Logic

18.2 Actuation Mechanisms

18.3 Electrostatic Switch Designs

18.4 Reliability and Scalability

References

Chapter 19: Atomic Switch

19.1 Chapter Overview

19.2 Historical Background of the Atomic Switch

19.3 Fundamentals of Atomic Switches

19.4 Various Atomic Switches

19.5 Perspectives

References

Chapter 20: ITRS Assessment and Benchmarking of Emerging Logic Devices

20.1 Introduction

20.2 Overview of the ITRS Roadmap for Emerging Research Logic Devices

20.3 Recent Results for Selected Emerging Devices

20.4 Perspective

20.5 Summary

Acknowledgments

References

Part Four: Concepts for Emerging Architectures

Chapter 21: Nanomagnet Logic: A Magnetic Implementation of Quantum-dot Cellular Automata

21.1 Introduction

21.2 Technology Background

21.3 NML Circuit Design Based on Conventional, Boolean Logic Gates

21.4 Alternative Circuit Design Techniques and Architectures

21.5 Retrospective, Future Challenges, and Future Research Directions

References

Chapter 22: Explorations in Morphic Architectures

22.1 Introduction

22.2 Neuromorphic Architectures

22.3 Cellular Automata Architectures

22.4 Taxonomy of Computational Ability of Architectures

22.5 Summary

References

Chapter 23: Design Considerations for a Computational Architecture of Human Cognition

23.1 Introduction

23.2 Features of Biological Computation

23.3 Evolution of Behavior as a Basis for Cognitive Architecture Design

23.4 Considerations for a Cognitive Architecture

23.5 Emergent Cognition

23.6 Perspectives

References

Chapter 24: Alternative Architectures for NonBoolean Information Processing Systems

24.1 Introduction

24.2 Hierarchical Associative Memory Models

24.3 N-Tree Model

24.4 Summary and Conclusion

Acknowledgments

References

Chapter 25: Storage Class Memory

25.1 Introduction

25.2 Traditional Storage: HDD and Flash Solid-state Drives

25.3 What is Storage Class Memory?

25.4 Target Specifications for SCM

25.5 Device Candidates for SCM

25.6 Architectural Issues in SCM

25.7 Conclusions

References

Part Five: Summary, Conclusions, and Outlook for Nanoelectronic Devices

Chapter 26: Outlook for Nanoelectronic Devices

26.1 Introduction

26.2 Quantitative Logic Benchmarking for Beyond CMOS Technologies

26.3 Survey-based Critical Assessment of Emerging Devices

26.4 Retrospective Assessment of ERD Tracked Technologies

References

Index

End User License Agreement

List of Tables

Table 3.1

Table 3.2

Table 3.3

Table 3.4

Table 3.5

Table 3.6

Table 3A.1

Table 3A.2

Table 4.1

Table 5.1

Table 5.2

Table 6.1

Table 8.1

Table 9.1

Table 9.2

Table 9.3

Table 10.1

Table 10.2

Table 12.1

Table 12.2

Table 12.3

Table 12.4

Table 13.1

Table 13.2

Table 13.3

Table 13.4

Table 15.1

Table 15.2

Table 15.3

Table 16.1

Table 17.1

Table 17.2

Table 17.3

Table 17.4

Table 17.5

Table 17.6

Table 19.1

Table 20.1

Table 22.1

Table 22.2

Table 24.1

Table 25.1

Table 25.2

Table 26.1

Table 26.2

Table 26.3

Table 26.4

Table 26.5

List of Illustrations

Figure P.1

Figure 1.1

Figure 1.2

Figure 1.3

Figure 2.1

Figure 2.2

Figure 2.3

Figure 2.4

Figure 2.5

Figure 2.6

Figure 2.7

Figure 2.8

Figure 2.9

Figure 2.10

Figure 2.11

Figure 2.12

Figure 3.1

Figure 3.2

Figure 3.3

Figure 3.4

Figure 3.5

Figure 3.6

Figure 3.7

Figure 4.1

Figure 4.2

Figure 4.3

Figure 4.4

Figure 4.5

Figure 4.6

Figure 4.7

Figure 4.8

Figure 4.9

Figure 4.10

Figure 4.11

Figure 4.12

Figure 4.13

Figure 4.14

Figure 5.1

Figure 5.2

Figure 5.3

Figure 5.4

Figure 5.5

Figure 5.6

Figure 5.7

Figure 5.8

Figure 5.9

Figure 5.10

Figure 5.11

Figure 5.12

Figure 5.13

Figure 5.14

Figure 5.15

Figure 5.16

Figure 5.17

Figure 6.1

Figure 6.2

Figure 6.3

Figure 6.4

Figure 6.5

Figure 6.6

Figure 6.7

Figure 6.8

Figure 6.9

Figure 6.10

Figure 6.11

Figure 6.12

Figure 6.13

Figure 6.14

Figure 7.1

Figure 7.2

Figure 7.3

Figure 7.4

Figure 7.5

Figure 7.6

Figure 7.7

Figure 7.8

Figure 7.9

Figure 7.10

Figure 7.11

Figure 8.1

Figure 8.2

Figure 8.3

Figure 8.4

Figure 8.5

Figure 8.6

Figure 8.7

Figure 8.8

Figure 8.9

Figure 8.10

Figure 8.11

Figure 8.12

Figure 8.13

Figure 8.14

Figure 8.15

Figure 8.16

Figure 8.17

Figure 8.18

Figure 8.19

Figure 9.1

Figure 9.2

Figure 9.3

Figure 9.4

Figure 10.1

Figure 10.2

Figure 10.3

Figure 11.1

Figure 11.2

Figure 11.3

Figure 11.4

Figure 11.5

Figure 11.6

Figure 11.7

Figure 11.8

Figure 11.9

Figure 11.10

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Figure 11.13

Figure 11.14

Figure 11.15

Figure 11.16

Figure 12.1

Figure 12.2

Figure 12.3

Figure 12.4

Figure 12.5

Figure 12.6

Figure 13.1

Figure 13.2

Figure 13.3

Figure 13.4

Figure 13.5

Figure 14.1

Figure 14.2

Figure 14.3

Figure 14.4

Figure 14.5

Figure 14.6

Figure 14.7

Figure 14.8

Figure 14.9

Figure 14.10

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Figure 14.12

Figure 14.13

Figure 14.14

Figure 14.15

Figure 14.16

Figure 14.17

Figure 14.18

Figure 14.19

Figure 14.20

Figure 14.21

Figure 14.22

Figure 14.23

Figure 14.24

Figure 14.25

Figure 15.1

Figure 15.2

Figure 15.3

Figure 15.4

Figure 15.5

Figure 15.6

Figure 16.1

Figure 16.2

Figure 16.3

Figure 16.4

Figure 16.5

Figure 16.6

Figure 16.7

Figure 16.8

Figure 16.9

Figure 16.10

Figure 16.11

Figure 16.12

Figure 16.13

Figure 16.14

Figure 16.15

Figure 17.1

Figure 17.2

Figure 17.3

Figure 17.4

Figure 17.5

Figure 17.6

Figure 17.7

Figure 17.8

Figure 17.9

Figure 17.10

Figure 17.11

Figure 17.12

Figure 17.13

Figure 17.14

Figure 17.15

Figure 17.16

Figure 17.17

Figure 17.18

Figure 17.19

Figure 17.20

Figure 17.21

Figure 18.1

Figure 18.2

Figure 18.3

Figure 18.4

Figure 18.5

Figure 18.6

Figure 18.7

Figure 18.8

Figure 18.9

Figure 18.10

Figure 18.11

Figure 19.1

Figure 19.2

Figure 19.3

Figure 19.4

Figure 19.5

Figure 19.6

Figure 19.7

Figure 19.8

Figure 19.9

Figure 19.10

Figure 19.11

Figure 19.12

Figure 19.13

Figure 20.1

Figure 21.1

Figure 21.2

Figure 21.3

Figure 21.4

Figure 21.5

Figure 21.6

Figure 21.7

Figure 21.8

Figure 21.9

Figure 21.10

Figure 21.11

Figure 21.12

Figure 21.13

Figure 22.1

Figure 22.2

Figure 22.3

Figure 22.4

Figure 23.1

Figure 23.2

Figure 23.3

Figure 23.4

Figure 23.5

Figure 24.1

Figure 24.2

Figure 24.3

Figure 24.4

Figure 24.5

Figure 24.6

Figure 24.7

Figure 24.8

Figure 24.9

Figure 24.10

Figure 24.11

Figure 24.12

Figure 24.13

Figure 24.14

Figure 24.15

Figure 24.16

Figure 24.17

Figure 24.18

Figure 24.19

Figure 24.20

Figure 24.21

Figure 24.22

Figure 24.23

Figure 24.24

Figure 24.25

Figure 24.26

Figure 24.27

Figure 24.28

Figure 24.29

Figure 24.30

Figure 24.31

Figure 24.32

Figure 24.33

Figure 26.1

Figure 26.2

Figure 26.3

Figure 26.4

Figure 26.5

Figure 26.6

Figure 26.7

Guide

Cover

Table of Contents

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Part 1

Chapter 1

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Emerging Nanoelectronic Devices

An Chen

GLOBALFOUNDRIES, USA

James Hutchby

Semiconductor Research Corporation, USA

Victor Zhirnov

Semiconductor Research Corporation, USA

George Bourianoff

Intel Corporation, USA

This edition first published 2015

© 2015 John Wiley and Sons Ltd

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Library of Congress Cataloging-in-Publication Data

Emerging nanoelectronic devices / edited by Dr An Chen, Dr James Hutchby,

Dr Victor Zhirnov, Dr George Bourianoff.

pages cm

Includes bibliographical references and index.

ISBN 978-1-118-44774-1 (cloth)

1. Nanoelectronics. 2. Nanoelectromechanical systems. 3. Nanostructured materials. I. Chen, An (Electronics engineer), editor. II. Hutchby, James, editor. III. Zhirnov, Victor V., editor. IV. Bourianoff, George, editor.

TK7874.84.E32 2014

621.381–dc23

2014029299

Dedication

ToLinda Wilson

Preface

Continued dimensional and functional1 scaling of CMOS2 integrated circuit technology is driving information processing systems into a broadening spectrum of new applications. Many of these applications are enabled by performance gains and/or increased complexity realized by scaling. Because dimensional scaling of CMOS eventually will approach fundamental limits, several new alternative information processing devices and microarchitectures for existing or new functions are being explored to sustain the historical integrated circuit scaling cadence and reduction of cost/function in future decades. This is driving interest in new devices for information processing and memory, new technologies for heterogeneous integration of multiple functions (a.k.a. “More than Moore”), and new paradigms for systems architecture.