Frequency Acquisition Techniques for Phase Locked Loops E-Book

Daniel B. Talbot

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 241

Veröffentlichungsjahr: 2012

Beschreibung

How to acquire the input frequency from an unlocked state

A phase locked loop (PLL) by itself cannot become useful until it has acquired the applied signal's frequency. Often, a PLL will never reach frequency acquisition (capture) without explicit assistive circuits. Curiously, few books on PLLs treat the topic of frequency acquisition in any depth or detail. Frequency Acquisition Techniques for Phase Locked Loops offers a no-nonsense treatment that is equally useful for engineers, technicians, and managers.

Since mathematical rigor for its own sake can degenerate into intellectual "rigor mortis," the author introduces readers to the basics and delivers useful information with clear language and minimal mathematics. With most of the approaches having been developed through years of experience, this completely practical guide explores methods for achieving the locked state in a variety of conditions as it examines:

• Performance limitations of phase/frequency detector–based phase locked loops
• The quadricorrelator method for both continuous and sampled modes
• Sawtooth ramp-and-sample phase detector and how its waveform contains frequency error information that can be extracted
• The benefits of a self-sweeping, self-extinguishing topology
• Sweep methods using quadrature mixer-based lock detection
• The use of digital implementations versus analog

Frequency Acquisition Techniques for Phase Locked Loops is an important resource for RF/microwave engineers, in particular, circuit designers; practicing electronics engineers involved in frequency synthesis, phase locked loops, carrier or clock recovery loops, radio-frequency integrated circuit design, and aerospace electronics; and managers wanting to understand the technology of phase locked loops and frequency acquisition assistance techniques or jitter attenuating loops.
Errata can be found by visiting the Book Support Site at: http://booksupport.wiley.com

Leseprobe

Contents

Cover

Series Page

Title Page

Copyright

Dedication

Toolkit

Preface

Chapter 1: Introduction

Chapter 2: A Review of PLL Fundamentals

2.1 What is a PLL?

2.2 Second-Order PLL

2.3 Second-Order PLL Type One

2.4 Second-Order PLL Type Two

2.5 Higher-Order PLL's

2.6 Disturbances

2.7 Frequency Steering and Capture

2.8 Effect of DC Offsets or Noise Prior to the Loop Filter

2.9 Injection-Locked Oscillations

Chapter 3: Simulating the PLL Linear Operation Mode

3.1 Linear Model

3.2 A Word About Damping

Chapter 4: Sideband Suppression Filtering

4.1 Reference Sidebands and VCO Pushing

4.2 Superiority of the Cauer (or Elliptical) Filter

Chapter 5: Pros and Cons of Sampled Data Phase Detection

5.1 What are the Forms of Sampled Data Phase Detectors?

5.2 A. Ramp and Sample Analog Phase Detector

5.3 B. The RF Sampling Phase Detector

5.4 C. Edge-Triggered S-R Flip-Flop

5.5 D. Edge-Triggered Flip-Flop Ensemble

5.6 E. Sample and Hold as a Phase Detector

Chapter 6: Phase Compression

Chapter 7: Hard Limiting of a Signal Plus Noise

Chapter 8: Phase Noise and Other Spurious Interferers

8.1 The Mechanism for Phase Noise in an Oscillator

8.2 Additive Noise in an FM Channel and the Bowtie

8.3 Importance of FM Theory to Frequency Acquisition

Chapter 9: Impulse Modulation and Noise Aliasing

9.1 Impulse Train Spectrum

9.2 Sampling Phase Detector Noise

9.3 Spur Aliasing

Chapter 10: Time and Phase Jitter, Heterodyning, and Multiplication

10.1 Heterodyning and Resulting Time Jitter

10.2 Frequency Multiplication and Angle Modulation Index

10.3 Frequency Multiplication's Role in Carrier Recovery

Chapter 11: Carrier Recovery Applications and Acquisition

11.1 Frequency Multiplier Carrier Recovery in General

11.2 The Simplest Form of Costas PLL

11.3 Higher Level Quadrature Demodulation Costas PLL

11.4 False Lock in BPSK Costas PLL

11.5 Additional Measures for Prevention of False Locking

11.6 False Lock Prevention Using DC Offset

Chapter 12: Notes on Sweep Methods

12.1 Sweep Waveform Superimposed Directly on VCO Input

12.2 Maximum Sweep Rate (Acceleration)

12.3 False Lock due to High-Order Filtering

12.4 Sweep Waveform Applied Directly to PLL Loop Integrator

12.5 Self-Sweeping PLL

Chapter 13: Nonsweep Acquisition Methods

13.1 Delay Line Frequency Discriminator

13.2 The Fully Unbalanced Quadricorrelator

13.3 The Fully Balanced Quadricorrelator

13.4 The Multipulse Balanced Quadricorrelator

13.5 Conclusion Regarding Pulsed Frequency Detection

13.6 Quadricorrelator Linearity

13.7 Limiter Asymmetry Due to DC Offset

13.8 Taylor Series Demonstrates Second-Order-Caused DC Offset

13.9 Third-Order Intermodulation Distortion and Taylor Series

Chapter 14: AM Rejection in Frequency Detection Schemes

14.1 AM Rejection with Limiter and Interferer

14.2 AM Rejection of the Balanced Limiter/Quadricorrelator versus the Limiter/Discriminator in the Presence of a Single Spur

14.3 Impairment due to Filter Response Tilt (Asymmetry)

14.4 Bandpass Filter Geometric and Arithmetic Symmetry

14.5 Comments on Degree of Scrutiny

Chapter 15: Interfacing the Frequency Discriminator to the PLL

15.1 Continuous Connection: Pros and Cons

15.2 Connection to PLL via a Dead Band

15.3 Switched Connection

Chapter 16: Actual Frequency Discriminator Implementations

16.1 Quadricorrelator, Low-Frequency Implementation

16.2 Frequency Ratio Calculating Circuit for Wide-Bandwidth Use

16.3 Dividing the Frequency and Resultant Implementation

16.4 Marriage of Both Frequency and Phaselock Loops

16.5 Comments on Spurs' Numerical Influence on the VCO

16.6 Frequency Compression

Chapter 17: Clock Recovery Using a PLL

17.1 PLL only

17.2 PLL with Sideband Crystal Filter (s)

17.3 PLL with Sideband Cavity Filter

17.4 The Hogge Phase Detector

17.5 Bang–Bang Phase Detectors

Chapter 18: Frequency Synthesis Applications

18.1 Direct Frequency Synthesis with Wadley Loop

18.2 Indirect Frequency Synthesis with PLLs

18.3 Simple Frequency Acquisition Improvement for a PLL

18.4 Hybrid Frequency Synthesis with DDS and PLL

18.5 Phase Noise Considerations

18.6 Pros and Cons of DDS-Augmented Synthesis

18.7 Multiple Loops

18.8 Reference Signal Considerations and Filtering

18.9 SNR of Various Phase Detectors

18.10 Phase Detector Dead Band (Dead Zone) and Remediation

18.11 Sideband Energy due to DC Offset Following Phase Detector

Example

18.12 Brute Force PLL Frequency Acquisition via Speedup

18.13 Short-Term and Long-Term Settling

18.14 N-over-M Synthesis

Chapter 19: Injection Pulling of Multiple VCO's as in a Serdes

19.1 Allowable Coupling Between any Two VCOs versus Q and BW

19.2 Topology Suggestion for Eliminating the Injection Pulling

Chapter 20: Digital PLL Example

Chapter 21: Conclusion

References

Index

IEEE Press445 Hoes LanePiscataway, NJ 08854

IEEE Press Editorial Board

John B. Anderson, Editor in Chief

R. AbhariG. W. ArnoldF. CanaveroD. GoldgofB-M. HaemmerliD. JacobsonM. LanzerottiO. P. MalikS. NahavandiT. SamadG. Zobrist

Kenneth Moore, Director of IEEE Book and Information Services (BIS)

Cover Image: Courtesy of Daniel B. Talbot

Copyright © 2012 by The Institute of Electrical and Electronics Engineers, Inc.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved

Published simultaneously in Canada

No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, [phone], fax [phone], or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, [phone], fax [phone], or online at http://www.wiley.com/go/permission.

Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages.

For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at [phone], outside the United States at [phone] or fax [phone].

Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com.

Library of Congress Cataloging-in-Publication Data:

ISBN: 9781118168103

This book is dedicated to our loved ones who have found their final homes.

Toolkit

Several useful tools, free simulation software, and illustrations accompany this book as a special bonus on the web at: http://booksupport.wiley.com. The reader can thus follow along and run the same simulations described in this book, as well as claim several free tools he/she will find useful throughout an engineering career.

Preface

Many excellent treatises covering phase-locked loops (PLLs) have been published, but to the author's surprise, few books exist covering the frequency acquisition assistance techniques necessary and/or available. A PLL by itself cannot become useful until it has acquired the applied signal's frequency. This acquisition process has been treated with extreme mathematical and/or graphical rigor in the past, mainly by Viterbi and Jet Propulsion Lab (JPL =) in publications featuring phase-plane trajectories. However, most of the PLL circuits in other analyses had no explicit assistive circuitry included. Often, a PLL will never reach frequency acquisition (called “capture” in most texts) by itself without explicit assistive circuits (with exception of the overused phase/frequency detector-based approach that has performance drawbacks during settled closed-loop operation that will be identified and explained later in detail).

This book attempts to bridge this information gap. Since mathematical rigor for its own sake can degenerate to intellectual “rigor mortis,” the author hopes to offer a treatment of the subject that can be comprehended by both engineer and technician (except for an occasional formula that might be included for essential reasons and even then the book is organized so that the nonmathematician can skip it and move on to the essence of the thought being discussed). A more important reason exists for avoiding excessive mathematical verbosity: often the objective gets forgotten and lost in the minutia; assumptions are too confining or too optimistic or too pessimistic, and the motive behind the complexity is not well stated. For this reason, we have decided to focus on the practical and to simulate actual situations wherever possible, both for clarity, so that the reader can take an active role in altering the assumptions and qualifications of a certain architecture and then rerun the simulation to see what his or her results might be. It is disappointing to be shown a solution that does not fit the problem.

Most of the approaches in this book have been developed through years of experience rather than from articles and books, but where references exist they will be cited. The author believes that it is good to communicate in something besides “mathspeak” (e.g., the English language is quite powerful) and to go directly to the fundamentals. Einstein once stated, “Everything should be made as simple as possible, but not simpler.” So get out your 64-bit Divining Rod and 32-bit abacus. The author's intention is to communicate with you, the reader, not snow you, “educate” you, and “intellectually subordinate” you. One can get subordination for free; one need not pay good money for it by buying a math-heavy book in which the author's main accomplishment is to write as esoterically as he possibly can and leave the reader with a feeling of general intellectual inferiority, even if unintentional. It is a hope that clarity trumps verbosity and it remains for you, the reader, to determine whether we succeed.

Chapter 1

Introduction

We must begin any treatment of PLL frequency acquisition with a review of the fundamentals of the PLL. Thereafter, the following subjects can be discussed (not necessarily in that order):

a. The difference between the type I second-order and the type II second-order PLL and why the type II second-order PLL is usually preferred

b. The mechanism for acquisition in an ordinary unassisted PLL

c. The multiplying phase detector (numerical multiplier, analog multiplier, RF mixer, or XOR gate used as a multiplier) and effects of hard limiting

d. The edge-triggered digital phase/frequency detector

e. The ramp-and-sample phase detector and a technique to exploit its uniqueness to realize wideband capture acquisition assistance

f. The quadricorrelator, balanced and unbalanced

g. The Costas PLL, “Frequency Squaring” Carrier Recovery, etc.

h. The clock and data recovery PLL

i. PLL considerations for frequency synthesizers

j. Signal-to-noise ratio (SNR) of the various phase detectors

k. Short- and long-term phase and frequency settling effects in a PLL

l. The effect of a phase detector dead zone on phase noise and wander

m. The reduction or elimination of phase detector dead zone and impact on reference frequency suppression

n. Sweeping techniques

o. Sweep disabling after lock and a self-disabling method

p. False locking on data or modulation sidebands

q. Preventing false lock on spurious signals, such as modulation sidebands

r. Comments on converting an analog to an all-digital architecture

s. Limiting acceleration in swept acquisition methods

t. Cycle slipping due to excessive acceleration or modulation within the loop

u. Killing the quadricorrelator output during final lock to suppress its otherwise added phase noise; using a dead zone versus a switch

v. DC offsets and noise and the effect on PLL acquisition

w. Heroic spur suppression using DC offset minimization and brickwall filtering

x. Brute force methods such as wideband/narrowband PLL bandwidth modes

y. The frequency ratio detector using counter techniques

z. Advantages and disadvantages of different assistive techniques and when to use which technique

Chapter 2

A Review of PLL Fundamentals

2.1 What is a PLL?

A PLL (phase-locked loop) is a circuit that varies a VCO (voltage-controlled oscillator) frequency (hence its phase) relative to that of an input until it matches that of the input signal [1,2]. If the VCO is replaced with a voltage-controlled phase modulator or a voltage-controlled delay element, it is then called a DLL (delay-locked loop) and cannot operate offset in its resting frequency.