Future Trends in Microelectronics E-Book

Serge Luryi

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: Wiley - IEEE
• Sprache: Englisch

Seitenzahl: 690

Veröffentlichungsjahr: 2013

Beschreibung

Leaders in the field predict the future of the microelectronics industry This seventh volume of Future Trends in Microelectronics summarizes and synthesizes the latest high-level scientific discussions to emerge from the Future Trends in Microelectronics international workshop, which has occurred every three years since 1995. It covers the full scope of cutting-edge topics in microelectronics, from new physical principles (quantum computing, correlated electrons), to new materials (piezoelectric nanostructures, terahertz plasmas), to emerging device technologies (embedded magnetic memories, spin lasers, and biocompatible microelectronics). An ideal book for microelectronics professionals and students alike, this volume of Future Trends in Microelectronics: * Identifies the direction in which microelectronics is headed, enabling readers to move forward with research in an informed, efficient, and profitable manner * Includes twenty-nine contributor chapters by international authorities from leading universities, major semiconductor companies, and government laboratories * Provides a unified, cohesive exploration of various trends in microelectronics, looking to future opportunities, rather than past successes

Leseprobe

Contents

Cover

Half Title page

Title page

Copyright page

Preface

Acknowledgments

References

Part I: Innovations in Electronics and Systems

Technology Innovation, Reshaping the Microelectronics Industry

1. Introduction

2. Mainstream silicon technology: Memory

3. Mainstream silicon technology: Logic

4. Emerging computing architectures

5. Silicon technology in the field of energy

6. Silicon technology and nitride devices

7. Silicon technology and photonics

8. Silicon technology and medical or healthcare applications

9. Future prospects

Acknowledgments

References

Challenges and Limits for Very Low Energy Computation

1. Introduction

2. Results and discussion

3. Conclusions

Acknowledgments

References

Getting Rid of the DRAM Capacitor

1. Introduction

2. Origins of floating-body 1T-DRAMs

3. Second coming of floating-body 1T-DRAMs

4. Multi-body FB-1T-DRAMs

5. Final remarks and conclusions

Acknowledgments

References

Physics and Design of Nanoscale Field Effect Diodes for Memory and ESD Protection Applications

1. Introduction

2. Structure and principle of operation of the FED

3. FED as a memory cell

3. FED as an ESD protection element

4. Conclusions

Acknowledgments

References

Sharp-Switching CMOS-Compatible Devices with High Current Drive

1. Introduction

2. Enhancement of TFET ION using Si1-xGex and Ge channel materials

3. Bipolar-enhanced TFET: BET-FET

4. A feedback-based high-current sharp-switching device: Z2-FET

5. Conclusions

Acknowledgments

References

Magnetic Tunnel Junctions with a Composite Free Layer: A New Concept for Future Universal Memory

1. Introduction

2. Magnetic memory technologies

3. MTJs with a composite free layer

4. Conclusions

Acknowledgments

References

Silicon Carbide High Temperature Electronics – Is This Rocket Science?

1. Introduction

2. Advantages of SiC electronics

3. Exploration of Venus

4. Proposed system for Venus lander

5. Results

6. Conclusion

Acknowledgments

References

Microchip Post-Processing: There is Plenty of Room at the Top

1. Introduction

2. Adding functionality to CMOS

3. Emerging microsystems

4. Conclusions

Acknowledgments

References

EUV Lithography: Today and Tomorrow

1. Introduction

2. A very short history of EUVL

3. Present of EUVL: Update on the current situation

4. EUVL and alternatives: The future

5. Conclusions

Acknowledgments

References

Manufacturability and Nanoelectronic Performance

1. Introduction

2. Manufacturability

3. Reproducibility of artefacts made by top-down methods

4. Reproducibility of artefacts made by bottom-up methods

4. Consequent device performance limits

5. Epitaxial control of layer thickness

6. Zeolite pores as wires

6. Conclusions

Acknowledgments

References

Part II: Optoelectronics in the Nano Age

Ultrafast Nanophotonic Devices for Optical Interconnects

1. Introduction

2. Vertical-cavity surface-emitting lasers

2. Optical modes in conventional VCSELs

3. High-speed data transmission using VCSELs

4. Improved temperature stability of 850 nm VCSELs

5. Single-mode VCSELs for data transmission

6. Large-aperture single-mode VCSELs and coherent VCSEL arrays

7. Conclusions

Acknowledgments

References

Will Optical Communications Meet the Challenges of the Future?

1. Introduction

2. The road to modern optical transmission technology

3. Today’s optical communications - developments and limitations

3. A glance into the future

4. Conclusions

References

Optical Antennae for Optoelectronics: Impacts, Promises, and Limitations

1. Introduction

2. Source of weak coupling of photons to electronic transitions

3. Coupling enhancement between photons and electronic transitions

4. Practical applications

5. The difference between an optical antenna and a radio antenna

Acknowledgments

References

Spin Modulation: Teaching Lasers New Tricks

1. Introduction

2. Bandwidth enhancement in spin-lasers

3. Tailoring chirp in spin-lasers

4. Conclusions

Acknowledgments

References

Part III: Harvesting Energy From the Sun and the Environment

Silicon Photovoltaics: Accelerating to Grid Parity

1. Introduction

2. The case for PV

3. Basic c-Si PV cell and cost per Watt trends

4. The evolution of c-Si technology

5. Market implications of c-Si roadmap opportunities

Acknowledgments

References

Two- and Three-Dimensional Numerical Simulation of Advanced Silicon Solar Cells

1. Introduction

2. Selective emitter solar cells: Simulation setup and simulated devices

3. Selective emitter solar cell: Impact of LD and HD profiles

4. Selective emitter solar cell: Loss mechanism analysis

5. Rear point contact solar cells: Introduction

6. RPC solar cells: Simulation methodology and devices

7. RPC solar cells: Comparison between PERL and PERC solar cells

8. RPC solar cells: Back-contact diameter in PERL cells

9. Conclusions

References

Mechanical Energy Harvesting with Piezoelectric Nanostructures: Great Expectations for Autonomous Systems

1. Introduction

2. Mechanical energy harvesting using MEMS

3. Mechanical energy harvesting using piezoelectric nanostructures

4. Further improvements at the nanoscale

5. Towards completely autonomous systems: Multisource approach

6. Conclusions and future prospects

Acknowledgments

References

Charged Quantum Dots for High-Efficiency Photovoltaics and IR Sensing

1. Introduction

2. 3D nanoscale potential profile in Q-BIC structures

3. Photoelectron kinetics in Q-BIC structures

4. Q-BIC solar cells and IR detectors

5. Conclusions

Acknowledgments

References

Active Optomechanical Resonators

1. Introduction

2. Optical and mechanical mode design

3. Laser rate equations with mechanical degree of freedom

3. Dynamical analysis

4. Steady state

5. Conclusions

Acknowledgments

References

Part IV: Physics Frontiers

State of the Art and Prospects for Quantum Computing

1. A grand challenge for the millennium

2. The general ideas of quantum computing

3. ARDA experts’ panel roadmap

4. Experiments

5. Proposals: Quantum computing with …

6. Theory: Assumptions (axioms) underlying the threshold theorem

7. Precision of continuous quantities and the basic axiom

8. Precision of quantum amplitudes

9. The fundamental trouble with the error-correction theory

10. Mathematics and physical reality

11. More powerful in doing what?

12. Quantum computing as a sociological problem

Acknowledgments

References

Wireless, Implantable Neuroprostheses: Applying Advanced Technology to Untether the Mind

1. Introduction

2. Context and motivation

3. Listening to the brain: Sensing dynamic changes in neural activity

4. The write operation: Perturbing the brain with light

5. Summary

Acknowledgments

References

Correlated Electrons: A Platform for Solid State Devices

1. What is a correlated oxide?

2. Challenges in materials synthesis

3. High-speed electronic switches

4. Exploratory transistor devices

5. Conclusions

Acknowledgments

References

Graphene-Based Integrated Electronic, Photonic and Spintronic Circuit

1. Introduction

2. Electronic properties of gated graphene quantum dots

3. Graphene quantum dot as a single electron transistor

3. Optical properties of a graphene quantum dot

4. Magnetic properties of a graphene quantum dot

5. Opportunities and challenges in graphene integrated circuits

Acknowledgments

References

Luttinger Liquid Behavior of Long GaAs Quantum Wires

1. Introduction

2. Theory of conductivity in 1D wires

3. Fabrication of quantum wires in V-grooves

4. Experimental results and analysis for short V-groove quantum wires

5. Resistance dependence on T and length of longer V-groove quantum wires

6. Conclusions

Acknowledgments

References

Toward Spin Electronic Devices Based on Semiconductor Nanowires

1. Introduction

2. Spin injection into semiconductor nanowires

3. Sample preparation

4. Cobalt micromagnets

5. Nonlocal spin injection

6. Conclusions

Acknowledgments

References

An Alternative Path for the Fabrication of Self-Assembled III-Nitride Nanowires

1. Introduction

2. Non-lithographic fabrication

3. Structural characteristics

4. Optical characteristics

5. Conclusions

Acknowledgments

References

InAs Nanowires with Surface States as Building Blocks for Tube-Like Electrical Sensing Devices

1. Introduction

2. Charge carrier density in intrinsic and doped InAs nanowires

4. Conclusions

References

Lévy Flight of Photoexcited Minority Carriers in Moderately Doped Semiconductors: Theory and Observation

1. Introduction

2. Anomalous diffusion of the minority carriers

3. Single step probability distribution

4. Distribution along a band: Boundary effects

5. Experimental luminescence spectra and observation of the Lévy flight distribution of the minority carriers

6. A single big jump approximation for the truncated Lévy flight

7. Conclusions

Acknowledgments

References

Terahertz Plasma Oscillations in Field Effect Transistors: Main Ideas and Experimental Facts

1. Introduction

2. Plasma waves in the FET channel

3. Instability of the steady state with a dc current in FET

4. Detection of THz radiation by an FET

5. Studies of THz emission from FETs

6. Experimental studies of THz detection by FETs

7. Conclusions

Acknowledgments

References

Index

FUTURE TRENDS IN MICROELECTRONICS

Copyright © 2013 by John Wiley & Sons, Inc. All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.Published simultaneously in Canada.

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ISBN 978-1118-44216-6

Preface

S. Luryi

Dept. of Electrical and Computer Engineering State University of New York, Stony Brook, NY 11794-2350, U.S.A.

J. M. Xu and A. Zaslavsky

School of Engineering, Brown University, Providence, RI 02912, U.S.A.

This book is a brainchild of the seventh workshop in the Future Trends in Microelectronics series (FTM-7). The first of the FTM conferences, “Reflections on the Road to Nanotechnology”, had gathered in 1995 on Ile de Bendor, a beautiful little French Mediterranean island.1 The second FTM, “Off the Beaten Path”, took place in 1998 on a larger island in the same area, Ile des Embiez.2 Instead of going to a still larger island, the third FTM, “The Nano Millennium”, went back to its origins on Ile de Bendor in 2001.3 As if to compensate for small size of Bendor, the fourth FTM, “The Nano, the Giga, the Ultra, and the Bio”, took place on the biggest French Mediterranean island of them all, Corsica.4 Normally, the FTM workshops gather every three years; however, the FTM-4 was held one year ahead of the usual schedule, in the summer of 2003, as a one-time exception. Continuing its inexorable motion eastward, the fifth FTM workshop, “Up the Nano Creek”, had convened on Crete, Greece, in June of 2006.5 The inexorable motion was then interrupted to produce a semblance of a random walk in the Mediterranean and the FTM-6 “Unmapped Roads” went to the Italian island of Sardinia (June, 2009).6 The last FTM gathering, “Into the Cross Currents”, returned to our earlier venue on Corsica (June 2012).

The FTM workshops are relatively small gatherings (less than 100 people) by invitation only. If you, the reader, wish to be invited, please consider following a few simple steps outlined on the conference website. The FTM website at www.ece.sunysb.edu/~serge/FTM.html contains links to all past and planned workshops, their programs, publications, sponsors, and participants. Our attendees have been an illustrious lot. Suffice it to say that among FTM participants we find five Nobel laureates (Zhores Alferov, Herbert Kroemer, Horst Stormer, Klaus von Klitzing, and Harold Kroto) and countless others poised for a similar distinction. To be sure, high distinction is not a prerequisite for being invited to FTM, but the ability and desire to bring fresh ideas is. All participants of FTM-7 can be considered authors of this book, which in this sense is a collective treatise.

The main purpose of FTM workshops is to provide a forum for a free-spirited exchange of views, projections, and critiques of current and future directions, among the leading professionals in industry, academia, and government.

For better or worse our civilization is destined to be based on electronics. Ever since the invention of the transistor and especially after the advent of integrated circuits, semiconductor devices have kept expanding their role in our lives. Electronic circuits entertain us and keep track of our money, they fight our wars and decipher the secret codes of life, and one day, perhaps, they will relieve us from the burden of thinking and making responsible decisions. Inasmuch as that day has not yet arrived, we have to fend for ourselves. The key to success is to have a clear vision of where we are heading. In the blinding light of a bright future, the FTM community has remained mindful of the fact that what controlled the past will still control the future - the basic principles of science. Thus, the trendy, red-hot projections of any given epoch deserve and require critical scrutiny.

Some degree of stability is of importance in these turbulent times and should be welcome. Thus, although the very term “microelectronics” has been generally re-christened “nanoelectronics”, we have stuck to the original title of the FTM workshop series.

The present volume contains a number of original papers, some of which were presented at FTM-7 in oral sessions, other as posters. From the point of view of the program committee, there is no difference between these types of contributions in weight or importance. There was, however, a difference in style and focus – and that was intentionally imposed by the organizers. All speakers were asked to focus on the presenter’s views and projections of future directions, assessments or critiques of important new ideas/approaches, and not on their own achievements. This latter point is perhaps the most distinctive feature of FTM workshops. Indeed, we are asking scientists not to speak of their own work! This has proven to be successful, however, in eliciting powerful and frank exchange. The presenters are asked to be provocative and/or inspiring. Latest advances made and results obtained by the participants are to be presented in the form of posters and group discussions.

Each day of the workshop was concluded by an evening panel or poster session that attempted to further the debates on selected controversial issues connected to the theme of the day. Each such session was chaired by a moderator who invited two or three attendees of his or her choice to lead with a position statement, with all other attendees serving as panelists. The debate was forcefully moderated and irrelevant digressions cut off without mercy. Moderators were also assigned the hopeless task of forging a consensus on critical issues.

To accommodate these principles, the FTM takes a format that is less rigid than usual workshops to allow and encourage uninhibited exchanges and sometimes confrontations of different views. A central theme is designed together with the speakers for each day. Another traditional feature of FTM workshops is a highly informal vote by the participants on the relative importance of various fashionable current topics in modern electronics research. This tradition owes its origin to Horst Stormer, who composed the original set of questions and maintained the results over four conferences. These votes are perhaps too bold and irreverent for general publication, but they are carefully maintained and made available to every new generation of FTM participants. Another traditional vote concerned the best poster. The 2012 winning poster was “Mechanical energy harvesting with piezoelectric nanostructures: Great expectations for autonomous systems” by Gustavo Ardila.

A joyful tradition of FTM meetings is the settling of scientific bets, a custom that dates back to the 1998 wager between Nikolai Ledentsov (pro) and Horst Stormer (con) about the putative future dominance of quantum dot-based lasers – a bet that Horst collected in 2004, at FTM-4. Another risky bet on the future dominance of SOI technology is to be adjudicated at a future (2015) workshop. The precise statement of this “good” bet (worth a six-magnum case of very good champagne) is: by 2015, SOI will cover more than 35% of the CMOS market including memories by value. This bet, proposed by Sorin Cristoloveanu, attracted three cons – Detlev Grützmacher, Dimitris Ioannou, and Enrico Sangiorgi – who will have to divide the spoils, should SOI fail to reach the mark. Several “bad” (penniless) bets that were supposed to be resolved at FTM-7 were put off as premature by the principals. Hopefully, by 2015 it will become clear whether or not “10% of all man-produced light will be white LED” (Michael Shur), “we shall have hi-fi real-time pocket translators” (Hiroshi Iwai), “most cars will have IP addresses” (Jimmy Xu), or “the Si industry will no longer be recognizable and there will be (essentially) no further improvement in devices” (Paul Solomon).

Not every contribution presented at FTM-7 has made it into this book (not for the lack of persistence by the editors). Perhaps most sorely we miss the exciting contribution by David Miller of Stanford University, entitled “The heat death of information processing and why interconnects matter more than logic”, in which he illustrated how the energy required by data communication is imposing severe limits on overall information processing, with the demand for communications bandwidth increasing a hundredfold every decade. As a result, he posited very low energy optoelectronics densely integrated with logic as a way of allowing the continued scaling of information processing systems. Abstracts of his and all other presentations can be found on the program webpage, http://www.ee.sunysb.edu/~serge/ARW-7/program.html

The FTM meetings are known for the professional critiques – or even demolitions – of fashionable trends, that some may characterize as hype. The previous workshops had witnessed powerful assaults on quantum computing, molecular electronics, and spintronics. This time Michel Dyakonov offered another thorough and conclusive update on quantum computing. It seems that by now most of the hype associated with some of these trends has dissipated and perhaps we can take some credit for the more balanced outlook that has emerged since.

We have grouped all contributions into four chapters: one dealing with transistors and CMOS or CMOS-compatible technology, another with photonics and lasers, and still another with solar cell and energy harvesting. The last chapter collected the contributions focused on fundamental physics and other, less technological subjects. The breakdown could not be uniquely defined, because some papers fit two or even three categories!

To produce a coherent collective treatise out of all of this, the interaction between FTM participants had begun well before their gathering at the workshop. All the proposed presentations were posted on the web in advance and could be subject to change up to the last minute to take into account peer criticism and suggestions. After the workshop is over, these materials (not all of which have made it into this book) remain on the web indefinitely, and the reader can peruse them starting at the www.ece.sunysb.edu/~serge/FTM.html home page.

Acknowledgments

The 2012 FTM workshop on Corsica and therefore this book were possible owing to support from:

US National Science Foundation

U.S. Department of Defense: ARO

U.S. DoD European offices: EOARD, ONR–Global

Industry: SAIT, Samsung Electronics Co.

Academia: SUNY–Stony Brook, Brown University.

On behalf of all workshop attendees sincere gratitude is expressed to the above organizations for their generous support and especially to the following individuals whose initiative was indispensable: William Clark, John Gonglewski, Kinam Kim, Mark Pinto, Shawn Thorne, Robert True, and John Zavada.

Finally, the organizers wish to thank all of the contributors to this volume and all the attendees for making the workshop a rousing success.

References

1. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: Reflections on the Road to Nanotechnology, NATO ASI Series E Vol. 323, Dordrecht: Kluwer Academic, 1996.

2. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: The Road Ahead, New York: Wiley Interscience, 1999.

3. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: The Nano Millennium, New York: Wiley Interscience/IEEE Press, 2002.

4. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: The Nano, The Giga, and The Ultra, New York: Wiley Interscience/IEEE Press, 2004.

5. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: Up the Nano Creek, Hoboken, NJ: Wiley Interscience/IEEE Press, 2007.

6. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: From Nanophotonics to Sensors to Energy, Hoboken, NJ: Wiley Interscience/IEEE Press, 2010.

Part I

Innovations in Electronics and Systems

I. Innovations in Electronics and Systems

The incredibly powerful silicon electronics is still full of steam, charging ahead despite the putatively insurmountable barriers and walls (of thermal, power, wiring, and scaling, for example). Equally evident is that the challenges ahead are real, getting greater, and often without a clear answer. One example is transition to EUV lithography, discussed in the chapter by Banine. What are the biggest challenges anticipated and the biggest changes assumed in the existing roadmap? If science is not (yet) the ultimate limit to nanoelectronics, is it manufacturability, discussed in the chapter by Kelly? What are the most desired innovations, and the most disruptive, interesting, and controversial directions? While the drive for ever greater device performance – discussed in a number of chapters devoted to novel memory and logic devices – is becoming prohibitively costly, could the advances in systems and integrated functionalities be sufficiently rewarding to justify and become the next driving force? These questions are addressed in Part I of this book, which opens with an insightful and comprehensive discussion of technology innovation by Kim and Chung, from the innovation powerhouse of Samsung Electronics.

Contributors

1.1 K. Kim and U-I. Chung

1.2 F. Balestra

1.3 N. Rodriguez, F. Gamiz, and S. Cristoloveanu

1.4 D. E. Ioannou, Z. Chbili, A. Z. Badwan, Q. Li, Y. Yang, and A. A. Salman

1.5 J. Wan, S. Cristoloveanu, S. T. Le, A. Zaslavsky, C. Le Royer, S. A. Dayeh, D. E. Perea, and S. T. Picraux

1.6 A. Makarov, V. Sverdlov, and S. Selberherr

1.7 C.-M. Zetterling

1.8 J. Schmitz

1.9 V. Y. Banine

1.10 M. J. Kelly

Technology Innovation, Reshaping the Microelectronics Industry

Kinam Kim and U-In Chung

Samsung Advanced Institute of Technology, Samsung Electronics Co. Ltd. Giheung, Gyonggi-do, South Korea

1. Introduction

The remarkable evolution of electronics was enabled by the rapidly advancing silicon technology. The performance of such devices as CPUs and memories has improved tremendously over the past 20 years: CPUs improved by a factor of 2,400, DRAM by a factor of 1,000 and NAND Flash by a factor of 32,000. Mobile network speed has also increased by a factor of 840, stimulated by an increased usage of smartphones and tablets, which have grown by 58%1 and 260%2 in 2011, respectively. Furthermore, Internet communication traffic is anticipated to increase by 32% annually, with the traffic reaching an order of zeta (1021) bytes by 2015.3

These performance improvements have been made possible by silicon technology downscaling, which is nearing the 20 nm node and will soon reach 10 nm. Novel fabrication techniques, structures and materials will be required to continue scaling beyond 10 nm to satisfy the data handling, processing and storage requirements of the future.

Future device development will be constrained by power consumption, in addition to the traditional scaling issues, since faster and higher data handling and processing will unavoidably require a lot of power. For instance, 1.1 petaflop (1015) computing in 20084 consumed 2.3 MW power for its operation, so an exascale (1018) system might dissipate an estimated 2.3 GW, roughly equivalent to the electricity produced by two nuclear power plants. Most of this energy is lost in the inefficient metal interconnects, which could be reduced by combining photonics with Si technologies. This silicon-photonics convergence will create new applications and markets in the future.

Furthermore, silicon technology is bringing innovation to new areas, such as energy, health, and medical applications. Examples of this are ultrafast DNA sequencing, extremely compact and efficient medical imaging devices, and low-cost energy-efficient lighting, among others. These applications, fueled by Si technologies, could eventually take up a major portion of the semiconductor market in the next decade.

2. Mainstream silicon technology: Memory

• Towards sub-20 nm DRAM

DRAM density has doubled every 18 months through scaling of the critical dimensions, approaching the 20 nm node today, as shown in Fig. 1, Major challenges to downscaling to the sub-10 nm regime will require device innovations in cell storage capacitors, cell array transistors (CATs) and patterning processes.5

Figure 1. DRAM technology roadmap of ITRS and top DRAM supplier.

The minimum cell capacitance must be maintained to provide an adequate signal for sensing and to meet retention time specifications.6 In order to maintain the cell capacitance, as DRAM downscaled from 90 nm to 20 nm, the capacitor structure has been changed from a simple 3D cylindrical shape to an extremely high aspect ratio (AR) supported cylinder or pillar structure, as shown in Fig. 2. For sub-10 nm DRAMs, structural innovation may not help any longer due to physical limitations in accommodating complex 3D structures. At sub-10 nm nodes, the distance between electrodes becomes ~10 nm or less, which in turn requires the physical thickness of the storage electrodes and the dielectrics to be thinner than 5 nm or less. These requirements will be very difficult to meet. However, the limitation of cell capacitance can be compensated by the technological innovation in CAT with extremely low leakage currents and/or array architecture and its integration process to provide high sensing signals.

Figure 2. Key technology evolution of DRAM from 90 nm to sub-20 nm: lithography and critical size (top), cell capacitor (middle), and cell array transistor (bottom).

From a device point of view, requirements related to the retention limit can be overcome by suppressing the storage node leakage current ILEAK. The data retention time tRE is fundamentally determined by the amount of the stored charge and the time-dependent charge loss at the storage node.7 The sensing voltage ΔVBL is as follows:

(1)

(2)

As shown in Eq. (2), the leakage current ILEAK must be suppressed as much as possible (to less than sub-fA/cell) to ensure good data retention characteristics. The leakage ILEAK originates mainly from the GIDL, subthreshold current, and junction leakage of the CAT. In recent years, CAT structures have successfully evolved from a planar-channel to a recessed-channel (RCAT), and later to a metal buried-gate (BCAT) structure that eventually will evolve to a vertical-channel (VCAT) structure satisfying the ION/ILEAK ~1010 ratio requirement. Figure 2 shows the evolution of the cell array transistor through the years.

The sensing signal voltage ΔVBL can also be improved by reducing CBL. Vertical scaling of the bit line (BL) electrodes with lower resistivity metal and gap filling with lower-κ dielectrics between BLs are the key points in reducing CBL and thereby enhancing ΔVBL.

Demands for higher speed devices with reduced power consumption require more stringent processes and technological breakthroughs in transistors. Aggressive scaling employing higher-κ gate oxide with multi-thickness, ultra-shallow junctions with carefully controlled thermal activation, as well as novel mobility-boosting technologies based on strain effects are possible candidates for the enhancement of device performance and power reduction.

With the optimization of the 3D cell storage capacitor and array transistor structures, DRAM is anticipated to downscale to the sub-10nm regime. Nevertheless, in the future, patterning technology, e.g. lithography and etching, will become critical. Currently, the major concern is the productivity of such technologies: i.e. extreme ultraviolet (EUV) and/or double patterning lithography, and high aspect ratio capacitor hole etching. The slow progress of EUVL technology will result in the need for expensive double or quadruple patterning technologies (DPT or QPT) for several critical layers at the 22 nm node. The rapid increase in fabrication costs, as well as overlay and uniformity issues are becoming major challenges due to the drastic increase in the number of process steps.

• Beyond sub-20 nm NAND flash

The conventional floating-gate (FG) NAND flash cell technology is currently at the 20 nm node.8 Moreover, sub-20nm cells using QPT have also been demonstrated9 using the word line (WL) air-gap technology in order to overcome coupling interference. However, as device technology enters the sub-20 nm region, cell-to-cell coupling interference, the numbers of stored electrons, WL-to-WL breakdown, endurance and data retention are becoming major challenges.10 Although circuit technologies including parallel programming, shadow programming and extended ECC (error correcting circuit) were successful in overcoming the cell-to-cell coupling down to the 20 nm node, they would not be effective in overcoming issues for beyond the 20 nm node planar NAND flash because coupling interference ratio is inversely proportional to the design rule for planar structures. Thus, as the design rule decreases, the coupling ratio will further increase, reaching the allowed design limit, which is about 5 at around 20 nm as shown in Fig. 3.

Figure 3. Gate-all-around charge trap flash (CTF) structure (bottom left) and 3D VNAND with gate-all-around CTF structure (top left). The coupling interference ratio of 3D VNAND is much lower than in planar devices. The coupling interference ratio defines the charge build-up in cell while an adjacent cell is programming, and should not exceed the allowed design limit of ~ 5 (dashed horizontal line).

However, a 3D NAND flash at the 10 nm node can be designed in such a way that the coupling interference ratio is at the same level as that of a 60 nm planar cell. The coupling interference ratio of the 3D vertical NAND (VNAND) remains far below the critical design limit even beyond the sub-10 nm region, as shown in Fig. 3. This is because the bit line coupling interference is almost eliminated by the gate-all-around (GAA) structure, and the WL-to-WL coupling interference can be reduced by the increased spacing between WLs.

Among several proposed 3D vertical structures, the terabit CAT (TCAT) is thought to be the most promising. It is based on a damascened metal gate and a TANOS (TiN-AlO-nitride-oxide-Si) cell. The metal gate in this structure could have a wide programming window because TANOS has a better erase speed than SONOS (Si-oxide-nitride-oxide-Si).11 Furthermore, by shrinking the diameter of the channel hole, erase speed can be further improved as the electric field in the tunnel oxide is enhanced. The TCAT erase scheme is the same as that of planar cells, so that it can be compatible with the conventional NAND flash architecture. Furthermore, it has a better array distribution uniformity by a factor of two and ten times the endurance of the 20 nm node planar technology.5

Further research will be necessary in order to achieve the required read margin and write speeds, which could be negatively affected by a low mobility and high leakage of channel poly-Si. To reduce the leakage current, the poly-Si has to be thin enough to be fully depleted, and its grain size has to be enlarged in order for its performance to be comparable to that of the single-crystal Si. Process technologies, such as high aspect ratio channel-hole formation, bowing and leaning free stacks, will also require further research.

• STT-MRAM as a post-DRAM technology

As the push for smaller DRAM cells faces formidable technological and economical challenges, a number of alternative post-DRAM devices are under consideration. Because of the severe charge leakage for downscaled storage elements, non-charge-based memory devices seem quite promising. One such device is the spin transfer torque magnetoresistive random access memory (STT-MRAM), which has a high operation speed, superior endurance and process compatibility with existing Si technology.12,13,14 The STT-MRAM technology utilizes magnetic tunnel junction (MTJ) tunneling for resistive storage as shown in Fig. 4, where MgO is widely used as the magnetic tunnel barrier. It can reach a similar area density as DRAM, since a cell consists of a single transistor as a selection device and a single MTJ as a storage element.

Figure 4. STT-MRAM structure where the magnetic tunnel junction (MTJ) exhibits two different resistance states depending on the relative spin orientation of the MTJ layers.

Figure 5. Current required to switch the spin state of the MTJ cell as a function of the technology node. Lines with symbols show the switching currents depending on the critical current density JC required to switch the state of the MTJ cell. Solid lines show the available transistor current drive ION at each technology node.

Figure 6. Two MTJ cell structures with equivalent thermal noise: (left) conventional planar MTJ cell with a long 3F footprint, where F is the minimum feature size; (right) three-dimensional MTJ cell structure with 1F footprint that is robust against thermal noise because of its larger free-layer ratio.

The critical current density JC required to switch the magnetic moment of the in-plane free layer is given by the following equation:

(3)

where α, η, HK, V, and MS are the magnetic damping constant, spin torque efficiency, magnetic anisotropy constant, volume of the free layer, and the saturation magnetization, respectively. The πMS2V term in Eq. (3) arises from the surface demagnetization energy due to the out-of-plane precession of the in-plane magnetization during the switching. Since this term is absent in the perpendicular magnetic structure, switching current reduction will be possible by using materials with perpendicular magnetic anisotropy.

To further reduce the critical current density, a higher spin torque efficiency and a smaller damping constant for the perpendicular free layer are needed. However, reduction of HKV will cause data retention problems. As the small storage volume may be vulnerable to random thermal noise, the usage of perpendicular magnetic materials with high crystalline or interfacial anisotropy can improve the data retention.16,17,18 Otherwise, for in-plane magnetic anisotropy, thermal stability can be ensured through a 3D MTJ cell structure, which retains a large free-layer volume without an increased cell footprint by folding the free layer to a special geometry, as shown in Fig. 6.

The STT-MRAM will be the most promising candidate around the 12 nm technology node, or about 2018. In addition to reducing the switching current of the MTJs, etching damage and thermal stability of the MgO tunnel barrier also need to be improved in order to obtain adequate retention characteristics.

• ReRAM as a post-NAND technology

Post-NAND devices are also being studied; one proposed technology is the resistive RAM (ReRAM) that makes use of resistance switching phenomena with structural simplicity. ReRAM is characterized by a resistive material acting as the memory element with a control element acting as the switch. Among the currently known material systems, tantalum oxide is the most promising candidate for the future nonvolatile ReRAM. In a Ta2O5/TaOx bi-layer structure, 1012 cycle endurance and ten-year retention time with fast program and erase pulses on the order of ~10 ns have been reported.19

The resistive switching characteristics and structure of this device are shown in Fig. 7. The resistance switching in this type of ReRAM occurs in the Ta2O5 layer via a redox reaction. But, the superior cell performance comes from the presence of a TaOx layer that plays two key roles. First, it is able to hold a high density of oxygen ions as an oxygen reservoir that mitigates the oxygen ion depletion that causes reset-switching failures. Second, the TaOx layer limits the set switching with a finite current compliance, thereby preventing overshoot and hard breakdown during the set switching.

Figure 7. Resistive switching characteristics and structure of the Ta2O5/TaOx device: (a) typical bipolar dc I–V switching operation of a 30 nm cell (SEM in inset) from high to low resistance state (HRS to LRS); (b) schematic of the TaOx device consisting of a thin Ta2O5 insulating layer and a TaOx base layer. Resistive switching is due to the movement of internal oxygen ions or vacancies.

ReRAM devices can be operated in the metal-insulator-metal (MIM) configuration that can be integrated into a crossbar array. In this case, the device footprint can be reduced to 4F2; and if stacked into multi-layers, the feature size becomes (4/n)F2, where n is the number of the stacked layers, as shown in Fig. 8. However, the crossbar structure always has a signal disturbance problem due to unwanted stray currents from the neighboring cross-points. Thus, it needs a proper selection device, such as a diode or a threshold switch, serially connected with MIM storage element. As of this moment, it is critical to find an appropriate and reliable selection device and to integrate it with the ReRAM material in a crossbar structure.

Figure 8. Cross-point ReRAM structure, where a resistive material acts as the memory element.

Another feasible approach is a vertical ReRAM (VReRAM) structure (equivalent to 1T-nR structure), which has a similar layout to the 3D vertical NAND of Fig. 3. In the 1T-nR, the selection device must be integrated in the ReRAM cell because multiple cells are connected to one transistor. Because the role of the selection device is to filter out the stray current from the n2 ReRAM cells, the specification of selection device for the 1T-nR structure is less tight than that of the crossbar structure. However, in the VReRAM structure, the hole sizes must be to be large enough to accommodate ReRAM cell materials, such as selection, resistive switching and base materials as well as the top electrode. This may keep VReRAM from further scaling.

When considering the technological issues of VReRAM and crossbar ReRAM, further research on self-rectifying ReRAM materials that would not require a selection device is urgently needed.

3. Mainstream silicon technology: Logic

In order to improve the performance of Si CMOS, logic devices have been continuously downscaled and integrated over the past 40 years, as shown in Fig. 9.20,21 However, as logic device size downscales into the nanometer regime, significant innovation in device structures and new materials have to be introduced in order to maintain the traditional rate of performance enhancement of past decades: e.g. Cu/low-κ dielectric at the 120 nm technology node; SiGe source/drain for the 65 nm node; and metal electrode/high-κ dielectric gate stacks replacing poly-Si/SiO2 gate stacks at the 45 nm node.

Figure 9. Logic device downscaling deep into the nanometer regime, highlighting new device structures and materials, such as metal electrode/high-κ dielectric gate stacks replacing poly-Si/SiO2 gate stacks at 45 nm; high-κ/metal gate at 32 through 20 nm; and fin-FETs at the 14 nm node.

The conventional planar logic structure will continue to scale down to the 20 nm node through optimizing the HK/MG (high-κ/metal gate) technology, introduced at the 32 nm node. However, below 20 nm, equivalent oxide thickness (EOT) will decrease sharply because in order to suppress the short channel effects (SCEs), channel doping concentration has to be increased rapidly. The EOT constraints can be relaxed if a multi-gate structure or fin-FET is used to replace planar layout.

Recently, due to the rapid growth of mobile applications, low power consumption has joined speed and performance as a key metric. Power consumption P in logic devices is dominated by VDD as follows:

(4)

where COX is the capacitance, VDD is the input voltage, IOFF is the off current and f is the frequency. There are three approaches for reducing VDD and IOFF for low power mobile applications: (i) alternative transistor architectures, such as 3D or GAA layout for better electrostatic control; (ii) high mobility materials for alternative channels; and (iii) alternative devices with low subthreshold swing SS < 60 mV/dec.

Of the three approaches, 3D devices with various performance boosting schemes are the furthest along, with fin-FETs being one of the best candidates for the next generation logic.

High mobility III-V or Ge channel materials are one of the promising directions for performance improvement as well as reducing power consumption. Even though there are many challenges to the 10 nm technology node or beyond, the improvement of gate stack/channel interface properties and introduction of heterogeneous process integration for new channel materials with higher electron and hole mobility should enable aggressive VDD scaling, thereby reducing power consumption.

One of the options to overcome thermal limit of sub-threshold slope below 60 mV/dec in a conventional CMOS is the tunneling FET (TFET). Tunneling FETs have been proposed for low VDD operation below 0.5 V,22 and would greatly benefit from low (effective) band gap energy, increasing the probability for tunneling. As a result, III-V or SiGe/Ge heterojunctions will possibly be the most effective materials for TFETs.

• Fin-FET devices

Figure 10. Drain-induced barrier lowering (DIBL) vs. gate length LG of different transistor structures (fin-FET, FD-SOI FET, and bulk FET), calculated with the MASTAR simulator.24

The influence of the drain electric field on the channel region, which is the physical mechanism underpinning SCEs, can be understood through the “natural length” of the device, expressed as λ in the following equation:23

(5)

where εSi, εOX, tSi, tOX are the permittivities and thicknesses of silicon and oxide, respectively. By moving from bulk to the fin-FET structure, tSi can be markedly reduced. Fin-FETs will be the best choice for minimizing the natural length.

Figure 11. Volume inversion effect and mobility vs. fin thickness: (a) electron concentration increases as the depth in silicon decreases; (b) volume inversion occurs only at a certain fin thickness (represented as silicon film thickness in the graph).

Tri-gated fin-FETs exhibit corner effects. Due to the higher electric field at the fin corner, strong inversion occurs faster than at the fin side. As a result, higher carrier concentration can be achieved at a lower VT. This comer effect improves the performance at the top of the fin, yielding an improved overall performance.

The third advantage of fin-FETs derives from their immunity to random dopant fluctuations, because the fin-FET channel can be nearly undoped.27

However, going from planar FETs to fin-FETs also runs into challenges. A 3D fin-FET is prone to severe variability, in particular work function variability owing to the metal grain boundaries and thickness variations. Also, the sidewall quality of the fin-FET, side orientation and degree of top corner rounding, as well as the uniformity of the interface layer thickness around the fin structure will become variability issues from a structural point of view.

Another challenge faced by fin-FETs is source/drain resistance. Normally, as the fin size shrinks, source/drain resistance increases rapidly due to reduced contact area. So the performance bottleneck in fin-FET scaling comes mainly from the source/drain resistance, as shown in Fig. 12.

Figure 12. Parasitic resistance. (a) Resistance vs. technology node. As the technology node scales down, parasitic resistances (source/drain resistance, gate resistance) increase, while channel resistance decreases because of the increase in channel mobility.28 (b) Contribution of the various resistance components to the total.29

The third challenge is the lack of multi-VT operation. As fin size decreases, the fin-FET VT can be tuned only slightly by “halo dopant effect”, which means more doping near the source and drain to reduce the size of the depletion regions in the vicinity of these junctions:

(6)

where φMS is the work function of the gate, φF is the difference between EF and the intrinsic Fermi level, QD is the depletion charge, QSS is the surface charge, COX is the oxide capacitance, WFIN is the width of the fin, and NA is the doping density. As shown by Eq. (6), the threshold voltage and charge depletion in fin-FETs are defined by the fin width.

If the fin width is small, the QD value becomes small, so the sensitivity of VT to channel doping is reduced. Therefore, overall VT is mainly determined by the metal workfunction and is difficult to control compared to planar devices. Hence, other approaches for achieving multi-VT operation are needed, such as multi-fin-size structures and multi-workfunction material processes.

Even though fin-FETs will be extended to the 10 nm node, new materials and new structures may be necessary for sub-10 nm nodes.

• Advanced channel materials for logic

As previously mentioned, high mobility III–V or Ge channel materials are promising candidates for improving the performance and reducing power consumption. New channel materials that enhance the electron and hole mobilities enable power reduction by aggressively scaling the VDD.

Many III-V compound semiconductors have lower electron effective masses than Si, leading to a higher injection velocity into the channel.30 Thus, III-V channel transistors can have higher ION than Si NMOS at lower operating voltages.31 There has been rapid progress in III-V channel transistors and, recently, InGaAs quantum well fin-FET32 and a GAA structure using the same materials33 have shown promising results for logic applications.

For III-V materials to be used with the silicon platform, defect-free III-V on Si is necessary, which is extremely difficult to achieve due to the lattice mismatch. One possible approach is the selective area growth (SAG) of lattice-mismatched materials inside trenches by MOCVD. Threading dislocations are trapped at the bottom of the trench, yielding a high-quality top layer, as shown in Fig. 13.

Figure 13. Cross-sectional (a) SEM and (b) TEM images of ~1.9 μm thick epitaxial InP layer grown on a patterned Si (001) wafer. As can be seen in the TEM image, defect-free InP crystal can be grown in the Si hole pattern.

The second technical issue comes from the lack of III-V PMOS; but there has been recent interest in group III-Sb materials, such as InGaSb, for PMOS applications. Additionally, side-by-side integration of III-V NMOS and PMOS transistors on a Si substrate needs to be developed. Another approach for the replacement of the PMOS is using a Ge channel.

The preparation of a hybrid substrate for NMOS and PMOS transistors is a major challenge. Selective area growth of III-V for NMOS and III-Sb/Ge for PMOS could be a feasible solution – a possible structure is shown in Fig. 14.

Figure 14. III-V/Ge hybrid CMOS on Si.

• Low subthreshold swing devices

To achieve a high ION at low VDD, subthreshold swing (SS) should also be reduced, which is very critical for low power consumption. Tunneling FETs (TFETs) can be a possible solution for low SS, especially tunneling FET based on III-V materials.22 The subthreshold swing of a TFET can be lower than 60 mV/dec because its operation mechanism is band to band tunneling at a reverse-biased source-channel pn junction. Figure 15(a) illustrates TFET operation in terms of band diagram modifications by VG: the tunneling length decreases with VG-induced band lowering, which leads to higher tunneling current. The main issue with TFETs is how to increase the ION to > 100 μA/μm while retaining low SS.

Figure 15. (a) Principles of TFET operation, with yellow arrows indicating interband tunneling. Gate bias enhances the tunneling probability by lowering the barrier, (b) Bird’s eye view of the n-type GAA nanowire TFET. (c) Cross sectional view of n-type GAA nanowire TFET.

In order to increase ION, recent TFET research has focused on III-V materials because a narrow band gap is preferred for increasing the tunneling probability. Also, to increase the gate controllability and ION, GAA nanowire TFETs have attracted much attention. This structure allows a better control of SS and IOFF, which should be as low as possible.34 Schematic illustration of a GAA n-type nanowire TFET is shown in Fig. 15(b) and (c).

Another advanced material, graphene, is also being considered as a prime candidate as a FET channel material because of its high mobility.35 However, graphene FETs suffer from a large IOFF due to a lack of bandgap, which is key in turning the device off and on by creating an electrostatic potential between the source and the drain. Therefore, in order for graphene to replace silicon in a transistor, generating a bandgap in graphene has been a top priority.36,37,38 So far, there has been a trade-off between the band gap and the high mobility; thus, generating a bandgap without sacrificing the mobility remains the greatest challenge for graphene.

Recently, two new structures have been suggested to resolve this issue: graphene barristor39 and graphene tunneling transistor.40 In the former structure, current is controlled by modulating the Schottky barrier between graphene and the semiconductor, as shown in Figs. 16(b) and (c). In the latter structure, current is controlled by modulating the Fowler-Nordheim tunneling barrier between the graphene and the insulator, as shown in Figs. 16(e) and (f). Both structures rely on a unique property of graphene: workfunction modulation. Since graphene has a low density of states near the Dirac point, its workfunction can be modulated by changing the carrier density. Interestingly, when Schottky (tunneling) barrier is formed between graphene and the semiconductor (insulator), the barrier height can be changed by the work function modulation, since the barrier height is determined by the difference between the EF of graphene and conduction band minimum of semiconductor (insulator). For instance, if graphene’s workfunction increases by, say, 0.35 eV, the Schottky barrier reduces by the same amount to align the Fermi levels on both sides (compare Figs. 16(b) and (c)). The off-state achieved this way could eventually enable graphene logic applications.

Figure 16. Barrier modulation of graphene barristor39 and graphene tunneling transistor.40 Graphene barrister: (a) 3D structure; (b) ON state, showing Schottky barrier between graphene and silicon determined by the difference between graphene EF and silicon EC; (c) OFF state. Graphene tunneling transistor: (d) schematic; (e) ON state, with tunneling barrier height set by difference between graphene EF and EC of barrier insulator (Fowler-Nordheim tunneling assumed); conduction band minimum of tunneling insulator; (f) OFF state. Tunneling barrier is increased by the modulated workfunction of graphene.40

While MOSFET-type transistor structures are not an obvious fit for graphene, graphene barristor or tunneling transistor could be candidates for logic applications. But compared to III-V materials, graphene is still in its early stages for logic and requires further development, especially with regard to low-defect graphene growth and process integration on silicon.

4. Emerging computing architectures

The fundamental underlying design of general-purpose computing systems has remained unchanged for decades. However, with the introduction of many-core CPUs and new memory devices, significant redesign of computing architecture is inevitable. In order to reduce power consumption, current systems have to be designed in such a way as to minimize wasted cycles and bandwidth for nonessential computing and data movement.

The future may bring powerful computing architectures that mimic the brain, more efficient and capable of processing adaptive tasks. Other computing architectures will become possible thanks to the rapid evolution of emerging memories, such as MRAM and ReRAM. These memories, in combination with logic devices, would allow flexibility in circuit design and faster hardware revisions or updates, which would lead to a reduced hardware development time.

• Neuromorphic devices

Neuromorphic systems refer to analog/digital VLSI and software programs that mimic neural systems for perception, motor control, sensory processing, and decision making. Neuromorphic VLSI chips mostly use an integrate-and-fire (IF) spiking neuron model. Neuromorphic IF neurons compute from inputs in the subthreshold region (on the order of mV) and emit sparse high-voltage pulses (on the order of volts) for cell-to-cell communication, so that low-power consumption can be achieved. An example of a neuromorphic visual system is shown in Fig. 17.

Figure 17. Neuromorphic visual system: (left) biological, (right) electronic.

However, subthreshold CMOS circuits are plagued by unavoidable transistor VT variability due to imperfections and temperature variations in the fabrication process.41 Typical CMOS VT may vary by ±20 mV, causing large errors in subthreshold computation of silicon neurons. Solving this mismatch problem or detouring around it will be a major challenge for achieving massively integrated silicon neuron chips.

Wiring large numbers of neurons on a 2D wafer faces higher constraints in comparison to 3D connections of a real brain. It is inefficient to assign independent paths to all connection; e.g., an N neuron chip requires N2 wires to be fully connected. To resolve this problem, most neuromorphic chips adopt a digital bus mechanism, such as address event representation (AER) based on an asynchronous digital pulse-based encoding method.42 Its performance is dependent on the clock speed of connected digital blocks.

Another challenge is the implementation of a synapse and its updating. In terms of neuroscience, a synapse is a biological structure that passes an electrical or chemical signal from one neuron to another. The synaptic weight can change over time, so that our brain learns. A fully-interconnected network with N neurons also needs N2 synapses. Therefore, implementation of synapses is more critical for a chip than of neurons. Since many transistors are necessary to form a digital synapse, some researchers are considering the use of memristor devices.43

In the future, neuromorphic chip industry is expected to start growing in low-power and high-performance sensory preprocessors, and will expand to include cognitive processors that can be used by robots or artificially intelligent computers.

• Real-time hybrid reconfigurable logic (RHRL)

Reconfigurable logic (RL) can provide significant flexibility in circuit design, enabling hardware revisions or updates, as well as reduction of hardware development times, all of which is very attractive to many hardware and software engineers. Reconfigurable logic can also reduce the software overhead in the processing units through proper hardware organization. However, device footprint, power consumption and slow operating speeds may outweigh the above benefits. As a result, RL is barely being noticeable in the current logic market, where the major players are ASICs or ASSPs.

A typical RL chip, for instance, is the Virtex-7 from Xilinx with about 2 million logic cells. However, due to heavy area/power/performance overheads, its applications have been limited to software field tests and/or low production volume niches. The disadvantage of FPGA is that it takes over a second to access the operational codes stored in an external flash or ROM. This hinders real-time reconfigurability.

To increase the programming speed, RL architectures with embedded nonvolatile memories are being considered, i.e. real-time hybrid reconfigurable logic (RHRL). The RHRL makes use of high-speed, high-density nonvolatile memory, such as ReRAM and MRAM, that can be integrated with standard CMOS processes. Figure 18(b) shows an example of an RHRL circuit that dispenses with the bulky look-up tables and interconnect circuits needed in SRAM-based reconfigurable logic, shown in Fig. 18(a).

Figure 18. Examples of reconfigurable logic, (a) SRAM-based reconfigurable logic, requiring bulky SRAM-based look-up tables and interconnect circuits, as well as external ROM or flash memory, (b) MRAM- or ReRAM-based real-time hybrid reconfigurable logic (RHRL) with embedded memory, which simplifies the system.

By using these nonvolatile memories, additional communication with an external flash or ROM becomes unnecessary, so that RHRL accesses the new operating codes within 1~2 clock cycles, i.e. within 10 ns. A second advantage of RHRL comes from low standby current. Standby power consumption can be lowered to almost a tenth of the conventional RL due to the nonvolatile nature of the memories. Finally, RHRL logic chip area, consisting of ReRAM and MRAM, can be reduced 2~3 times compared to conventional RL. Due to these benefits, RHRL using MRAM or ReRAM as logic setters should allow much wider functionality and will likely find usage in multi-standard applications, e.g. radio-frequency communications in 3G, 4G, Wi-Fi, etc.

5. Silicon technology in the field of energy

Considering how energy has enriched our lives, it is no surprise that energy efficiency is a major topic of interest. The world’s primary energy consumption is projected to grow by 1.6% per annum, reaching about 17 billion tons of equivalent oil by 2030.44 Electricity will comprise roughly 40% of this energy, which requires almost doubling the electricity generation capability in the next 20 years. This is not an easy task, especially given environmental concerns, radiation safety, etc. Thus, the current interest in renewable energy is well justified. A renewable energy platform that is derived from silicon technologies is the solar cell, which makes use of a perpetual resource to obtain electricity. Furthermore, silicon technology is bringing innovation to power electronics, which is the key component in renewable energy systems.

However, more important than energy generation is energy saving. The U.S. Energy Information Administration estimated that in 2010, about 13% of the total U.S. electricity was spent in residential and commercial sectors. As a drastic measure, countries are banning inefficient but inexpensive incandescent lighting, which is accelerating the adoption of solid-state lighting based on light emitting diodes (LEDs). Current solid-state lighting is still expensive compared to fluorescent lighting, but it will soon become competitive as the LED technology evolves, in part aided by silicon technology.

• Solar cells

The average growth rate of the solar cell industry has been over 25% in recent years. Currently, crystalline Si solar cells hold about 90% of the market, with the rest divided by thin film technologies based on CdTe, CIGS (CuIn1-xGaxSe2), or amorphous Si.

For crystalline Si solar cells, due to their structural simplicity, screen printing has been adopted and has become industry standard with its fair efficiency and simple processing, enabling the facility manufacturers to provide turn-key systems. The current cell and module efficiencies are 16–21% and 13–18%, respectively. The highest demonstrated cell efficiency is 24.7% with a passivated emitter rear local (PERL) contact structure by the University of New South Wales,45 but PERL structures have not been commercialized to date due to the high wafer and process cost. In the commercial arena, interdigitated back contact (IBC) technology has attracted much research effort worldwide, demonstrating a best cell efficiency of 24.2% and module efficiency of 21.2%.46 The IBC structure has both p- and n- type contacts on the backside, reducing optical reflection losses due to the metallic contact grid. However, it also suffers from high processing costs and expensive n- type CZ wafers, which limit its applicability to high-efficiency market sectors.

In order to reduce costs, modifications of cell structure and materials have been tried. A promising low-cost solution is the interdigitated front contact (IFC) structure, which adopts several advanced semiconductor technologies.47 Also, multi-crystalline wafers lower manufacturing cost even though the efficiency suffers from recombination losses at the grain boundaries. Figure 19 shows the schematic diagrams of PERL, IBC and IFC solar cells.

Figure 19. Crystalline Si solar cell structures: (a) passivated emitter rear local (PERL) structure; (b) interdigitated back contact (IBC) structure; and (c) interdigitated front contact (IFC) structure.

Although in theory Si solar cells can reach 29.3% efficiency, the practical efficiency limit is expected to be 26%. Efficiency trends of some solar cell technologies are plotted in Fig. 20