Harsh Environment Electronics E-Book

• Herausgeber: Wiley-VCH Verlag GmbH & Co. KGaA
• Kategorie: Fachliteratur
• Sprache: Englisch

Seitenzahl: 691

Veröffentlichungsjahr: 2019

Beschreibung

Provides in-depth knowledge on novel materials that make electronics work under high-temperature and high-pressure conditions

This book reviews the state of the art in research and development of lead-free interconnect materials for electronic packaging technology. It identifies the technical barriers to the development and manufacture of high-temperature interconnect materials to investigate into the complexities introduced by harsh conditions. It teaches the techniques adopted and the possible alternatives of interconnect materials to cope with the impacts of extreme temperatures for implementing at industrial scale. The book also examines the application of nanomaterials, current trends within the topic area, and the potential environmental impacts of material usage.

Written by world-renowned experts from academia and industry, Harsh Environment Electronics: Interconnect Materials and Performance Assessment covers interconnect materials based on silver, gold, and zinc alloys as well as advanced approaches utilizing polymers and nanomaterials in the first section. The second part is devoted to the performance assessment of the different interconnect materials and their respective environmental impact.

-Takes a scientific approach to analyzing and addressing the issues related to interconnect materials involved in high temperature electronics
-Reviews all relevant materials used in interconnect technology as well as alternative approaches otherwise neglected in other literature
-Highlights emergent research and theoretical concepts in the implementation of different materials in soldering and die-attach applications
-Covers wide-bandgap semiconductor device technologies for high temperature and harsh environment applications, transient liquid phase bonding, glass frit based die attach solution for harsh environment, and more
-A pivotal reference for professionals, engineers, students, and researchers

Harsh Environment Electronics: Interconnect Materials and Performance Assessment is aimed at materials scientists, electrical engineers, and semiconductor physicists, and treats this specialized topic with breadth and depth.

Leseprobe

Table of Contents

Cover

Preface

What This Book Is About

1 Wide‐Bandgap Semiconductor Device Technologies for High‐Temperature and Harsh Environment Applications

1.1 Introduction

1.2 Crystal Structures and Fundamental Properties of Different Wide‐Bandgap Semiconductors

1.3 Devices of Wide‐Bandgap Semiconductors

1.4 Conclusion

References

2 High‐Temperature Lead‐free Solder Materials and Applications

2.1 Introduction

2.2 High‐Temperature Solder Applications

2.3 Requirements for a Candidate Solder in High‐temperature Applications

2.4 High‐Pb‐Content Solders

2.5 Zn‐Based Solders

2.6 Bi‐Based Solders

2.7 Au‐Based Solders

2.8 Sn‐Based Solders

2.9 Conclusion and Future Research Directions

References

3 Role of Alloying Addition in Zn‐Based Pb‐Free Solders

3.1 Introduction

3.2 Zn‐Al‐Based Solders

3.3 Zn–Sn‐Based Solders

3.4 Zn‐Based Alloys with Minor Addition

3.5 Zn–Ni‐Based Solders

3.6 Zn–Mg‐Based Solders

3.7 Zn–In‐Based Solders

3.8 Zn–Ag‐Based Solders

3.9 Conclusion

Acknowledgment

References

4 Effect of Cooling Rate on the Microstructure, Mechanical Properties, and Creep Resistance of a Cast Zn–Al–Mg High‐temperature Lead‐Free Solder Alloy

4.1 Introduction

4.2 Experimental Procedures

4.3 Results and Discussion

4.4 Conclusions

References

5 Development of Zn–Al–

x

Ni Lead‐Free Solders for High‐Temperature Applications

5.1 Introduction

5.2 Experimental

5.3 Results and Discussions

5.4 Conclusions

Acknowledgments

References

6 Study of Zn–Mg–Ag High‐Temperature Solder Alloys

6.1 Introduction

6.2 Materials and Methods

6.3 Results and Discussions

6.4 Conclusions

Acknowledgments

References

7 Characterization of Zn–Mo and Zn–Cr Pb‐Free Composite Solders as a Potential Replacement for Pb‐Containing Solders

7.1 Introduction

7.2 Experimental

7.3 Results and Discussion

7.4 Conclusion

Acknowledgments

References

8 Gold‐Based Interconnect Systems for High‐Temperature and Harsh Environments

8.1 Introduction

8.2 High‐Temperature Solder System

8.3 Various Au‐Based Solder Systems

8.4 Other Interconnecting Systems

8.5 Applications

8.6 Substitutes for Au and Reductions in Use

8.7 Future Uses of Au

8.8 Conclusions

Acknowledgments

References

9 Bi‐Based Interconnect Systems and Applications

9.1 Introduction

9.2 Various Bi‐Based Solder Systems

9.3 Conclusion

Acknowledgments

References

10 Recent Advancement of Research in Silver‐Based Solder Alloys

10.1 Introduction

10.2 Overview of Different Ag‐Based Systems

10.3 Conclusions

Acknowledgments

References

11 Silver Nanoparticles as Interconnect Materials

11.1 Introduction

11.2 Synthesis of Ag Nanoparticles

11.3 Composition of Ag Nanopaste

11.4 Joining Methods

11.5 Properties of Nano‐Ag Joints

11.6 Factors Affecting the Properties of Nano‐Ag Joints

11.7 Applications of Ag Nanoparticles

11.8 Conclusions and Future Trends

References

12 Transient Liquid Phase Bonding

12.1 Introduction

12.2 History and Development of TLP

12.3 Theoretical Aspects of TLP

12.4 Development and Applicable Trends of TLP Using Alloy Systems (Phase Diagrams) with Special Features

12.5 Applications and Materials Used in TLPB

12.6 Future of TLP and Conclusion

References

13 All‐Copper Interconnects for High‐Temperature Applications

13.1 Introduction

13.2 Direct Cu‐to‐Cu Bonding

13.3 Cu Paste Bonding

13.4 Conclusions

Acknowledgments

References

14 Glass‐Frit‐Based Die‐Attach Solution for Harsh Environments

14.1 Introduction

14.2 Overview of Different Glass Frit Systems

14.3 Bonding Process

14.4 Bond Characteristics

14.5 Conclusions

Acknowledgments

References

15 Carbon‐Nanotube‐Reinforced Solders as Thermal Interface Materials

15.1 Introduction

15.2 Typical Thermal Interface Materials

15.3 Solders as Thermal Interface Materials

15.4 Literature Study: Different Fabrication Techniques

15.5 Challenges and Future Scope

References

16 Reliability Study of Solder Joints in Electronic Packaging Technology

16.1 Introduction

16.2 Reliability Tests

16.3 Conclusion

Acknowledgments

References

Index

End User License Agreement

List of Tables

Chapter 1

Table 1.1 Comparison of important semiconductors properties for high‐temperature...

Table 1.2 Some important properties of III–V nitride semiconductors.

Chapter 2

Table 2.1 Requirements for a candidate high‐temperature solder.

Table 2.2 Comparison of various high‐temperature Pb‐free solder alternatives.

Chapter 4

Table 4.1 Average chemical composition of the regions shown in Figure 4.5 obta...

Table 4.2 Stress exponents and average activation energies of the tested materia...

Chapter 5

Table 5.1 Chemical composition of Zn–Al–Ni solder alloys.

Table 5.2 Eutectic phase melting characteristics from DTA curves during heating.

Table 5.3 Eutectoid phase transformation characteristics from DTA curves during ...

Table 5.4 CTE of Zn–4Al–

x

Ni solders at temperature range of 30–270 °C.

Table 5.5 Variation in mechanical properties with increasing Ni content.

Table 5.6 Electrical resistivity of Zn–4Al–

x

Ni alloys.

Chapter 6

Table 6.1 XRF Analysis for different Zn–Mg–Ag alloy systems.

Table 6.2 EDS results for the ZMA0 alloy.

Table 6.3 EDS results for the ZMA0.5 alloys.

Table 6.4 EDS results for the ZMA1 alloys.

Table 6.5 Energy‐dispersive X‐ray results for the ZMA3 alloys.

Table 6.6 Variation in mechanical properties with increasing Ag content.

Table 6.7 Conductivity and resistivity values for different ZMA alloys.

Chapter 7

Table 7.1 Melting properties of the Zn–

x

Mo system.

Table 7.2 CTE of Zn–

x

Mo alloy.

Table 7.3 Melting properties of the Zn–

x

Cr system.

Table 7.4 CTE of the Zn–

x

Cr system.

Table 7.5 Comparison of some properties of high‐temperature Pb‐based solders, eu...

Chapter 9

Table 9.1 Properties of Bi–Ag solder alloys compared with Pb–5Sn solder [ 8 –10...

Table 9.2 Thermal properties of Bi–Ag solder alloys compared with Pb–5Sn solder ...

Table 9.3 Indentation hardness and elastic modulus of 78Bi–14Cu–8Sn alloy.

Table 9.4 Solidus and liquidus temperature of different Sn–Bi alloys (°C).

Table 9.5 Die shear strength of as‐bonded and aged Bi–Ni TLP bonds at different ...

Chapter 10

Table 10.1 Melting behavior of typical Pb‐free solders [23] .

Chapter 12

Table 12.1 Characteristics of transient liquid phase bonding.

Table 12.2 Development of TLP‐type processes in years.

Table 12.3 Comparison of Ni–Sn TLP bonding with available TLP bonding techniques...

Chapter 14

Table 14.1 Pb containing low‐melting solder glasses [48] .

Table 14.2 Representative cation compositions of low‐melting Pb‐based glasses [4...

Chapter 15

Table 15.1 Comparison of melting temperature of commercially available TIM solde...

Table 15.2 Comparison of mechanical strength of commercially available TIM solde...

Table 15.3 Comparison of thermal conductivity of commercially available TIM sold...

List of Illustrations

Chapter 1

Figure 1.1 Two types of tetrahedrons forming the building blocks of all...

Figure 1.2 Three types (A, B, C) of Si–C double‐atomic layer arrangemen...

Figure 1.3 Zinc‐blende and wurtzite bonding between Si and C atoms in a...

Figure 1.4 Crystal structure of the purely cubic 3C‐SiC polytype: each ...

Figure 1.5 Crystal structure of (a) 4H‐SiC polytype, where half of the ...

Figure 1.6 Crystal structures of the (a) GaN wurtzite (2H) and (b) zinc...

Figure 1.7 MOVPE (a) Si and (b) Ge incorporation rates as a function of...

Figure 1.8 Schematic cross‐section of 4H‐SiC lateral JFET.

Figure 1.9 Temperature dependence of specific contact resistance (

ρ

...

Figure 1.10 Measured

I

DS

–

V

DS

characteristics of 4H‐SiC n‐channel JF...

Figure 1.11 Circuit schematic of the continuous test.

Figure 1.12 Test waveforms of the module at 560 V and 100 kHz.

Figure 1.13 Leakage current versus temperature.

Figure 1.14 Temperature‐dependent output characteristics.

Figure 1.15 Temperature‐dependent transfer characteristics.

Figure 1.16 Normalized

V

GS(th)

measured during the gate biasing test....

Figure 1.17 (a) Turn‐on loss and (b) Turn‐off loss of CCS050M12CM2 at 6...

Figure 1.18 Schematic cross‐section of the 4H‐SiC planar‐MESFET with p

+

...

Figure 1.19

I

–

V

characteristics of the 4H‐SiC planar‐MESFET (

m

 = 4) ver...

Figure 1.20 (a) The saturation drain current and (b) the transconductan...

Figure 1.21 (a) The drain leakage current and (b) the

I

ON

/

I

OFF

rati...

Figure 1.22 SiC pressure sensor cross‐sectional view.

Figure 1.23 Sensor characteristic response at 200 °C.

Figure 1.24 High‐temperature sensor response.

Figure 1.25

M

versus

H

measurements of rapidly (▴) and slowly (•) aggre...

Figure 1.26 (a) Temperature dependence of

H

c

for 0 : 93% Ni

2+

:ZnO...

Figure 1.27 Vickers hardness of bulk single crystals α‐SiC, AlN, GaN, Z...

Chapter 2

Figure 2.1 Schematic diagram of a power electronics package.

Figure 2.2 Schematic diagram of BGA packaging [15] .

Figure 2.3 Schematic diagram of flip‐chip configurations.

Figure 2.4 Chip‐level packaging using Au wire bonding.

Figure 2.5 Binary phase diagram of Zn–Al solder alloy.

Figure 2.6 Binary phase diagram of Zn–Sn solder alloy.

Figure 2.7 Micrographs of solders: (a and d) Zn–20Sn, (b and e) Zn–30Sn, and (c...

Figure 2.8 Micrographs of Zn–Sn solder alloys between Cu substrate after solder...

Figure 2.9 DSC result of Bi–2.5Ag solder alloy.

Figure 2.10 Endothermic peak temperatures for Bi–Ag solder.

Figure 2.11 Cross‐sectional optical images of Bi–Ag solder bulk: (a) Bi–1.5Ag, ...

Figure 2.12 (a) SEM micrographs of Bi–3.5Ag solder alloy and (b and c) Ag‐rich ...

Figure 2.13 Microstructure of Bi–Ag solders: (a) Bi–2.5Ag and (b) Bi–11Ag.

Figure 2.14 DSC result of Bi–2.5Sb solder.

Figure 2.15 Endothermic peak temperatures for Bi–Sb solder.

Figure 2.16 Cross‐sectional optical images of Bi–Sb solder bulk: (a) Bi–1.5Sb, ...

Figure 2.17 (a and b) SEM micrographs of Bi–5Sb solder alloy and (c) Cu

3

Sb IMC ...

Figure 2.18 Phase diagram of Au–Sn solder alloy.

Figure 2.19 Micrograph of the eutectic Au–Sn alloy.

Figure 2.20 Interfacial reaction of Sn‐rich Au–Sn/Ni solder joint under aging a...

Figure 2.21 Phase diagram of Au–Ge solder.

Figure 2.22 Micrographs of the Au–0.24Ge–0.05Sb solder alloy (a) as‐cast and (b...

Figure 2.23 Micrographs of Sn–5Sb/Cu couple reacted at 260 °C for (a) 30 minute...

Figure 2.24 Effects of temperature on the average grain size of Sn–5Sb.

Figure 2.25 SEM micrographs of cross‐sectional view of Sn–3.5Ag–0.7Cu–

x

Bi solde...

Figure 2.26 Average IMC thickness against aging time at aging temperature of 12...

Figure 2.27 Grain size as a function of La content.

Figure 2.28 Particle size as a function of thermal aging condition.

Figure 2.29 Average grain size versus La content for (a) as‐cast and (b) therma...

Figure 2.30 Average IMC particle size versus La content for (a) as‐cast and (b)...

Figure 2.32 Effect of thermal aging at 200 °C on the shear strength of Sn–1Ag–0...

Figure 2.33 FESEM micrographs samples aged at 200 °C for 300 hours: (a) Sn–1Ag–...

Figure 2.31 FESEM micrographs of the as‐cast samples: (a) Sn–1Ag–0.5Cu, (b) Sn–...

Chapter 3

Figure 3.1 Zn‐rich portion of the Al–Zn phase diagram.

Figure 3.2 Microstructure and EDX analysis of the different points in the SEM m...

Figure 3.3 SEM micrographs of (a) Zn–4Al–3Mg and (b) Zn–4Al–3Mg–13Sn alloys.

Figure 3.4 SEM micrographs showing different phases in (a) Zn–6Al–5Sn and (b) Z...

Figure 3.5 SEM micrograph of the interface between Zn–12Al–1.0In alloy and Cu s...

Figure 3.6 High‐magnification SEM images of the joints ultrasonically brazed at...

Figure 3.7 Zn–Sn binary phase diagram highlighting the Zn‐rich interest region ...

Figure 3.8 SEM micrographs showing

α

‐Zn phase and

β

Sn–

α

Zn eutect...

Figure 3.9 Representative longitudinal microstructures of the Zn–10 Sn and Zn–4...

Figure 3.10 Effect of peak temperature on the thickness of IMC layers in the di...

Figure 3.11 SEM images in

backscattered electron image

(

BEI

) mode of the interf...

Figure 3.12 Scanning electron micrographs showing area fraction (i.e. 7%) of Zn...

Figure 3.13 TMA curves for (a) Zn, (b) Zn–2Mg, and (c) Zn–5Mg showing the avera...

Chapter 4

Figure 4.1 Shear–stress‐normalized displacement curves of the (a) SC and (b) F...

Figure 4.2 Temperature dependence of the (a) SYS and (b) USS for the SC and FC ...

Figure 4.3 Temperature dependence of the hardness values for the SC and FC cond...

Figure 4.4 Optical micrographs of the (a) SC and (b) FC alloys at different mag...

Figure 4.5 SEM micrographs of the (a) SC and (b) FC alloys, showing different m...

Figure 4.6 XRD patterns of the tested alloys.

Figure 4.7 SEM micrograph of the (a) SC alloy, showing dispersion of second pha...

Figure 4.8 SEM micrograph of the (a) FC alloy, showing dispersion of second pha...

Figure 4.9 (a) Heating and (b) cooling DSC curves of the tested materials.

Figure 4.10 Impression creep curves of the SC alloy obtained at different tempe...

Figure 4.11 Impression creep curves of the FC alloy obtained at different tempe...

Figure 4.12 Comparison of minimum impression creep rates obtained at different ...

Figure 4.13 Temperature‐compensated minimum impression velocity as a function o...

Figure 4.14 Plots of the temperature dependence of the temperature‐compensated ...

Chapter 5

Figure 5.4 Optical microstructures of Zn–4Al–0.6Ni solder at different magnific...

Figure 5.1 Optical microstructures of Zn–4Al solder at different magnification ...

Figure 5.2Figure 5.2 Optical microstructures of Zn–4Al–0.2Ni solder at differen...

Figure 5.3Figure 5.3 Optical microstructures of Zn–4Al–0.4Ni solder at differen...

Figure 5.5 (a) SEM micrograph of Zn–4Al–0.2Ni showing different points for EDS ...

Figure 5.6 (a) Rod‐shaped IMC in Zn–4Al–0.6Ni showing different points for EDS ...

Figure 5.7 Area fraction of proeutectic β‐phase (via ImageJ): (a) 35.6% (b) 13....

Figure 5.8 Variation in interlamellar spacing in Zn–4Al–0.4Ni at different loca...

Figure 5.9 DTA curves of (a) Zn–4Al, (b) Zn–4Al–0.2Ni, (c) Zn–4Al–0.4Ni, and (d...

Figure 5.10 TMA curves of (a) Zn–4Al, (b) Zn–4Al–0.2Ni, (c) Zn–4Al–0.4Ni, and (...

Figure 5.11 Fracture surfaces of (a) 0Ni, (b) 0.2Ni, (c) 0.4Ni, and (d) 0.6Ni c...

Chapter 6

Figure 6.1 Isothermal section of Mg–Zn–Ag ternary at 300 °C.

Figure 6.2 FESEM images of (a) ZMA0, (b) ZMA0.5, (c) ZMA1, and (d) ZMA3 at 1000...

Figure 6.3 FESEM images of the ZMA0 alloy at (a) lower magnification and (b) hi...

Figure 6.4 FESEM image of the ZMA0.5 alloy showing points for EDS analysis.

Figure 6.5 FESEM image of the ZMA1 alloy at (a) lower magnification and (b) hig...

Figure 6.6 FESEM image of the ZMA3 alloy at (a) lower magnification and (b) hig...

Figure 6.7 DSC thermographs of Zn–3Mg–

x

Ag alloys.

Chapter 7

Figure 7.1 DTA curves for Zn–

x

Mo system.

Figure 7.2 Scanning electron micrograph of Zn–0.4Mo showing grain size measurem...

Figure 7.3 Scanning electron micrograph of Zn–0.6Mo showing grain size measurem...

Figure 7.4 Column chart showing Brinell hardness of the Zn–

x

Mo system.

Figure 7.5 Column chart showing tensile strength of the Zn–

x

Mo system.

Figure 7.6 Tensile fracture surface of (a) and (b) Zn–0.4Mo; (c) and (d) Zn–0.6...

Figure 7.7 Column chart showing %IACS of Zn–

x

Mo alloys.

Figure 7.8 DTA graph of the Zn–

x

Cr system.

Figure 7.9 Scanning electron micrograph of Zn–0.2Cr showing grain size measurem...

Figure 7.10 Scanning electron micrograph of Zn–0.4Cr showing grain size measure...

Figure 7.11 Column chart showing Brinell hardness of the Zn–

x

Cr system.

Figure 7.12 Column chart showing tensile strength of the Zn–

x

Cr system.

Figure 7.13 Tensile fracture surface of (a) and (b) Zn–0.2Cr; (c) and (d) Zn–0....

Figure 7.14 Column chart showing %IACS of the Zn–

x

Cr system.

Chapter 8

Figure 8.1 Au–Sn phase diagram.

Figure 8.2 SEM images of binary Au-20Sn (wt fraction) eutectic alloy showing ph...

Figure 8.3 SEM‐

backscattered electron

(

BSE

) micrograph of the (a) Au–0.35Sn–0.0...

Figure 8.4 Microhardness of the three Au‐rich alloys before and after thermal a...

Figure 8.5 Optical micrographs of the Sn–0.30Au–0.08Ag (mole-fraction) candidat...

Figure 8.6 Microhardness of the 3Sn‐rich alloys before and after thermal aging ...

Figure 8.7 Au–Ge phase diagram.

Figure 8.8 SEM image of the as‐produced Au–0.28Ge (mole fraction) eutectic allo...

Figure 8.9 SEM of the Au–0.24Ge–0.05Sb candidate alloy (a) as‐produced, (b) 150...

Figure 8.10 Microhardness values showing the softness induced by microalloying ...

Figure 8.11 Au–In phase diagram.

Figure 8.12 Au–Si phase diagram [38].

Figure 8.13 Schematic representation of the Au–Sn SLID samples. Layer thickness...

Figure 8.14 SEM picture of the cross‐section of a typical fully bonded sample u...

Chapter 9

Figure 9.1 Bi–Ag binary phase diagram showing eutectic composition wit...

Figure 9.2 Microstructure of Bi–Ag solder balls: (a) Bi–2.5Ag and (b) B...

Figure 9.3 Tensile properties of bulk Bi–Ag and pure Bi samples: (a) te...

Figure 9.4 Polarization curves for (a) Bi–11Ag, Pb–5Sn, and Zn–40Sn all...

Figure 9.5 Bi–Sb phase diagram exhibiting complete solid solubility.

Figure 9.6 Relation between temperature and wetting angle with Cu and S...

Figure 9.7 Cross‐sectional optical images for (a) Bi–1.5Sb, (b) Bi–2.5S...

Figure 9.8 Change in wetting angle with Ag and Sb addition in Bi‐based ...

Figure 9.9 Effect of Cu on (a) melting point of solder alloy and spread...

Figure 9.10 Representative SEM micrograph of Cu‐60% Bi samples sintered...

Figure 9.11 Schematic microstructure of the bulk of the as‐reflowed 78B...

Figure 9.12 Thermal conductivity vs. temperature for Bi–Cu–Sn alloy [3...

Figure 9.13 Bi–Sn phase diagram showing solidus and liquidus temperatur...

Figure 9.14 SEM micrographs of interfaces of Bi–5 wt% Sn solder with (a...

Figure 9.15 SEM micrographs of 70Bi–30%Sn (

backscatter electron image

,

Figure 9.16 Microstructure of (a) bulk Bi–2La solder with La phases and...

Figure 9.17 Cross‐sectional microstructure of the fabricated Bi/Cu–Al–M...

Chapter 10

Figure 10.1 Application method for sintered Ag paste with pressure.

Figure 10.2 SEM micrograph of silver pastes sintered at 250 °C under 40 MPa pre...

Figure 10.3 Application method for pressureless sintered Ag paste.

Figure 10.4 SEM image of cross‐section of sintered nano‐Ag joint.

Figure 10.5 (a) Schematic drawing of the bonding arrangement (not to scale) wit...

Figure 10.6 Cross‐sectional backscattered electron images of nanoporous bonding...

Figure 10.7 Cross‐section SEM images of a perfectly bonded sample at low magnif...

Figure 10.8 SEM picture of the cross‐section of the assembly composed of a Si c...

Figure 10.9 Cross‐sectional SEM images of a typical bonded sample at high magni...

Figure 10.10 Schematic representation of solid‐state bonding process between Si...

Chapter 11

Figure 11.1 A schematic diagram of the experimental setup (not to scal...

Figure 11.2 Schematic representation of size‐controlled Ag nanoparticle...

Figure 11.3 An illustration of nanoparticle synthesis by high‐temperatu...

Figure 11.4 The laser ablation experimental setup [38] .

Figure 11.5 Experimental setup of the microwave apparatus with a single...

Figure 11.6 Temperature profile for nano‐Ag paste sintering.

Figure 11.7 Schematic diagrams of the sintering process of Ag nanoparti...

Figure 11.8 Field emission scanning electron microscopy (FESEM) images ...

Figure 11.9 Representation of the relationship between die‐attach area ...

Figure 11.10 Heat capacity of nano‐Ag‐filled ACA with SAM.

Figure 11.11 Thermal conductivity of nano‐Ag‐filled ACAs with SAM.

Figure 11.12 Viscosity as a function of the shear rate for four differe...

Figure 11.13 Measured creep compliance

J

c

and recovery compliance

J

Figure 11.14 Recovery behaviors of four kinds of Ag pastes.

Figure 11.15 Comparing conductivity of e‐beam‐irradiated Ag paste with ...

Figure 11.16 Resistivity change of printed line of hybrid (micron‐sized...

Figure 11.17 R

TIM

of the TIM using three kinds of AgNP sintered at 250 ...

Figure 11.18 Roughness mean square (RMS) and mean electrical conductivi...

Figure 11.19 SEM images at 5000× magnification for post‐sintered Ag80–A...

Figure 11.20 Contact resistivity versus ascending joint pressure.

Figure 11.21 (a) Thermal conductivity and porosity of Ag nanoparticles ...

Figure 11.22 R

TIM

of the TIM using AgNP‐20 (stars), AgNP‐30 (dots), and...

Chapter 12

Figure 12.1 Four stages of TLP bonding (for bulk materials) defined by Tuah‐Pok...

Figure 12.2 Stages of TLP bonding occurring when A (silver) is bonded with a B ...

Figure 12.3 Detailed nominal stages in the TLP bonding process (based on Refs. ...

Figure 12.4 Nominal stages of TLP bonding (for microjoining of materials).

Figure 12.5 Schematic of the reactive TLP bonding between Al‐bearing Mg alloy a...

Figure 12.6 Cu–Sn phase diagram with major phases.

Figure 12.7 SEM images taken from the polished cross‐sections of the Cu/Sn/Cu s...

Figure 12.8 (a) Fracture mode (SEM image) and (b) scanning acoustic microscope ...

Figure 12.9 Phase diagram of Ni–Sn binary system showing Sn percentage and poss...

Figure 12.10 Cross‐sectional SEM micrographs of the Ni/Sn/Ni TLP bonded interfa...

Figure 12.11 (a) Fracture mode (SEM image) and (b) void morphology (cross secti...

Figure 12.12 Ag–Sn phase diagram [69].

Figure 12.13 An SEM image taken from the polished cross‐section of as‐reflowed ...

Figure 12.14 (a) Soldered at 270 °C for 60 minutes with resulting phases AuSn‐δ...

Figure 12.15 Phase diagram of Au–Sn with eutectic shift in the left portion of ...

Figure 12.16 Phase diagram of Cu–Ga.

Chapter 13

Figure 13.1 TEM microstructure of CuCu bonding at a temperature of 40...

Figure 13.2 TEM image of the interface between the chemical mechanical ...

Figure 13.3 Cross‐section transmission electron microscope (

XTEM

) highe...

Figure 13.4 Morphology of Cu nanoparticles observed by transmission ele...

Figure 13.5 TEM observation of CuCu bonding interface with PVD Cu NPs ...

Figure 13.6 (a) Cu and (b) Ni atomic mapping images from EDS analysis o...

Figure 13.7 Cross‐sectional FE‐SEM image of the CuCu joint bonded with...

Figure 13.8 The cross‐sectional SEM images of CuCu bonding interfaces ...

Chapter 14

Figure 14.1 Schematic of the structure of a fired conductive frit showi...

Figure 14.2 Schematic diagram of die‐attaching process on ceramic subst...

Figure 14.3 Schematic of the typical bonding thermal cycle (not to scal...

Figure 14.4 Voids in glass frit caused by insufficient heat treatment o...

Figure 14.5 Variation of average shear forces of die attach on ceramic ...

Figure 14.6 A typical SEM micrograph showing the Si die‐bonded structur...

Figure 14.7 Results of pull test glass‐frit‐bonded sensor chips.

Figure 14.8 A typical image from the Microfocus X‐ray inspection system...

Chapter 15

Figure 15.1 Geometry of the single‐lap solder joint.

Figure 15.2 X‐ray diffraction patterns showing the peaks of Sn‐phase, B...

Figure 15.3 SEM micrographs of (a) Cu‐coated MWCNTs and (b) fractured s...

Chapter 16

Figure 16.1 Schematic of shear test arrangement.

Figure 16.2 Schematic of the wire pull test.

Figure 16.3 Schematic of the hot ball pull test.

Figure 16.4 Schematic of the cold ball pull (CBP) test.

Figure 16.5 Schematic of the different failure modes after pull test.

Figure 16.6 Schematic of the three‐point bend test.

Figure 16.7 Schematic of the four‐point bend test.

Figure 16.8 A typical board‐level drop‐impact test setup.

Figure 16.9 A typical drop test board layout of chip scale packages (CS...

Figure 16.10 Solder joints subjected to shear strain during thermal cyc...

Figure 16.11 Solder bumps (joints) subjected to tensile loading due to ...

Figure 16.12 Representative temperature profile for thermal cycle test ...

Figure 16.13 Thermal fatigue crack through the bulk solder near the pac...

Figure 16.14 Schematic of the shock impact test setup with (a) three‐po...

Figure 16.15 Schematic of the shock impact arrangement test with swingi...

Figure 16.16 Diagram of transducer operation in

scanning acoustic micro

...

Figure 16.17 Measuring a crack inside a SAC solder joint of 0603 (1.5 ×...

Guide

Cover

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E1

Harsh Environment Electronics

Interconnect Materials and Performance Assessment

Edited by

Ahmed Sharif

Copyright

Editor

Prof. Ahmed Sharif

Bangladesh University of Engineering and Technology

Department of Materials and

Metallurgical Engineering

Zahir Raihan Rd

1000 Dhaka

Bangladesh

Cover Image: © Elizabeth Fernandez/Getty Images

All books published by Wiley‐VCH are carefully produced. Nevertheless, authors, editors, and publisher do not warrant the information contained in these books, including this book, to be free of errors. Readers are advised to keep in mind that statements, data, illustrations, procedural details or other items may inadvertently be inaccurate.

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applied for

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A catalogue record for this book is available from the British Library.

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the Deutsche Nationalbibliothek

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© 2019 Wiley‐VCH Verlag GmbH & Co. KGaA, Boschstr. 12, 69469 Weinheim, Germany

All rights reserved (including those of translation into other languages). No part of this book may be reproduced in any form – by photoprinting, microfilm, or any other means – nor transmitted or translated into a machine language without written permission from the publishers. Registered names, trademarks, etc. used in this book, even when not specifically marked as such, are not to be considered unprotected by law.

Print ISBN: 978‐3‐527‐34419‐2

ePDF ISBN: 978‐3‐527‐81399‐5

ePub ISBN: 978‐3‐527‐81397‐1

oBook ISBN: 978‐3‐527‐81396‐4

To my father and mother

For their earnest endeavors to shape my educational career.

To my children

For bringing joy and happiness in the family.

To my wife

For her persistent and enduring support.

Preface

High‐temperature electronics are attractive for possible applications in automotive, aerospace, downhole drilling equipment, or other industrial systems. These devices need to perform under extreme temperature conditions, and not show any deterioration in terms of switching speeds, junction temperatures, power density, and so on. Wide‐bandgap semiconductors have been demonstrated to operate at temperatures up to 500 °C, but packaging is still a major hurdle to product development. In this connection, there is a growing interest in solutions for interconnect materials for wide‐bandgap semiconductor in order to fabricate functional electronics for applications where the temperature at the die exceeds 300 °C.

This book has two objectives:

(i) Identify the technical barriers to the development and manufacture of high‐temperature interconnect materials to investigate the complexities introduced by harsh conditions.

(ii) Understand the techniques adopted and the possible alternatives of interconnect materials to cope with the impacts of extreme temperatures for implementing at industrial scale.

This book is written for graduate and research students in materials engineering and electronics engineering. It will serve as a useful supplement to microelectronics course material, treating this specialized discipline with breadth and depth. The book answers several questions related to interconnect materials options that come to mind when one starts thinking and imagining beyond a normal electronics course. While there has been great success in the adoption of various materials and systems for high‐temperature applications, there is still room for development and improvement. The book highlights emergent research and theoretical concepts in the implementation of different materials in soldering and die‐attach applications. Examining the application of nanomaterials, current trends within the topic area, and the potential environmental impacts of material usage, the book is a pivotal reference for professionals, engineers, students, and researchers. A knowledge of the different materials systems to deal with the effects of temperature on performance and of the strategies is needed for engineers to make reliable devices. Currently, no book provides this essential information. Since this book takes a scientific approach for analyzing and addressing the issues related to interconnect materials involved in high‐temperature electronics, it is valuable as a handbook for graduates, engineering, manufacturing, and science professionals.

What This Book Is About

This book presents a comprehensive, critical review of the state of the art in finding a Pb‐free solution in soldering and die‐attach application for high‐temperature electronics, providing a systematic and scientific exploration of the issues involved in material selection and developing bonding techniques for particular applications. Researchers with different materials background have contributed to 16 chapters covering topics ranging from semiconductors, materials selection for interconnection, to reliability testing. Chapter 1 introduces the field of wide‐bandgap semiconductor for high‐temperature electronics, comparing the different types of semiconductors, listing potential applications, and presenting the technical challenges that must be addressed for successful high‐temperature products to be developed. Chapter 2 identifies the possible lead‐free solder alternatives for applications at elevated temperature and also specifies the further research requiring areas. The next five chapters particularly focus on the zinc (Zn)‐based solder system, which is the cheapest option with different alloying conditions as a high‐temperature interconnect material to be used in elevated temperature electronics systems. Chapter 3 discusses the overall characteristics of different types of Zn‐based high‐temperature solder alloys with respect to relative advantages, limitations, cost, workability, and reliability issues to make it favorable for ultimate device‐level implementation. Chapter 4 focuses on the elevated‐temperature strength, hardness, and creep resistance of the Zn–4Al–3Mg solder alloy solidified at variable cooling rates. Chapter 5 investigates the effects of Ni addition on the microstructure, melting behavior, and thermal and mechanical properties of the Zn–Al‐based lead free solder (i.e. Zn–4Al–xNi). Chapter 6 focuses on the effects of Ag addition on the microstructure and mechanical, electrical, and thermal properties of the Zn–3Mg–xAg (i.e. x = 0.5, 1, and 3) ternary alloys. Chapter 7 demonstrates the effect of a small addition of refractory metal (i.e. Mo and Cr) particles on the microstructural and mechanical properties of the Zn matrix. Chapter 8 explores the various Au‐based interconnecting systems available at high temperature in place of Pb‐containing alloys along with their properties, various bonding technologies, and their future trend in the modern world. Chapter 9 summarizes the different bonding technologies based on Bi‐based interconnect materials in terms of chemical composition and structural properties. The next two chapters discuss silver (Ag)‐based bonding materials in packaging devices for high‐temperature use. Chapter 10 highlights current trends and up‐and‐coming researches in the implementation of Ag in soldering and die‐attach applications. Chapter 11 discusses the various methods of Ag nanoparticle synthesis and the bonding technologies of sintered Ag joints while examining their key properties at different sintering conditions. Chapter 12 describes transient liquid phase (TLP) bonding in brief, in special relation to phase diagram describing the mechanism behind joint forming, classification, applicable variants, and characteristic features of some potential alloy systems. Various all‐Cu connection technology for Cu–Cu bonding methods and the fundamental aspects of the bonding mechanisms are reviewed in Chapter 13. Chapter 14 focuses on the different compositional systems for developing glass‐based die attach along with the basic bonding technology and as well as on the performance and reliability of the obtained joints. Chapter 15 emphasizes the importance of carbon nanotube (CNT)‐reinforced solder composite for their application as thermal interface materials. Finally, Chapter 16 presents procedures for accelerated testing and nondestructive examinations of high‐temperature electronics for reliability determination.

20 August 2018

Ahmed Sharif

Dhaka

1Wide‐Bandgap Semiconductor Device Technologies for High‐Temperature and Harsh Environment Applications

Md. Rafiqul Islam1 Roisul H. Galib2 Montajar Sarkar1 and Shaestagir Chowdhury3

1Bangladesh University of Engineering and Technology (BUET), Department of Materials and Metallurgical Engineering, Old Academic Building, Zahir Raihan Road, Dhaka, 1000, Bangladesh

2University of California San Diego, Department of Mechanical and Aerospace Engineering, La Jolla, CA, 92093, USA

3Portland State University, Department of Mechanical and Materials Engineering, OR, 97291, USA

CHAPTER MENU

Introduction, 1

Crystal Structures and Fundamental Properties of DifferentWide-Bandgap Semiconductors, 3

Devices of Wide‐Bandgap Semiconductors, 10

Conclusion, 25

1.1 Introduction

Silicon carbide (SiC) has become the preferred semiconductor material for harsh environment sensing applications, induction heating, photovoltaics, downhole oil development, and hybrid and electric vehicles because of its wide‐bandgap energy (3.2 eV for 4H‐SiC), excellent chemical and thermal stability, and high breakdown electric field strength (∼2.2 MV cm−1) [1–3]. Particularly in sensors and electronic systems which can operate in the temperature range 300–600 °C, are required for in situ monitoring of fuel combustion and subsurface reservoirs (i.e. deep well drilling), and for outer space exploration [3]. The use of semiconductor devices that can operate properly at such high temperatures would not only minimize the need for expensive and large cooling systems but also provide for improved system reliability [4]. SiC also has gained popularity as a material for both unipolar and bipolar power device applications under high‐power, high‐frequency and high‐temperature conditions. Besides, high‐temperature pressure sensors have been proposed and implemented using SiC‐based piezoresistive devices and have demonstrated sensing capabilities between 350 and 600 °C [5]. Piezoresistive sensors, however, exhibit strong temperature dependence and suffer from contact resistance variations at elevated temperatures. Moreover, SiC has a longer lifetime, since it is an indirect bandgap material. The high lifetime yields a long diffusion length, and thus a high base transport factor. SiC is replacing Si as a semiconductor since SiC has the capability to be used in high‐temperature, high‐speed, and high‐voltage applications. Most current SiC‐based electronic devices are fabricated using either 4H‐ or 6H‐SiC due to the aforementioned shortcoming of 3C‐SiC. Between 4H‐ and 6H‐SiC, 4H‐SiC has substantially higher carrier mobility, shallower dopant ionization energies, and low intrinsic carrier concentration. Thus, it is the most favorable polytype for high‐power, high‐frequency, and high‐temperature device applications. In addition, 4H‐SiC has an intrinsic advantage over 6H‐SiC for vertical power device configurations because it does not exhibit electron mobility anisotropy, while 6H‐SiC does [6]. Indeed, many SiC device fabrication efforts have shifted toward 4H‐SiC as it has become more readily available. For example, the unipolar 4H‐SiC junction field‐effect transistor (JFET) and the metal semiconductor field‐effect transistor (MESFET) are seen as suitable structures for integrated circuit (IC) development since they do not suffer from gate oxide degradation.

Apart from SiC, gallium nitride (GaN) has gained much interest since it is naturally a high bandgap emitter. GaN not only has a higher bandgap, 3.4 eV, than SiC but it also has a high thermal conductivity, 1.3 W cm−1 °C−1. GaN‐based field‐effect transistors (FETs) such as high‐electron mobility transistors (HEMTs) and metal–oxide–semiconductor (MOS) channel HEMTs have shown outstanding properties in terms of achieving high breakdown voltage, low on resistance, and high switching frequency [7,8].

In the field of light emitting diode (LED) devices, several trends are pushing research into new materials to improve their efficiency. LED efficiency is increasing by strain control of epitaxial films that compose the LED's active region structure [9]. Heterostructures of GaInN and GaN are used to produce a strain‐relieving layer located beneath the active region [10]. Moreover, implementation of LED driver circuits using GaN‐based FETs can potentially increase their efficiency and improve switching frequencies.

Wide‐bandgap emitters are also bringing semiconductor technology to full color displays [11]. For the first time, all three primary colors can be generated using semiconductor technology, which promises to allow the reliability, compactness, and other desirable attributes of semiconductors to be applied to this important technological market [11]. Besides, diluted magnetic semiconductor (DMS) Ni2: ZnO are ferromagnetic at high temperatures, which is attributed to the increase in domain volumes and the generation of lattice defects upon aggregation [12].

In this chapter, we focus on the crystal structures of SiC, GaN, and AlN. Then, we correlate their structures with their applications in JFET, metal oxide semiconductor field‐effect transistor (MOSFET), MESFET, etc.

1.2 Crystal Structures and Fundamental Properties of Different Wide‐Bandgap Semiconductors

1.2.1 Relevant Properties of GaN, SiC, and Si

Table 1.1 compares the relevant material properties of SiC and GaN with Si, the three most popular semiconductor device technologies for high‐temperature applications. Most notable are the large thermal conductivities, breakdown voltages, and saturation velocities of SiC and GaN. The device maximum operating temperature parameter is calculated as the temperature at which the intrinsic carrier concentration equals 5 × 1015 cm−3 and is intended as a rough estimate of the bandgap limitation on device operation. More important for the eventual maximum operating temperature is the physical stability of the material.

Table 1.1 Comparison of important semiconductors properties for high‐temperature electronics.

Property

Si

3C SiC (6H SiC)

GaN

Bandgap

1.1

2.2

3.39

Maximum operating temperature (K)

600

1200

Melting point (K)

1690

Sublimes

Physical stability

Good

Excellent

Good

Electron mobility (RT, cm

2

 V

−1

 s

−1

)

1400

1000

900

Hole mobility (RT, cm

2

 V

−1

 s

−1

)

600

40

150

Breakdown voltage (

E

b

, 10

6

 V cm

−1

)

0.3

4

5

Thermal conductivity (

c

T

, W cm

−1

)

1.5

5

1.3

Figure 1.1 Two types of tetrahedrons forming the building blocks of all SiC crystals, with each tetrahedron consisting of one Si atom and four covalently bonded nearest‐neighboring C atoms.

Figure 1.2 Three types (A, B, C) of Si–C double‐atomic layer arrangement along the c‐axis (stacking direction) through close‐packed spheres. The c‐axis is normal to the paper plane.

1.2.2 Structure of SiC

1.2.2.1 Polytypism in SiC

SiC is the most prominent of a family of close‐packed materials that exhibit a one‐dimensional polymorphism called polytypism. The SiC polytypes are differentiated by the stacking sequence of the tetrahedrally bonded Si–C bilayers, such that the individual bond lengths and local atomic environments are nearly identical, while the overall symmetry of the crystal is determined by the stacking periodicity. Similar to silicon, SiC is a covalently bonded semiconductor. In the crystalline form, each silicon atom is covalently bonded to four neighboring carbon atoms to form a tetrahedron (Figure 1.1) and vice versa. There are two types of tetrahedrons in the SiC crystal. The first type is obtained by rotating another tetrahedron along its c‐axis by 180°, and one type of tetrahedron is the mirror image of the other when the c‐axis is parallel to the mirror. The c‐axis denotes the direction normal to the Si–C double‐atomic layers. In each layer, the silicon (or carbon) atoms have a close‐packed hexagonal (HCP) arrangement. There are three types of sites (named A, B, C) in arranging the Si–C double‐atomic layers, and each layer is normal to the c‐axis (Figure 1.2).

A shorthand has been developed to catalog the literally infinite number of possible polytype crystal structures. Each SiC bilayer, while maintaining the tetrahedral bonding scheme of the crystal, can be situated in one of three possible positions with respect to the lattice. These are each arbitrarily assigned the notation A, B, or C. Depending on the stacking order, the bonding between Si and C atoms in adjacent bilayer planes is either of a zinc‐blende (cubic) or wurtzite (hexagonal) nature. Zinc‐blende bonds are rotated 60° with respect to nearest neighbors, while hexagonal bonds are mirror images (Figure 1.3). Each type of bond provides a slightly altered atomic environment, making some lattice sites inequivalent in polytypes with mixed bonding schemes and reducing the overall crystal symmetry. These effects are important when considering the substitutional impurity incorporation and electronic transport properties of SiC.

Figure 1.3 Zinc‐blende and wurtzite bonding between Si and C atoms in adjacent planes. The three tetrahedral bonds are 60° rotated in the cubic case and mirror images in the hexagonal case.

If the stacking is ABCABC…, the purely cubic zinc‐blende structure, commonly abbreviated as 3C‐SiC (or beta SiC), is realized (Figure 1.4). The number 3 refers to the three bilayer periodicity of the stacking, and the letter C denotes the overall cubic symmetry of the crystal. 3C‐SiC is the only possible cubic polytype. All other polytypes are mixtures of the fundamental zinc‐blende and wurtzite bonds.

Figure 1.4 Crystal structure of the purely cubic 3C‐SiC polytype: each lattice site (k, representing cubic symmetry) is equivalent.

Some common hexagonal polytypes with more complex stacking sequences are 4H‐ and 6H‐SiC (Figure 1.5). 4H‐SiC is composed equally of cubic and hexagonal bonds, while 6H‐SiC is two‐thirds cubic. Despite the cubic elements, each has overall hexagonal crystal symmetry. The family of hexagonal polytypes is collectively referred to as alpha SiC. Rhombohedral structures such as 15R and 21R have also been documented [13].

Figure 1.5 Crystal structure of (a) 4H‐SiC polytype, where half of the atomic sites are hexagonally bonded (h), while half are cubic (k). (b) 6H‐SiC polytype where the lattice is two‐third cubic (k1 and k2) and one‐third hexagonal (h1). The two cubic sites are inequivalent and are expected to have slightly different binding energies for substitutional impurities.

4H‐ and 6H‐SiC are the only choices for wafer substrates since 3C‐SiC wafers are not yet commercially available. Regardless of polytype, fabrication of devices directly on SiC wafers is hindered by lack of device quality wafers, inability to drive in surface doping, and poor electrical quality as a result of direct ion implantation into the substrate [14]. Therefore, the SiC electronics fabrication is mainly centered on epitaxial layers grown on these substrates. Currently, high‐quality homoepitaxial layers of 4H‐ and 6H‐SiC with different thicknesses and doping levels are routinely produced. 3C‐SiC is also gaining attention as it can be grown heteroepitaxially on various substrate materials. Furthermore, there has been significant progress in producing device‐grade 3C‐SiC epilayers in recent years. However, it is necessary to further reduce crystallographic structural defects in 3C‐SiC epilayers before this polytype becomes a viable alternative to 4H‐ and 6H‐SiC [15].

1.2.2.2 Modification of SiC Structures with Dopant

One of the major limitations in the development of wide‐bandgap semiconductors has been finding suitable shallow dopants. Nitrogen is the most popular donor impurity, while Al is favored for p‐type doping. Dopants may be introduced either during epitaxy or by ion implantation. In chemical vapor deposition (CVD), NH and triethylaluminum (TMA) have proved to be suitable dopant source gases for n‐ and p‐type doping, respectively [16]. When N doping is introduced during the growth, carrier concentrations as high as 1018 cm−3 have been realized. Ion implantation with subsequent Ar annealing has yielded electron concentrations as large as 3 × 1019 cm−3 at an N volume concentration of 5 × 1020 cm−3[17].

p‐Type doping is a recognized problem in SiC, although considerable progress has been made. All of the acceptor impurities thus far investigated, namely, Al, B, Ga, and Sc, form deep levels and are difficult to activate, generally requiring a high‐temperature anneal. Al is somewhat difficult to incorporate into the SiC lattice, and high carrier concentrations are difficult to achieve. p‐Type carrier concentrations in the 1019–1020 cm−3 range using TMA in a CVD process on the Si face of 6H SiC has been reported [18]. Growth on the C face resulted only in a hole concentration of 2 × 108 cm3. The carrier concentration was easily controllable down to the low p = 1016 cm−3 range. On the upper end, the observed hole concentration became nonlinear as a function of TMA flow above 1019 cm−3.

The dopants can occupy either hexagonal or cubic sites in the more complex SiC polytypes. These different environments give rise to different binding energies, and care must be taken when deconvolving the separate contributions from Hall data. Analyzing several samples, it was confirmed that the relative abundance of the various N dopant levels corresponded to the ratio of available binding sites. That is, in 4H‐SiC, an equal number of donors occupy cubic sites and hexagonal sites. In 6H‐SiC, the ratio is 2 : 1, reflecting the fact that two‐thirds of the bonding is cubic. In 6H‐SiC, the measured ionization energy of the hexagonal site was 85.5 meV, while the cubic sites were 125 meV (h and k1, k2, respectively, in Figure 1.5 b). For 4H‐SiC, the hexagonal and cubic binding energies were measured to be 45 and 100 meV, respectively. In 3C‐SiC, a value of 48 meV for the lone cubic site was determined. Typical compensation values were 1–2 orders of magnitude below the observed electron concentration.

1.2.3 III–V Nitride‐Based Structure

The III–V nitrides have long been viewed as a promising system for optoelectronic applications in the blue and ultraviolet (UV) wavelengths and, more recently, as a high‐temperature, high‐power semiconductor with electronic properties potentially superior to SiC; however, progress in the nitrides has been much slower than that in SiC and ZnSe. Since GaN development presently lags behind that of ZnSe, many research groups have overlooked the long‐term advantages of the nitrides for emitting and detecting applications.

The wurtzite nitride polytypes form a continuous alloy system whose direct room temperature (RT) bandgaps range from 6.2 eV in AlN to 3.4 eV in GaN. The high thermal conductivity and superior stability of the nitrides and their substrates should eventually allow higher power laser operation with less rapid degradation than ZnSe.

1.2.3.1 Fundamental Properties of GaN and AlN

GaN and AlN have a smaller lattice mismatch than that of any of the ZnSe alloys, which permits greater range and flexibility in heterostructure design. A comparison of some important properties of GaN and AlN semiconductors is shown in Table 1.2.

Table 1.2 Some important properties of III–V nitride semiconductors.

Wurtzite polytype

Zinc‐blende polytype

GaN

Bandgap energy

E

g

, (200 K) = 3.39 eV

E

g

(300 K) = 3.2–3.3 eV

Temperature coefficient

d

E

g

/d

T

 = −6.0 × 10–4 eV K

−1

Lattice constant

a

 = 3.189Å

c

 = 5.185 Å

a

 = 4.52 Å

Thermal expansion

Δ

a

/

a

 = 5.59 × 10

−6

 K Δ

c

/

c

 = 3.17 × 10

−6

 K

Thermal conductivity

K

 = 1.3 W cm

−1

 K

−1

AlN

Bandgap energy

E

g

(300 K) = 6.2 eV

E

g

(300 K) = 5.11 eV

Lattice constant

a

 = 3.112Å

c

 = 4.982 Å

a

 = 4.38 Å

Thermal expansion

Δ

a

/

a

 = 4.2 × 10

−6

 K Δ

c

/

c

 = 5.3 × 10

−6

 K

Thermal conductivity

K

 = 2 W cm

−1

 K

−1

1.2.3.2 Nitride Crystal Growth

The earliest investigations of III–V nitrides were made on small crystals or powder samples. Johnson et al. [19], in what we believe to be the earliest report of GaN, first described the conversion of metallic Ga in a NH3 stream into GaN via the reaction:

The property of GaN produced by this technique was not up to the mark. Hence, nearly every crystal growth technique, substrate type, and orientation has been tried in an effort to grow high‐quality III–V nitride thin films. Maruska and Tietjen grew the first single‐crystal epitaxial GaN thin films by vapor transport [20]. In their method, HCl vapor flowed over a Ga melt, causing the formation of GaCl, which was transported downstream. At the substrate, the GaCl mixed with NH3, resulting in the following chemical reaction [21]:

Maruska and Tietjens's approach was an early version of the modern‐day metalorganic vapor‐phase epitaxy (MOVPE) GaN growth technique. In MOVPE, trimethylgallium (TMG), TMA, and trimethylindium (TMI) react with NH3, at a substrate which is heated to roughly 1000 °C [22].

A disadvantage of the MOVPE approach is the high substrate temperature necessary to thermally dissociate NH3. Due to thermal mismatch with all of the available substrates, post‐growth cooling introduces significant amounts of strain and defects into the nitride film.

In an effort to reduce substrate temperatures, many groups have begun exploring a molecular‐beam epitaxy (MBE) approach in which the reactive nitrogen is supplied by microwave plasma excitation [23,24]. This has been made possible by the commercial development of compact electron–cyclotron–resonance (ECR) microwave plasma sources such as the Wavemat MPDR 610 and ASTEX CECR. These sources use a coaxial or cylindrical cavity geometry to efficiently couple microwave energy (2.45 GHz) into the nitrogen discharge region. The plasma stream is diffusive and neutral, providing atomic, molecular, and ionic N radicals to the growth surface.

1.2.3.3 Polytypism in the III–V Nitrides

GaN and AlN are all most commonly observed as the wurtzite 2H polytype (Figure 1.6a), but each can also crystallize in a metastable zinc‐blende 3C structure Figure 1.6 b) [25,26]. In general, wurtzite material grows on hexagonal substrates, while zinc blende can be grown on cubic substrates. The exception is the sapphire (0001) and zinc‐blende (111) faces, which are normal to the stacking direction, and are therefore polytype neutral.

Figure 1.6 Crystal structures of the (a) GaN wurtzite (2H) and (b) zinc‐blende (3C) polytypes.

1.2.3.4 Electrical Properties of Undoped Nitride Thin films

Using improved crystal growth techniques, researchers have succeeded in reducing the background electron concentration to 1016 cm−3. High GaN bulk mobility of μm = 600 and 1500 cm2 V−1 s−1 at 300 and 77 K, was reported, respectively, in an unintentionally doped sample having n = 4 × 1016 cm−3. AlN is always observed to be insulating, even when doped, almost certainly because its donor, acceptor, and defect levels all lie deep within the bandgap.

1.2.3.5 Properties of Doped GaN

Both p‐type and n‐type GaN doping has been the major catalyst of the rising interest in the nitrides. At first, Akasaki et al. [27] observed that compensated Mg‐doped GaN could be converted into conductive p‐type material by low‐energy electron‐beam irradiation (LEEBI). This result was improved by Nakamura et al. [28] to achieve GaN with p = 3 × 1018 cm−3 and a resistivity of 0.2 Ω cm. A model has been proposed [29] for describing H acceptor compensation in GaN in which Mg–H defect complexes are converted to conventional acceptor impurities by annealing or LEEBI. Due to the large binding energy (i.e. 150–200 meV) of Mg and possible residual H contamination, acceptor activation ratios of only 10−2–10−3 are typically achieved. Thus, large amounts of Mg must be incorporated to obtain high doping levels in GaN. Work aimed at improving Mg activation or finding a better acceptor is needed.

It was reported that the carrier concentrations of Si‐doped GaN grown by MOVPE were in the range of 1017 to 2 × 1019 cm−3, while Ge doping produced material with electron concentrations of 7 × 1016 to 1019 cm−3[30]. A linear variation in the electron concentration as a function of both the SiH4 and GeH4 flow rates was observed across the entire experimental range (Figure 1.7). Ge incorporation was roughly an order of magnitude less efficient than Si, as judged by the larger GeH4 flow rates required to obtain similar electron concentrations.

Figure 1.7 MOVPE (a) Si and (b) Ge incorporation rates as a function of gas flow. Both dopants are well behaved, with linear flow versus active donor incorporation rates; however, GeH4, requires a factor of 10 higher flow to obtain the same doping level.

Source: Nakamura et al. 1992 [30]. Redrawn with permission of IOP.

1.2.4 Alloys and Heterostructures

Most semiconductor devices are optimized by heterojunctions, which are commonly achieved through the use of alloys. GaN‐based technology depends heavily on its alloys with AlN and possibly with InN.

1.2.4.1 GaInN

One of the major issues for better power efficiency is the strain control of epitaxial films that compose the LED's active region structure [9]. For example, having a strain‐relaxed multiple quantum well (MQW) active region reduces the quantum‐confined Stark effect (QCSE) in the quantum wells (QWs) and leads to a higher radiative efficiency [31]. An electron–hole recombination will proceed more rapidly if the coupling between the initial and final state is stronger. To control strain in LED structures, one typical method is to use a strain‐relieving layer located beneath the active region [32]. A GaInN underlayer can reduce strain in QWs in a simple and effective way, resulting in a decrease in the QCSE [33]. Growing a GaInN layer underneath an MQW active region creates tensile strain in the following GaN quantum barrier (QB) and thus reduces the compressive strain in the GaInN. QW grown on top of the QB layer leads to a lower piezoelectric field in the QW and to enhance radiative efficiency. Research groups, having grown GaInN underlayers in GaInN LEDs, found several typical trends including (i) a decreased blueshift of the peak wavelength as the injection current increases, (ii) a reduced QCSE, and (iii) a reduced efficiency droop at high currents [32,33].

Figure 1.8 Schematic cross‐section of 4H‐SiC lateral JFET.

Source: Redrawn from [34].

1.3 Devices of Wide‐Bandgap Semiconductors

1.3.1 SiC in Junction Field‐Effect Transistors (JFETs)

There is growing interest in 4H‐SiC because of its larger bandgap energy and higher electron mobility (950 cm2 V−1 s−1 perpendicular to the c‐axis and 1150 cm−2 V−1 s−1 parallel to the c‐axis) as compared with 6H‐SiC, and its commercial availability in wafer sizes up to 6 in. in diameter. Depletion‐mode 4H‐SiC n‐channel JFETs were designed for low‐voltage and good characteristics at temperatures ranging from RT up to 600 °C in air [34]. The schematic of the device, shown in Figure 1.8, was a p‐type 4H‐SiC wafer substrate on which three epitaxial layers were grown: firstly a 5‐μm‐thick lightly doped p‐type (p−) layer, followed by a 300‐nm‐thick n‐type (n) layer, and finally a 200‐nm‐thick heavily doped p‐type (p+) layer [34]. The p+ layer is used to form the gate electrode, whereas the n layer comprises the channel region of the JFET. The thickness and dopant concentration of the n layer set the threshold voltage (VT) of the transistor. Then a 1‐μm‐thick SiO2 masking layer was deposited by plasma‐enhanced chemical vapor deposition (PECVD) and patterned to expose the source and drain regions to nitrogen implantation at 600 °C to form heavily doped n‐type (n+) regions required for practically ohmic metallic contacts. Subsequently, a multilayered stack of 50 nm titanium (Ti), 100 nm nickel (Ni), and 50 nm titanium–tungsten (TiW, 10% Ti, 90% W) was deposited and patterned via liftoff to form the metal contacts.

Figure 1.9 Temperature dependence of specific contact resistance (ρc) for a Ti/Ni/TiW metal stack on n+ 4H‐SiC.

Source: Chang et al. 1971 [35]. Redrawn with permission of Elsevier.

Figure 1.10 Measured IDS–VDS characteristics of 4H‐SiC n‐channel JFET with W/L = 100/10 μm. (a) At 600 °C, for different values of VGS. (b) At various temperatures, for VGS = 0 V.

Source: Malhan et al. 2009 [36]. Redrawn with permission of John Wiley & Sons.

Ti/Ni/TiW metal stacks are used to form ohmic contacts to n‐type 4H‐SiC with specific contact resistance of 1.14 × 10−3 Ω cm2 at 600 °C. This contact is rectifying (i.e. a Schottky contact) and becomes ohmic after rapid thermal annealing (RTA).

1.3.1.1 Specific Contact Resistance (ρc)

Figure 1.9 shows how ρc depends on temperature. It decreases slightly with increasing temperature in the range from 25 to 400 °C due to the increasing average electron kinetic energy and hence current density [35]. However, it increases with increasing temperature in the range from 400 to 600 °C, due to thermal degradation of the metal contacts.

1 I–V Characteristics

Figure 1.10a,b shows how the drain current versus drain‐to‐source voltage (IDS–VDS) curve for gate‐source voltage (VGS) equal to 0 V changes with temperature. Despite the built‐in voltage decreases by approximately 0.5 V [36], the effective width of the channel becomes wider from 25 to 600 °C. A monotonic decrease in drain saturation current (IDsat) with increasing temperature is observed. This can be attributed to the decrease in electron mobility at elevated temperatures, which follows a power law [37]. This decrease also causes specific on resistance (Ron,sp) to increase to 280.2 mΩ cm2 at 600 °C.

The off‐state current (Ioff) for VGS = −9 V increases from 6.31 × 10−9 A to 1.97 × 10−7 A as the temperature increases from RT to 600 °C, due to increased intrinsic carrier concentration [37]. However, the increase in Ioff is significantly larger than theoretically predicted, suggesting the presence of trap states (e.g. associated with crystalline defects caused by ion implantation). The saturation (VDS = 20 V) on‐current (VGS = 0 V) to off‐current (VGS = −9 V) ratio IDsat/Ioff is 2.66 × 105 at RT and decreases to 1.53 × 103 at 600 °C. This is in contrast to the 6H‐SiC n‐channel JFET with W/L = 200/10 μm reported by National Aeronautics and Space Administration (