Incremental Data Converters for Sensor Interfaces E-Book

Chia-Hung Chen

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 218

Veröffentlichungsjahr: 2023

Beschreibung

Comprehensive resource discussing operating principles, available architectures, and design of micropower incremental analog-to-digital converters (IADCs) Incremental Data Converters for Sensor Interfaces describes the motivation for using incremental analog-to-digital converters (IADCs), including the theoretical foundations of their operation, the trade-offs in their use, and the practical issues in the circuit analysis and design of IADCs. The text covers core foundational knowledge such as the key algorithms used, circuits for single-stage and multi-stage IADCs, the design of the digital post filters for single- and multi-stage IADCs, IADC applications in measurement and instrumentation, medicine, imagers, and IoT, and comparison of delta-sigma (D-S) and incremental ADCs (IADCs) in terms of accuracy, latency, and multiplexed operation. To aid in reader comprehension and serve as an excellent classroom learning resource, Incremental Data Converters for Sensor Interfaces includes in-text problems and homework for graduate studies, along with helpful computer codes in MATLAB and Simulink. Additional topics covered in Incremental Data Converters for Sensor Interfaces include: * Sensors and sensor interfaces, mixed-mode (analog-digital) communication and consumer signal chains, and ADC algorithms * Quantization errors vs. quantization noise, and performance parameters and figures of merit, including resolution, linearity, accuracy, bandwidth, latency, and power dissipation * Nyquist-rate and oversampling data converters, noise-shaping ADCs, and basic architectures for IADCs, including single- and multi-stage designs and discrete vs. continuous-time operation * Loop filter design, D/A converter design, dynamic element matching and digital calibration, and quantizer design With comprehensive coverage of foundational knowledge surrounding the subject, various real-world examples, and helpful learning aids, Incremental Data Converters for Sensor Interfaces is an essential resource for graduate students in electronics programs, along with industrial circuit design professionals.

Leseprobe

Table of Contents

Cover

Table of Contents

Title Page

Copyright

About the Authors

Preface

References

Abstract & Keywords

Abstract

Keywords

1 Fundamentals of Analog‐to‐Digital Data Converters (ADCs)

1.1 Performance Parameters for Analog‐to‐Digital Converters

1.2 Algorithms and Architectures for Analog‐to‐Digital Converters

References

2 Delta‐Sigma ADCs

2.1 Sampled‐Data ADCs

2.2 Loop Filter Structures and Circuits for Sampled‐Data ADCs

2.3 Optimization of Zeros and Poles for Sampled‐Data ADCs

2.4 Limitations on the Performance of Sampled‐Data ADCs

2.5 Multistage Sampled‐Data ADCs

2.6 Continuous‐Time ADCs

2.7 Advantages and Limitations of Continuous‐Time ADCs

References

Notes

3 Single‐Stage Incremental Analog‐to‐Digital Converters

3.1 The First‐Order IADC

3.2 Higher‐Order Single‐Stage IADCs

3.3 Decimation Filter and the Overall Design of IADCs

3.4 Estimation of Power Consumption

References

4 Multistage and Extended Counting Incremental Analog‐to‐Digital Converters

4.1 Multistage Noise Shaping (MASH) Incremental ADCs

4.2 Design Examples

4.3 The Zoom Incremental ADC

4.4 Zoom ADC Design Example

References

5 Design Examples

5.1 A Third‐Order 22‐Bit IADC

5.2 A 16‐Bit Multistep IADC with Single‐Opamp Multi‐Slope Extended Counting

5.3 Multistep IADCs

5.4 A Hybrid Continuous‐Time Incremental and SAR Two‐Step ADC with 90.5 dB Dynamic Range Over 1 MHz Bandwidth

5.5 A Multistage Multistep IADC

References

Index

End User License Agreement

List of Tables

Chapter 2

Table 2.1 Optimum zero locations and SQNR improvements.

Chapter 4

Table 4.1 Comparison with recent hybrid and single‐loop IADCs.

Chapter 5

Table 5.1 Performance summary and comparison.

Table 5.2 Performance summary and comparison with state‐of‐art CT‐IADCs.

Table 5.3 Measured performance summary and comparison.

List of Illustrations

Chapter 1

Figure 1.1 Analog front‐end for sensor interface.

Figure 1.2 (a) The symbol of an ADC; (b) a simple ADC model.

Figure 1.3 Normalized analog‐to‐digital converter transfer and error curves ...

Figure 1.4 Operating regions of ADCs.

Figure 1.5 A dual‐slope analog‐to‐digital converter.

Figure 1.6 (a) The delta‐sigma ADC; (b) Quantizer model.

Figure 1.7 Sampled‐date integrator (accumulator).

Figure 1.8 A first‐order ΔΣ ADC (MOD1).

Figure 1.9 The frequency response of |NTF|

2

.

Figure 1.10 A second‐order ΔΣ ADC.

Figure 1.11 Dithering.

Figure 1.12 The successful approximation ADC.

Figure 1.13 5‐bit SAR ADC implementation.

Figure 1.14 Flash A/D converter.

Chapter 2

Figure 2.1 ΔΣ noise filtering loop.

Figure 2.2 The first‐order ΔΣ ADC (MOD1).

Figure 2.3 The second‐order ΔΣ ADC (MOD2).

Figure 2.4 The estimated SQNR for ΔΣ ADCs: (a) with 1‐bit quantizer; (b) wit...

Figure 2.5 Block diagram of a MOD4 ΔΣ ADC.

Figure 2.6 The low‐distortion CIFF structure.

Figure 2.7 The simplified circuit diagram of a second‐order ΔΣ ADC (MOD2).

Figure 2.8 The differential circuit diagram of the first integrator of the M...

Figure 2.9 |NTF|

2

frequency responses for the MOD2 ΔΣ ADC with and without z...

Figure 2.10 Bootstrapped switch (a) basic concept and (b) implementation [7]...

Figure 2.11 Idle tone patterns (a) for OSR = 32; (b) OSR = 64.

Figure 2.12 Block diagram of a MASH ΔΣ ADC.

Figure 2.13 Block diagram of a CT MOD2 ΔΣ ADC.

Figure 2.14 CT ΔΣ ADC scheme.

Figure 2.15 The impulse responses of the NRZ and RZ DACs.

Figure 2.16 Closed‐ and open‐loop models of a CT ΔΣ ADC.

Figure 2.17 Closed‐loop model of the CTMOD1 ΔΣ ADC.

Figure 2.18 Design of a CTMOD2: (a) block diagram and (b) open‐loop branch....

Figure 2.19 (a) Block diagram of the CT ΔΣ ADC; (b), (c), and (d) the transf...

Figure 2.20 The signal gain response and impulse response of a CT MOD2 ADC....

Figure 2.21 Excess loop delay correction in a CT MOD2.

Figure 2.22 Resistor tuning circuit.

Figure 2.23 Jitter and ISI effects in NRZ, RZ and DRZ DAC signals. (a) Jitte...

Chapter 3

Figure 3.1

z

‐domain models of integrators with reset: (a) a delay‐free integ...

Figure 3.2 (a) The

z

‐domain model of a single‐stage first‐order IADC with a ...

Figure 3.3 The

z

‐domain model of a single‐stage IADC2 with a low‐distortion ...

Figure 3.4 The conventional single‐stage ΔΣ ADC.

Figure 3.5 SQNR versus OSR for a single‐bit (

L

 = 2) modulator from first‐ord...

Figure 3.6 Signal transfer function of IADCs from first‐order to fifth‐order...

Figure 3.7 IADC1 with a FIR DAC.

Figure 3.8 (a) The decimation filter of a conventional ΔΣ ADC. (b) A Hogenau...

Figure 3.9 Optimal impulse responses of third‐order IADC digital filters.

Figure 3.10 An extended‐counting ADC of 2–0. Source: Adapted from Rombouts e...

Figure 3.11 A switched‐capacitor integrator circuit in integration phase.

Chapter 4

Figure 4.1 A 1‐1 MASH modulator.

Figure 4.2 A 1‐1 MASH IADC.

Figure 4.3 A 2‐1 MASH incremental ADC.

Figure 4.4 (a) Residue voltage acquisition. (b) An IADC using a Nyquist‐rate...

Figure 4.5 (a) An example of IADC with extended counting using hardware shar...

Figure 4.6 (a) SQNR comparison.of the binary‐extended counting scheme wi...

Figure 4.7 (a) Serial charge‐redistribution DAC.(b) Illustration of DAC ...

Figure 4.8 System‐level

z

‐domain block diagram of the IADC1 with SAR binary‐...

Figure 4.9 Simplified timing diagram and the timing generator.

Figure 4.10 (a) Equivalent block diagram during step 1: IADC1 with an FIR fe...

Figure 4.11 (a) Step 1: single‐ended switched‐capacitor circuit implementati...

Figure 4.12 (a) Switched‐capacitor circuits implementation of Step 2: reusin...

Figure 4.13 (a) Simulated SQNR versus IADC1 comparator's offset voltage when...

Figure 4.14 (a) Two‐stage opamp circuit. Simulations show 86 dB dc gain, 20 ...

Figure 4.15 Measured spectra at signal frequencies: (a) 170 Hz and (b) 800 H...

Figure 4.16 (a) Measured SNR and SNDR versus differential voltage amplitude....

Figure 4.17 (a) Measured PSD when chopper was turned on or off. (b) Measured...

Figure 4.18 The block diagram of a 0–L incremental ADC.

Figure 4.19 The block diagram of a 0–L zoom ADC.

Figure 4.20 DAC output waveforms for zoom IADCs: (a) with single‐bit quantiz...

Figure 4.21 (a) Concept diagram of the zoom 2nd‐order IADC with 1‐bit quanti...

Figure 4.22 (a) Measured output spectrum of the zoom IADC with DEM on. (b) M...

Chapter 5

Figure 5.1 Block diagram of the 22‐bit third‐order IADC.

Figure 5.2 Single‐ended switched‐capacitor schematic.

Figure 5.3 Quantization noise power as a function of

u

/

V

ref

for

M

 = 1024.

Figure 5.4 The rotating capacitor input circuit. The dotted frames contain r...

Figure 5.5 The input integrator with offset compensation using fractal seque...

Figure 5.6 Integrator output voltages after fractal sequencing.

Figure 5.7 The gain response of the decimation filter.

Figure 5.8 Block diagram of (a) a conceptual IADC and (b) a first‐order IADC...

Figure 5.9 (a) Block diagram of the proposed multistep IADC with multi‐slope...

Figure 5.10 (a) First step: a first‐order IADC with FIR feedback path. (b) S...

Figure 5.11 Comparison of the proposed architecture with single‐step IADCs. ...

Figure 5.12 (a) Simulated waveform of the residue at the integrator output d...

Figure 5.13 Chip micrograph of the prototype IADC.

Figure 5.14 Measured PSDs for the three steps with a −0.44 dBFS sine wave in...

Figure 5.15 Measured SNR/SNDR versus the input amplitude for 170 and 800 Hz ...

Figure 5.16 Measured spectra with the chopper turned on versus chopper turne...

Figure 5.17 Measured output noise of the prototype IADC with dc input.

Figure 5.18 Measured INL/DNL in 16‐bit accuracy LSBs.

Figure 5.19 The proposed IADC2 in two‐step operation. (a) First step. (b) Se...

Figure 5.20 (a) Simulated SQNR versus OSR of the first step (

M

1

). The input ...

Figure 5.21 The equivalent single‐ended switched‐capacitor circuits implemen...

Figure 5.22 (a) The detailed timing diagrams for the two‐step IADC2. (b) The...

Figure 5.23 Measured spectra. The dotted line is for the first step only (IA...

Figure 5.24 Measured spectra. (a) DWA turned on versus off with 1 V

PP

(−6.8 ...

Figure 5.25 The IADC3 in two‐step operation. (a) First step. (b) Second step...

Figure 5.26 (a) System diagram. (b) CT to DT transformation.

Figure 5.27 The ZOH

s

–

z

mapping.

Figure 5.28 The circuit diagram of the hybrid IADC.

Figure 5.29 The second stage SAR ADC of the two‐step hybrid IADC.

Figure 5.30 (a) Output spectrum after Step 1; (b) output spectrum after Step...

Figure 5.31 Die micrograph of the hybrid two‐step IADC.

Figure 5.32 The measured SNR and SNDR at

f

clk

 = 64 MHz, OSR = 32,

f

in

 = 990....

Figure 5.33 Measured output spectra: (a) with full‐scale input; (b) with −80...

Figure 5.34 (a) An example of a MASH 2‐1 IADC. The interstage gain

G

I

is not...

Figure 5.35 The digital ECL logic and decimation filter in a conventional MA...

Figure 5.36 (a) The second‐step operation of the proposed two‐step MASH2‐1. ...

Figure 5.37 (a) SQNR versus the OSR of the first step (

M

1

) within a total OS...

Figure 5.38 (a) The complete digital filter to reconstruct the proposed IADC...

Figure 5.39 The switched‐capacitor circuits of the proposed IADC2‐1‐2. The f...

Figure 5.40 The second‐step switched‐capacitor circuits of the proposed IADC...

Figure 5.41 Circuits to generate the timing control and two‐phase non‐overla...

Figure 5.42 (a) Simulated SQNR loss versus matching error. (b) Simulated SQN...

Figure 5.43 The Miller‐compensated two‐stage opamp in the integrator.

Figure 5.44 The passive adder and comparator circuits.

Figure 5.45 Microphoto of the proposed IADC2‐1‐2 silicon prototype.

Figure 5.46 Measured spectra for 1 kHz (right) and 17 kHz (left) input sine ...

Figure 5.47 Feedback DAC DWA calibration turn‐on versus turn‐off.

Figure 5.48 Measured SNDR versus input amplitude.

Figure 5.49 (a) Measured INL and DNL. (b) Power breakdown of each building b...

Guide

Cover

Series Page

Table of Contents

Title Page

Copyright

About the Authors

Preface

Abstract & Keywords

Begin Reading

Index

End User License Agreement

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Ahmet Murat Tekalp

Incremental Data Converters for Sensor Interfaces

Chia‐Hung Chen

National Yang Ming Chiao Tung UniversityHsinchu, Taiwan

Gabor C. Temes

Oregon State UniversityCorvallis, OR, USA

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About the Authors

Chia‐Hung Chen received his B.S. degree in nuclear engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1994, and his M.S. degree in electrical engineering from Columbia University, New York, in 2003. He received his Ph.D. from Oregon State University, Corvallis, OR, in 2013.

Dr. Chen worked at start‐up companies in Taiwan from 2003 to 2009, designing audio codec circuits, DC–DC power converters, and phase locked loops (PLLs). In 2013–2014, he was with MediaTek, Woburn, MA. From 2016 to 2018, he was a technical manager at EgisTec, designing fingerprint sensors and ADCs. He is currently an assistant professor at the Department of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan. He has been serving as a member of the technical program committee (TPC) for the IEEE Custom Integrated Circuits Conference (CICC) since 2021 and VLSI Symposium on Technology, Systems and Automation (VLSI‐TSA) since 2022. His research interests are in the design of precision analog circuits and energy‐efficient data converters.

Gabor C. Temes (SM'66–F'73–LF'98) received undergraduate degrees from the Technical University of Budapest and Eötvös University, Budapest, Hungary, in 1952 and 1955, respectively. He received PhD degree in electrical engineering from the University of Ottawa, ON, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest, Budapest, Hungary, in 1991.

Dr. Temes was Editor of the IEEE Transactions on Circuit Theory and Vice President of the IEEE Circuits and Systems (CAS) Society. In 1968 and 1981, he was cowinner of the IEEE CAS Darlington Award, and in 1984 winner of the Centennial Medal of the IEEE. He received the Andrew Chi Prize Award of the IEEE Instrumentation and Measurement Society in 1985, the Education Award of the IEEE CAS Society in 1987, and the Technical Achievement Award of the IEEE CAS Society in 1989. He received the IEEE Graduate Teaching Award in 1998, and the IEEE Millennium Medal, as well as the IEEE CAS Golden Jubilee Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 SIA‐SRC University Researcher Award. He is a member of the US National Academy of Engineering and the US National Academy of Inventors.

Preface

Sensors are playing a rapidly increasing role in our lives. They are used in instrumentation and measurement applications, in medicine as biosensors, in automotive controls, on the Internet of Things, in surveillance systems, in imagers, and in many other applications. The sensor outputs are physical analog signals and therefore require accurate analog‐to‐digital converters (ADCs) to enable their digital signal processing. Some sensor systems, such as imagers or neural recorders, contain dozens or even hundreds of sensors, each requiring data conversion. It is then desirable to share a single ADC among many of these sensors.

Historically, the accurate conversion of slow signals such as those measured by a digital voltmeter was performed by single‐ or dual‐slope Nyquist‐rate ADCs. These ADCs converted analog samples one by one into their digital equivalents. However, for even moderately fast signals, the long conversion time made these converters impractical. A noise filtering (“noise shaping”) ADC, such as the delta‐sigma ADC, provides fast and accurate conversion for streaming signals, but it cannot be used for measurement applications and cannot be multiplexed among several sensor channels. ΔΣ ADCs also suffer from several practical issues, such as the long latency between analog input and digital output, which makes them unsuitable for robotic and other feedback system applications. They also need complicated digital post filtering and may suffer from idle tones, instability, and other imperfections.

It was shown by R. J. van de Plassche in 1978 [1] that a first‐order ΔΣ ADC can be converted into a highly accurate Nyquist‐rate one by periodically resetting its analog and digital memory elements. He used bipolar current‐mode circuitry in the realization of his new scheme with two chips. There was no immediate follow‐up to his paper. Nine years later, an MOS‐integrated version of the modified first‐order ΔΣ ADC was implemented with switched‐capacitor stages [2], and a year later, a second‐order cascade realization was published [3]. Since the digital word was obtained by collecting increments of the input signals, the early authors named the device an incremental analog‐to‐digital converter (IADC). After these papers appeared, the many potential applications of this new type of converter became widely recognized. Soon, hundreds of papers were published which described a variety of innovative architectures and circuits. These extended the speed and accuracy of these IADCs. This resulted in important new applications and thus in the fabrication of many millions more IADCs both in embedded and stand‐alone forms.

The theory and design techniques of IADCs have now been discussed in many research and tutorial papers and even book chapters [4, 5]. In spite of this exposure, the authors feel that the subject material is now extensive and mature enough to be exposed in a book of its own, which collects this information and can explain the theory and the many practical aspects of IADC design in sufficient detail.

The book is primarily aimed at industrial engineers, especially those involved in the design of analog‐ and mixed‐mode (analog/digital) integrated circuits. However, the authors also used its material to teach short courses for industry, tutorial lectures, and graduate courses.

We thank the reviewers for their valuable suggestions and the contributions of Dr. Yi Zhang of Analog Devices Inc. to this work.

Hsin Chu, Taiwan, 01 September 2023Corvallis, Oregon, 01 September 2023

Chia‐Hung Chen

Gabor C. Temes

References

1 R. J. van de Plassche, “A sigma‐delta modulator as an A/D converter,”

IEEE Transactions on Circuits and Systems

, vol. 25, no. 7, pp. 510–518, July 1978.

2 J. Robert et al., “A 16‐bit low‐voltage A/D converter,”

IEEE Journal of Solid‐State Circuits

, vol. 22, no. 2, pp. 157–163, April 1987.

3 J. Robert and Ph. Deval, “A second‐order high‐resolution incremental A/D converter with offset and charge injection compensation,”

IEEE Journal of Solid‐State Circuits

, vol. 23, no. 3, pp. 736–741, March 1988.

4 C.‐H. Chen, Y. Zhang, T. He, and Temes, G. C., “Micro‐power incremental analog‐to‐digital converters,” in

Efficient Sensor Interfaces, Advanced Amplifiers and Low Power RF Systems

, Springer, 2015.

https://doi.org/10.1007/978-3-319-21185-5_2

.

5 S. Pavan, R. Schreier, and G. C Temes, “Incremental analog‐to‐digital converters,” in

Understanding Delta‐Sigma Data Converters

, Wiley, 2017.

Abstract & Keywords

Abstract

Integrated sensor systems‐on‐chip require high‐accuracy, low‐latency analog‐to‐digital converters (ADCs) which can interface with wide input‐range signals and often be shared among multiple sensor channels. Incremental analog‐to‐digital converters (IADCs) are often the best choice for such role. They are obtained by adding a simultaneous reset to the analog modulators and digital filters of a ΔΣ ADC. They are Nyquist‐rate ADCs which use noise shaping to convert a finite number of analog samples into a single digital word. They retain most advantages of the ΔΣ ADCs and are much easier to be multiplexed, with shorter latency and simpler digital filters. In this book, the operation and design theory of IADCs is discussed. The advantages and disadvantages of IADCs and ΔΣ ADCs are also explained. It is shown how ΔΣ modulator architectures, such as multistage noise shaping (MASH), can also be used in the design of IADCs. A hybrid approach which combines an IADC with a Nyquist‐rate ADC is introduced to further leverage the advantages of reset operation. The analysis and design of extended counting and hardware recycling schemes are then discussed. Five design examples are discussed, including a single‐loop IADC, a multistep IADC, an IADC with multislope extended counting, a hybrid continuous‐time IADC with a SAR, and a multistage multistep IADC.

Keywords

delta sigma (ΔΣ) modulator

low latency

incremental analog‐to‐digital converters

multistage

multistep

extended counting

decimation filter

sensor interface

measurement and instrumentation

1Fundamentals of Analog‐to‐Digital Data Converters (ADCs)

Sensors are devices which convert physical phenomena (sound, light, temperature, and others) into another signal, usually an electrical one. There are hundreds of applications for sensors in measurements and instrumentation, biomedical and environmental applications, Internet of Things (IoT), image sensors, and many more. In most cases, the electric output of the sensor is transmitted to a computer through an analog interface. This interface (often called analog front‐endorAFE) may be used to amplify the sensor's output signal and to filter out unwanted noise from it. In most cases, it is followed by an analog‐to‐digital data converter (ADC) used to convert the AFE output into a digital form suitable for digital signal processing by a follow‐up computer. The detailed structure of the AFE depends on the properties of the sensor output signal and on the application of the sensor. Figure 1.1 illustrates the block diagram of a sensor and its AFE. In this chapter, the fundamental principles of ADC are discussed, and an introduction to some high‐accuracy data converters will be given.

1.1 Performance Parameters for Analog‐to‐Digital Converters

The ADC is often the most complex and critical part of the signal chain. Its specifications, as for those of the AFE, may vary widely, depending on the sensor signal and on the application of the device. Figure 1.2 illustrates the operation of an ADC. The input is an analog signal Vin, while the digital output Dout is a sequence of numbers which is the digital representation of Vin. The input–output relation is

(1.1)

Here, Vref is the reference voltage of the converter, and Vq is the quantization error. The quantization error cannot be avoided, since Vin may take on any value within its range, while the digital signal is the sum of its bits (binary‐weighted digits), and hence, it can only assume a finite number of values. The symbol of the ADC is shown in Figure 1.2, along with a simple model based on Eq. (1.1).

Figure 1.1 Analog front‐end for sensor interface.

Figure 1.2 (a) The symbol of an ADC; (b) a simple ADC model.

Figure 1.3 illustrates the normalized input–output characteristics of two M‐level ADCs. Vref = 1 V is assumed. Both ADCs are bipolar, i.e. able to convert both positive and negative inputs. Both have M steps and M + 1 levels. The resolution of an M‐step converter in bits is given by N = log2 (M + 1). The 45° line k · y shows the accurate output values which an infinite resolution ADC would provide for Vref = 1 V. The least significant bit value in the figure is VLSB = Δ = 2. The figure shows that in a range of the input range −(M + 1) <y < (M + 1), the magnitude of quantization error e = v − y satisfies |e| <Δ/2 = 1. This is the linear input range of the ADC.

Figure 1.3