Integrated Nanophotonics E-Book

• Herausgeber: Wiley-VCH GmbH
• Kategorie: Fachliteratur
• Sprache: Englisch

Seitenzahl: 656

Veröffentlichungsjahr: 2023

Beschreibung

Integrated Nanophotonics

Helps readers understand the important advances in nanophotonics materials development and their latest applications

This book introduces the current state of and emerging trends in the development of integrated nanophotonics. Written by three well-qualified authors, it systematically reviews the knowledge of integrated nanophotonics from theory to the most recent technological developments. It also covers the applications of integrated nanophotonics in essential areas such as neuromorphic computing, biosensing, and optical communications. Lastly, it brings together the latest advancements in the key principles of photonic integrated circuits, plus the recent advances in tackling the barriers in photonic integrated circuits.

Sample topics included in this comprehensive resource include:

• Platforms for integrated nanophotonics, including lithium niobate nanophotonics, indium phosphide nanophotonics, silicon nanophotonics, and nonlinear optics for integrated photonics
• The devices and technologies for integrated nanophotonics in on-chip light sources, optical packaging of photonic integrated circuits, optical interconnects, and light processing devices
• Applications on neuromorphic computing, biosensing, LIDAR, and computing for AI and artificial neural network and deep learning

Materials scientists, physicists, and physical chemists can use this book to understand the totality of cutting-edge theory, research, and applications in the field of integrated nanophotonics.

Leseprobe

Table of Contents

Cover

Title Page

Copyright

Preface

References

1 Packaging and Test of Photonic Integrated Circuits (PICs)

1.1 Introduction

1.2 Challenges and Specificities of PIC Packaging and Test

1.3 Advances in Optical Coupling Strategies

1.4 Electronic/Photonic Convergence

1.5 Toward an Ecosystem in Test and Assembly of PICs

1.6 Conclusion

Acknowledgments

References

2 The Last Mile Technology of Silicon Photonics Toward Productions and Emerging Applications

2.1 Introduction

2.2 Fiber‐to‐Chip Assembly

2.3 Hybrid Integration of Light Source

2.4 Electronic and Photonic Co‐Packaging

2.5 Outlook

References

3 Integrated Nonlinear Photonics and Emerging Applications

3.1 Introduction

3.2 Supercontinuum

3.3 Optical Frequency Comb

3.4 Nonlinear Wave Mixing

3.5 Conclusion and Perspectives

References

4 Excitation, Generation, Positioning, and Modulation for Quantum Light Sources Integrated on Chip

4.1 Introduction

4.2 Excitation and Orientation of Quantum Emitters

4.3 Chip‐Scale Integration Based on Quantum Emitters

4.4 Deterministically Positioning of Quantum Emitter

4.5 Quantum Light Interaction with Metasurface for Modulation

4.6 Conclusion

References

5 Quantum Light Sources in Two‐Dimensional Materials

5.1 Introduction

5.2 Theory of Quantum Light Sources

5.3 Quantum Light Sources in 2D Materials

5.4 Integration with On‐Chip Components

5.5 Integration with Off‐Chip Components

5.6 Summary and Outlook

Acknowledgments

References

6 Inverse Design for Integrated Photonics Using Deep Neural Network

6.1 Introduction

6.2 Deep Neural Network (DNN) Models

6.3 Deep Learning for Forward Modeling to Predict Optical Response

6.4 Deep Learning for Inverse Modeling to Construct Device Topology

6.5 Deep Learning for Generative Modeling to Produce Device Topology Candidates

6.6 Physics‐informed Neural Networks

6.7 Nanophotonic Power Splitter Design Using Generative Modeling

6.8 Deep Learning Techniques

6.9 Conclusion

References

7 Deep Learning Driven Data Processing, Modeling, and Inverse Design for Nanophotonics

7.1 Introduction

7.2 Artificial Neural Networks and Deep Learning

7.3 Ultrafast Physics Predictions

7.4 Photonics Inverse Design

7.5 Advanced Data Processing for Photonics Applications

7.6 Conclusion and Outlook

References

8 Optical Waveguide of Lithium Niobate Nanophotonics

8.1 Introduction

8.2 Photonics Lithium Niobate

8.3 Nanophotonic Lithium Niobate‐Based Optical Waveguide

8.4 Optical Studies of Nanophotonic Lithium Niobate‐Based Optical Waveguide

8.5 Nanophotonic LiNbO

3

Under Stirrer Time Effect

8.6 Nanophotonic Studies of LiNbO

3

Under Stirrer Time Effect

8.7 Conclusions

References

9 Active, Tunable, and Reconfigurable Nanophotonics

9.1 Introduction

9.2 Liquid Crystal‐Integrated Tunable Devices

9.3 Optically Tunable Devices

9.4 Phase Change Materials‐Based Reconfigurable Devices

9.5 Mechanically Tunable Photonic Devices

9.6 Tunable Photonic Devices with Material Engineering

9.7 Electrically Tunable Photonic Devices

Acknowledgments

References

Index

End User License Agreement

List of Tables

Chapter 1

Table 1.1 Results for the comparison of processes.

Chapter 2

Table 2.1 The major technologies for light source integration.

Chapter 3

Table 3.1 Summary of nonlinear optical signal processing in integrated photo...

Chapter 5

Table 5.1 Exemplary criteria of single‐photon sources for key quantum applic...

Table 5.2 Typical single‐photon sources based on various TMDCs [13].

Table 5.3 Characteristics of defect‐related quantum emitters in h‐BN prepare...

Table 5.4 Comparison of SPEs in graphene, TMDCs, and h‐BN, benchmarking agai...

Table 5.5 Device figure of merit, PL enhancement, lifetime reduction, and Pu...

Chapter 8

Table 8.1 The energy bandgaps, refractive index, optical dielectric constant...

Table 8.2 The LiNbO

3

nanophotonics parameters at 3000 rpm coating speed and ...

Table 8.3 The energy bandgaps, refractive index, and optical dielectric cons...

Table 8.4 Structural parameters of LiNbO

3

nanostructures at different stirre...

Table 8.5 The energy bandgaps and refractive index correspond to grain size ...

List of Illustrations

Chapter 1

Figure 1.1 Typical assembly flow for the packaging of a silicon photonics PI...

Figure 1.2 Typical content of a silicon photonics module (with QSFP chassis)...

Figure 1.3 Edge coupling structure obtained by inverted taper design.

Figure 1.4 Scheme and SEM view of a single polarization grating coupler (SPG...

Figure 1.5 Evanescent coupling between two PICs with adiabatic couplers.

Figure 1.6 Optical on‐wafer test of silicon photonics PICs using a V‐groove ...

Figure 1.7 Wafer‐level test of PICs with edge couplers using reflective glas...

Figure 1.8 Automated probe tester with dedicated test and measurement instru...

Figure 1.9 FEM thermomechanical simulation model of a wire‐bond‐based PIC pa...

Figure 1.10 HF simulation model of a PIC package with the typical S‐paramete...

Figure 1.11 Lensed fiber to silicon photonics chip coupling.

Figure 1.12 Butt coupling assembly of a silicon photonics PIC and a V‐groove...

Figure 1.13 Microlens array assembled on the top a silicon photonics PIC to ...

Figure 1.14 Glass interposer connected to a PIC, using (a) edge coupling app...

Figure 1.15 Gold box package developed within the EU‐founded iPhos project....

Figure 1.16 PIC‐on‐board package developed within the EU‐founded 5G‐PHOS pro...

Figure 1.17 Microoptics assembly of a 400 Gbps Datacom transceiver (MASSTART...

Figure 1.18 Co‐packaging approach: the host chip is surrounded by optical ch...

Figure 1.19 Photonic interposer, showing optical routing between several CMO...

Figure 1.20 Active alignment of a V‐groove array embedding a single‐mode fib...

Figure 1.21 Active and passive techniques for automated optical coupling.

Figure 1.22 (a) Configurations for top camera measuring reference mark of su...

Figure 1.23 Passive coupling of optical fiber to a PIC using V‐groove (a) us...

Figure 1.24 (a) View of a microlens array made of silica, with post‐processe...

Figure 1.25 Passive alignment of an optical flex embedding polymer waveguide...

Figure 1.26 Relaxed tolerance assembly using an optical plug with two reflec...

Figure 1.27 Fraunhofer IZM self‐alignment assembly technique: (a) schematics...

Figure 1.28 Landscape of the main flip chip processes with interconnections ...

Figure 1.29 Cross section of a 25 μm diameter copper bump before reflow with...

Figure 1.30 Example of 50 μm pitch copper pillars (a), copper bumps (b), and...

Figure 1.31 Overview of the different bump and assembly technologies.

Figure 1.32 TSV last process at Fraunhofer IZM (top view and cross‐section)....

Figure 1.33 Overview of TSV mid‐process flow.

Figure 1.34 Fan‐out wafer‐level package structures from different process fl...

Figure 1.35 Massive routing and design for FOWLP, Industrial data center app...

Figure 1.36 Active interposer, (a) INTACT prototype with opened lid to obser...

Figure 1.37 System overviews including photonic interposer, (a) A*STAR schem...

Figure 1.38 (a) Optical and SEM cross section of ring modulator with 10 μm d...

Figure 1.39 (a) Phoxtrot project demonstrator showing the 3D integration con...

Figure 1.40 3D package developed within the EU‐founded PhoxTrot project.

Figure 1.41 PIC under test using built‐in photodetector strategy with a spec...

Figure 1.42 Current measured at the output of various devices, embedded in a...

Figure 1.43 (a) ficonTEC Fiber attach station with input and output feeders....

Figure 1.44 FiconTEC fully automated inline configuration for a photonics se...

Figure 1.45 (a) development setup of the fiber strip and cleave system with ...

Figure 1.46 Through silicon laser soldering experiments performed within the...

Figure 1.47 (a) ficonTEC Software screenshot, (b) System‐health monitoring s...

Chapter 2

Figure 2.1 Fiber‐to‐chip coupling using grating couplers: (a) pig‐tailed, an...

Figure 2.2 Fiber‐to‐chip coupling using edge couplers: (a) lensed fiber with...

Figure 2.3 (a) Typical coupling loss of the suspended edge coupler over C ba...

Figure 2.4 (a) The chip after curing and fixing with the single fibers at bo...

Figure 2.5 (a) Schematic of the LD bonding to the fabricated silicon photoni...

Figure 2.6 (a) Output power of the LD chip as a function of input current. (...

Figure 2.7 A simplified schematic of a BGA Silicon PIC module.

Figure 2.8 Typical scheme of (a) 2.5D and (b) 3D EIC/PIC integration

Figure 2.9 (a) schematic drawing of an arbitrary splitter using 50 : 50 powe...

Chapter 3

Figure 3.1 Schematic diagram of several integrated nonlinear photonic struct...

Figure 3.2 Transparent window of waveguide platforms.

Figure 3.3 (a) Refractive indices and (b) nonlinear‐index coefficient of dif...

Figure 3.4 Different applications based on SCG.

Figure 3.5 History of SCG in integrated waveguide.

Figure 3.6 (a) Representative experimental SCG in the SOI platform with diff...

Figure 3.7 Experimental SCG and coherence in Si

3

N

4

waveguides by T. J. Kippe...

Figure 3.8 Experimental demonstration of SCG in a Ge‐on‐Si waveguide by A. D...

Figure 3.9 (a) SCG in Si

0.2

Ge

0.8

waveguide with different peak power by M. M...

Figure 3.10 Experimentally generated SC spectra and their corresponding cohe...

Figure 3.11 Experimental SC spectra of different peak powers for the TE mode...

Figure 3.12 (a) SC spectrum of TE mode through Ge

11.5

As

24

Se

64.5

waveguide by...

Figure 3.13 Experimental and simulated spectra in the LiNbO

3

waveguide based...

Figure 3.14 Chip‐based OFC technologies. Schematic configurations of devices...

Figure 3.15 History of OFC based on microresonator, SC, EO effect, and MLL....

Figure 3.16 Structures and output spectra of two different types of silica m...

Figure 3.17 Structures and output spectra of chip‐based silicon nitride micr...

Figure 3.18 (a) Microscope image and (b) output spectrum of chip‐based silic...

Figure 3.19 (a) SEM image and (b) OPO spectra for different pump wavelengths...

Figure 3.20 Output spectra of frequency comb based on different material pla...

Figure 3.21 Representative spectra for SC generation based on different mate...

Figure 3.22 Representative spectra for chiped‐based (a) resonant EO comb by ...

Figure 3.23 Representative structures and output spectra of on‐chip MLLs. QC...

Figure 3.24 Different applications based on OFC.

f

rep

and

f

rep

+ δf

...

Figure 3.25 Nonlinearities and corresponding nonlinear mediums used for opti...

Figure 3.26 (a) Schematic illustration of WDM 16‐QAM signal wavelength conve...

Figure 3.27 (a) Concept and operation principle of PAM‐4 wavelength conversi...

Figure 3.28 (a) Conceptual diagram of silicon‐chip‐based instantaneous GVD m...

Figure 3.29 (a) Conceptual block diagram of higher‐order QAM generation usin...

Figure 3.30 (a) Conceptual diagram of optical channel de‐aggregator. (b) Opt...

Figure 3.31 (a) Conceptual diagram of the optical inter‐channel interference...

Figure 3.32 (a) Working principle of the chip‐based all‐optical XOR gate and...

Figure 3.33 (a) Experimental setup of the SFG interferometer. (b) Experiment...

Chapter 4

Figure 4.1 (a) Measurement of polarization states for QDs.(b) Polarizati...

Figure 4.2 (a) Electric field intensities of focused radial component at and...

Figure 4.3 Electric field intensities of focused azimuthal component at and ...

Figure 4.4 (a) Theoretical output patterns of radially polarized and azimuth...

Figure 4.5 (a) Schematic of a colloidal QD emitting confined in the plasmoni...

Figure 4.6 (a) Illustration of filtering the fundamental and first‐order mod...

Figure 4.7 (a) Schematic illustration of the QDs confined between silver fla...

Figure 4.8 (a) Schematic diagram of a 2D piezoelectric actuator for introduc...

Figure 4.9 (a) Schematic of mechanical lift‐off and transferring on patterne...

Figure 4.10 (a) Schematic of hBN for monolithically fabricated emitter and w...

Figure 4.11 (a) Diagram of energy level for negatively charged NV center....

Figure 4.12 (a) Schematic of intersected nanocircuits with NV center in nano...

Figure 4.13 (a) Schematic of NV center in nanodiamond coupling to the gap su...

Figure 4.14 (a) False‐color SEM image of the intersected waveguide containin...

Figure 4.15 (a) Schematic of entangled states on a single photon between SAM...

Figure 4.16 (a) Schematic of arrays of entangled photon pairs excited by met...

Chapter 5

Figure 5.1 Schematic illustration of crystalline and electronic band structu...

Figure 5.2 Probability distributions of photon numbers for different light s...

Figure 5.3 Schematic diagram of a Hanbury Brown and Twiss (HBT) experiment s...

Figure 5.4 Schematic illustrations of Hong–Ou–Mandel interference for fully ...

Figure 5.5 The honeycomb lattice structure (Left), the first Brillouin zone ...

Figure 5.6 Calculated band structures of (from Left to Right) bulk MoS

2

, qua...

Figure 5.7 Illustration of excitonic transition: the solid green line exempl...

Figure 5.8 Electronic bands of TMDCs with W compounds at the K and K′ valley...

Figure 5.9 Low‐temperature PL intensity map of WSe

2

crystal (Left) and the b...

Figure 5.10 PL spectra (Left) and the second‐order time correlation curve (R...

Figure 5.11 The AA′ stacking (Left) and honeycomb lattice (Right) of h‐BN.

Figure 5.12 Schematic illustration of crystalline structures and possible de...

Figure 5.13 Room‐temperature PL spectra (Left) and the second‐order time cor...

Figure 5.14 Room‐temperature PL spectra of different defect‐related emitters...

Figure 5.15 Schematic drawings of graphene cells in real space (Left) and re...

Figure 5.16 Calculated electron dispersion in the honeycomb lattice of graph...

Figure 5.17 Schematic representation of quantum dot and exciton (Left) and t...

Figure 5.18 Schematic chemical structure of the graphene QDs with alkyl chai...

Figure 5.19 Cross‐section illustration and optical microscope image of WSe

2

‐...

Figure 5.20 Cross‐section device illustration of multilayer h‐BN sandwiched ...

Figure 5.21 Conceptual illustration of an integrated quantum photonic circui...

Figure 5.22 Simulated electric field distribution of the rib waveguide with ...

Figure 5.23 Schematic illustration of the h‐BN/SiN hybrid system (Top Left)....

Figure 5.24 Schematic illustration of generating localized exciton states in...

Figure 5.25 Schematic of the fabrication process for the SiO

2

/h‐BN/SiO

2

/SiN ...

Figure 5.26 Gallery of h‐BN photonic structures. 2D photonic crystal lattice...

Figure 5.27 Scanning electron microscopic images and simulated electric fiel...

Figure 5.28 Gallery of 2D SPE‐plasmonic cavity hybrid systems. WSe

2

monolaye...

Figure 5.29 Schematic illustration of an h‐BN flake coupled to a gold wavegu...

Figure 5.30 Schematic illustration of the h‐BN embedded microcavity (Top Lef...

Figure 5.31 Schematic of monolayer WSe

2

coupled to plasmonic gap modes (Top ...

Figure 5.32 Schematic illustration of the SPE–fiber coupled system excited t...

Figure 5.33 Schematic of the fiber‐based Fabry–Pérot cavities embedded with ...

Chapter 6

Figure 6.1 Three distinct categories of network models: (a) forward modeling...

Figure 6.2 Schematic of the SOI‐based power splitter. (a) Top view, where ...

Figure 6.3 Metric as a function of the number of 3D FDTD runs, for the conve...

Figure 6.4 A three‐missing‐air‐holes (L3) cavity is used as the base structu...

Figure 6.5 Configuration of the neural network prepared to learn the relatio...

Figure 6.6 Forward DNN architecture for predicting the meta‐surface optical ...

Figure 6.7 U‐Net for the example of the silicon nanostructure model. The vol...

Figure 6.8 Demonstration of inverse design for a power splitter to fill gap ...

Figure 6.9 Architecture of the meta‐filter design network and design example...

Figure 6.10 Schematic illustration of the silicon nanostructure and the gene...

Figure 6.11 Tandem DNNs architecture with an input layer of color values ,...

Figure 6.12 Several representative unit cells and the Brillouine grid‐sampli...

Figure 6.13 Predictive network architecture showing the convolutional encode...

Figure 6.14 GAN consists of a generative (G) and a discriminative (D) networ...

Figure 6.15 CVAE model for inverse design of meta‐materials. Three submodels...

Figure 6.16 Architecture of the proposed GAN. Three networks, the generator ...

Figure 6.17 Basic architecture of a VAE implemented in the framework. (a) Th...

Figure 6.18 Flowchart of the VAE‐ES framework. The generator (G) is utilized...

Figure 6.19 Overview of progressively growing GAN (PGGAN) network architectu...

Figure 6.20 (a) Schematic of a PINN for solving inverse problem in photonics...

Figure 6.21 Panel (a) shows the schematic for nanocylinder with constant per...

Figure 6.22 Schematic of the SOI‐based nanophotonic power splitter. The rect...

Figure 6.23 The Adversarial CVAE network with cycle consistency. The network...

Figure 6.24 Training trajectory across epoch. At each epoch, generated dev...

Figure 6.25 Mean and over the range of and nm of the devices used fo...

Figure 6.26 Device topologies of (a) training data for , (b) training data ...

Figure 6.27 Mean and over the wavelength range of and nm of the devi...

Figure 6.28 Convolutional neural network (CNN) architecture.

Figure 6.29 (a) Target and predicted total transmittance of CNN and FCDNN, a...

Chapter 7

Figure 7.1 (a) Sketch of an artificial neuron, taking as input a vector of...

Figure 7.2 (a) Sketch of the extinction cross‐section predictor neural netwo...

Figure 7.3 Comparison of simulations (solid lines) and neural‐network predic...

Figure 7.4 Statistics of the network predictions on 1000 random structures w...

Figure 7.5 Simplified scheme of the generalized nanooptics predictor network...

Figure 7.6 Vanilla CNN vs. U‐Net illustrated by the example of near‐field pr...

Figure 7.7 (a) Scheme of coupling a physics predictor neural network to an e...

Figure 7.8 (a) Illustration of the

one‐to‐many problem

in invers...

Figure 7.9 MMI inverse design via tandem neural network. (a) MMI model wit...

Figure 7.10 Example of initial dataset generation for optimizing coupling to...

Figure 7.11 Effect of iterative training data generation on a MMI inverse ...

Figure 7.12 Example of the effect of perturbation acceptance threshold on th...

Figure 7.13 By structuring diffraction‐limit sized silicon nanostructures in...

Figure 7.14 (a) Scheme of the experimental setup for speckle‐based hyperspec...

Chapter 8

Figure 8.1 PL spectra of LiNbO

3

in different molarity concentrations (a) 1 m...

Figure 8.2 LiNbO

3

of different molarity concentration (a) Transmission spect...

Figure 8.3 (a) Dielectric constant (real) vs. photon energy (

hv

), (b) Dielec...

Figure 8.4 Plot of optical conductivity (

σ

) vs. photon energy (

hv

) of L...

Figure 8.5 Plot of ln (

α

) vs. photon energy (

hv

) of LiNbO

3

nanostructur...

Figure 8.6 XRD patterns of LiNbO

3

nanophotonics with different molarity conc...

Figure 8.7 Surface morphology of LiNbO

3

nanophotonics at different molarity ...

Figure 8.8 AFM images of LiNbO

3

nanophotonics at different molarity concentr...

Figure 8.9 Thickness of LiNbO

3

nanophotonics at room temperature.

Figure 8.10 LiNbO

3

nanophotonics in different molar concentrations (a) Trans...

Figure 8.11 XRD patterns of LiNbO

3

nanostructures at different stirrer times...

Figure 8.12 SEM images of LiNbO

3

nanostructures at different stirrer times (...

Figure 8.13 AFM images of LiNbO

3

nanostructures at different stirrer times (...

Figure 8.14 (a) Reflection spectra, (b) Energy bandgap and (c) Refractive in...

Figure 8.15 PL spectra of LiNbO

3

at different stirrer times (a) 8 hours, (b)...

Chapter 9

Figure 9.1 Polarization‐modulating metasurfaces integrated with LC. (a) SRR ...

Figure 9.2 Refractive‐index‐controlling metasurfaces integrated with LC. (a)...

Figure 9.3 (Viewing angle)‐dependent and wavelength‐dependent nanophotonic d...

Figure 9.4 Spin and OAM‐dependent nanophotonic devices. (a) Polarization‐sen...

Figure 9.5 (a) Realization of switchable color by integration of VO

2

with pl...

Figure 9.6 (a) By doping VO

2

with W and Sr, 100 nm‐thick films were deposite...

Figure 9.7 MEMS‐based mechanically tunable nanophotonic devices with various...

Figure 9.8 Mechanically tunable nanophotonic devices with various materials ...

Figure 9.9 Mechanically tunable nanophotonic devices. (a) Multi‐imaging devi...

Figure 9.10 Bandgap engineering of TiO

2

using hydrogen dopant. (a) Schematic...

Figure 9.11 Refractive index modulation of TiO

2

with thermo‐optic effect. (a...

Figure 9.12 Tunability of silicon optical indices with thermo‐optic effect. ...

Figure 9.13 (a) Refractive index and extinction coefficient of IGZO. (b) (up...

Figure 9.14 (a) Schematic of metal‐chitosan‐metal F–P resonator. (b) Calcula...

Figure 9.15 (a) The illustration of the metal–oxide–ITO layer. (b) When posi...

Figure 9.16 (a) the comparison of the carrier density where the gate voltage...

Figure 9.17 Applications of ITO with phase modulations. (a) Top: schematic o...

Guide

Cover

Table of Contents

Title Page

Copyright

Preface

Begin Reading

Index

End User License Agreement

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Integrated Nanophotonics

Platforms, Devices, and Applications

Edited by Peng Yu, Hongxing Xu, and Zhiming Wang

Editors

Dr. Peng YuUniversity of Electronic Science and TechnologyInstitute of Fundamental and Frontier ScienceNo.4, Section 2, North Jianshe RoadChenghua District610054 ChengduChina

Prof. Hongxing XuWuhan UniversitySchool of Physics and Technology299 Bayi RoadWuchang District430072 WuhanChina

Prof. Zhiming WangUniversity of Electronic Science and TechnologyInstitute of Fundamental and Frontier ScienceNo.4, Section 2, North Jianshe RoadChenghua District610054 ChengduChina

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Preface

Moore's law predicts that the size of chip components will reach the limit of classical physics while global information technology shows explosive growth. Therefore, this demand poses challenges to the interconnect systems and devices regarding bandwidth, capacity, cost, and power consumption. Compared with the traditional discrete optical–electrical–optical processing method, integrated nanophotonics reduces complexity and improves the reliability of the systems. The attempt to connect integrated photonic devices with IC is becoming a major scientific and industrial trend due to our eagerness to meet the energy consumption and speed requirements for information processing in new applications, such as artificial intelligence and big data [1, 2]. Also, integrated nanophotonics can address several bottlenecks generated in IC, especially when going to high operating frequencies [3]. Therefore, integrated nanophotonics will be the mainstream technology for next‐generation information devices. Consequently, it is necessary and urgent to publish a book introducing the recent progress of integrated nanophotonics. This book is systematically presented to provide an overall understanding and insight into the integrated nanophotonics field by discussing the latest development in designs, applications, and materials for integrated nanophotonics. We hope the chapters of this book contribute to the academic exchanges in integrated nanophotonics, promote this emerging field to a broader range of readers, and promote the application of some integrated nanophotonics‐related technologies.

The book's main body comprises nine chapters that focus on integrated nanophotonics. The included chapters do not cover the entire breadth of the field of integrated nanophotonics, but we hope they will give the reader an interesting summary of this exciting field. The nine chapters provide a comprehensive perspective on packaging and testing of photonic integrated circuits, silicon photonics, integrated nonlinear photonics, integratable quantum light sources, deep‐learning design for integrated nanophotonics, waveguiding, and reconfigurable nanophotonics.

The editors thank all the contributors to this book for their remarkable chapters. We owe special thanks to Dr. Shaoyu Qian and Ms. Katherine Wong at Wiley for supporting this book. Last but not least, we would like to thank Mr. Haoyun Niu, who provided indispensable editorial assistance and support. Peng Yu is funded by the National Natural Science Foundation of China (No. 62005037). The editors acknowledge the support from the National Key Research and Development Program (No. 2019YFB2203400).

Chengdu, People's Republic of China

Wuhan, People's Republic of China

Peng Yu

4 January 2023

Hongxing Xu, Zhiming Wang

References

1

Soref, R. (2010). Mid‐infrared photonics in silicon and germanium.

Nature Photonics

4: 495–497.

2

Benson, O. (2011). Assembly of hybrid photonic architectures from nanophotonic constituents.

Nature

480: 193–199.

3

Dong, M., Clark, G., Leenheer, A.J. et al. (2022). High‐speed programmable photonic circuits in a cryogenically compatible, visible–near‐infrared 200 mm CMOS architecture.

Nature Photonics

16: 59–65.

1Packaging and Test of Photonic Integrated Circuits (PICs)

Stéphane Bernabé1, Tolga Tekin2, Bogdan Sirbu2, Jean Charbonnier4, Philippe Grosse1, and Moritz Seyfried3

1Université Grenoble Alpes, Photonics Division, CEA LETI, Minatec Campus, 17, rue des martyrs, F38054 Grenoble, France

2Fraunhofer IZM, Photonic and Plasmonic Systems, Gustav‐Meyer‐Allee 25, 13355 Berlin, Germany

3ficonTEC Service GmbH, Research and Development, Rehland 8, 28832 Achim, Germany

4Université Grenoble Alpes, Silicon Devices Division, CEA LETI, Minatec Campus, 17, rue des martyrs, F38054 Grenoble, France

The chief commercial advantage of the PIC is in its reduction in the number of component coupling and packaging steps. The result is greater reliability, lower cost and power, and smaller size.

Ivan P. Kaminow (2008)

1.1 Introduction

Compared to semiconductor electronic integrated circuits (EIC), packaging and testing of photonic integrated circuits (PIC) require specific methods and processes. It is due to the particularity of their optical I/Os and in some cases the thermal sensitivity of integrated photonic functions. These constraints prevented industrial processes to reach the same cost breakdown as electronic ICs: today, the major part (up to 80%) of a photonic module cost still lies in packaging and test operations, not in the circuit itself. As explained previously in this book, various technologies exist to fabricate PICs, using various types of materials and structures, with few standards or roadmap relating to packaging and testing.

PIC integration into a module follows an assembly sequence which includes wafer‐level test, chip dicing, coupling of optical I/Os to an optical fiber or a laser diode, electrical interconnect to an EIC, and finally the PIC integration into a package or onto a module board. These main steps will be examined in this chapter, reviewing also the main challenges, guidelines, and technologies required by next‐generation photonic modules, such as photonic chiplets or photonic interposers.

1.2 Challenges and Specificities of PIC Packaging and Test

Integration of PICs into a module, embedded in a system (e.g. a switch unit in a 1U blade used in a datacenter rack) requires several specific steps, which will contribute to the final module cost. The final packaged device has to meet the application specifications in terms of operating temperature and environmental standards (e.g. Telcordia GR‐468‐CORE: Generic Requirements for Optoelectronic Devices Used in Telecommunications Equipment). Figure 1.1 shows a typical assembly flow, involving a silicon photonics‐based circuit to achieve a high data rate (e.g. 400 Gbps) datacom transceiver module for intra data center interconnects.

Figure 1.1 Typical assembly flow for the packaging of a silicon photonics PIC into a datacom transceiver module.

This typical assembly flow is shared by most of PIC‐based modules, with slight variations depending on the targeted application and performances. For example, for data rates of 25 Gbps per channel and above, photoreceivers may require high bandwidth transimpedance amplifiers (TIA) add‐ons, flip‐chipped onto Photonic chips [1] using copper pillar interconnects to lower parasitics and shorten wire length. Figure 1.2 shows the motherboard of a previously released 40 Gbps datacom silicon photonics‐based transceiver from Luxtera (10 Gbps per channel).

Figure 1.2 Typical content of a silicon photonics module (with QSFP chassis).

Source: C. Kopp, CEA‐Leti.

As well as for semiconductor devices, PICs packaging and testing are mainly driven by interconnects management. Interconnects achieve the PIC connection to the motherboard, sometimes through an intermediate printed circuit board or package (e.g. BGA laminate, or ceramic package). Quite obviously, by contrast to EICs, two types of PICs interconnects can be distinguished:

Optical interconnects

, allowing the connectivity of the PICs integrated optical waveguides to an external waveguide, for example, an optical fiber, with a maximized transmitted optical power. Optical coupling may be the most discussed obstacle to achieve low‐cost photonics. By contrast to laser diode packaging, optical coupling of PICs generally involves multiple optical channels, leading to the use of fiber ribbons or

multicore fibers

(

MCF

). Fibers are thus mounted into glass V‐groove

fiber arrays

(

FA

) to be handled during test or packaging processes.

Electrical interconnects

, which may be an RF line allowing the proper transmission of a high data rate modulated electrical signal to or from an integrated active photonic device (e.g. phase modulator, photodiode).

1.2.1 Optical Interconnects

From the earliest demonstration of planar waveguide circuits, the challenge of low loss, high yield connection to an optical fiber, or another external waveguide (e.g. a III–V laser) has been identified as a key challenge to allow further adoption of the PIC technology at an industrial level. These challenges are fairly independent on the PIC fabrication technology (lithium niobate oxide, doped glass, silicon photonics, polymer), especially when single‐mode waveguides are considered [2–4]. In this chapter, we will focus on single‐mode waveguides, which can be found in many application fields, especially in the long‐range telecommunications, data center high‐speed interconnects, and may compete with VCSEL links for short reach interconnects such as CPU to memory in the near future.

The main parameter that has to be optimized for efficient optical interface –actually, by targeting the lowest possible value – is the coupling loss (CL). It is related to the linear coupling efficiency η, which is the ratio between the coupled optical power into the external waveguide (P1) and the available optical power at the output of the PIC optical port (P0), by Eq. (1.1)

(1.1)

This CL is a positive value and it is typically wavelength dependent. Some authors use the logarithmic coupling efficiency CE = 10 log(η), which is negative. Additional to the CL, some applications require the amount of reflected power to the input waveguide to be minimized. This results in reducing the corresponding return loss (RL), defined as RL = −10 log(Pr/P0), where Pr denotes the reflected optical power.

Analytical expression of the CL can be obtained by using Kolgelnik's electromagnetic theory of laser beams. In the case of single‐mode waveguides, the coupling efficiency is obtained by calculating the overlap integral between the respective field amplitudes of the fundamental modes E0 and E1 related to the PIC and the external waveguide (secondary waveguide) (Eq. (1.2)), in a reference plane (x, y) orthogonal to the z optical axis

(1.2)

References [5–9] provide expressions of η, in the case the output beam from the PIC can be approximated by a Gaussian beam with a waist denoted ω. This approximation is valid for most of the optical waveguide obtained by microtechnologies fabrication processes.

Several cases can be distinguished here. The simplest coupling scenario that could be considered is butt coupling, with no gap between the two waveguides. In this case, E0 is the amplitude of the field at the output of the PIC, and E1 is the amplitude of the external waveguide's field. Another possible configuration is the case of lens‐assisted coupling: one or several lenses are inserted between the PIC and the external waveguide, allowing beam refocusing of the PIC's beam to the external waveguide input plane. The same Eq. (1.2) should be used, considering E0 as the field obtained by propagating the PIC's output beam through the optical system, overlapping with the external waveguide at the entrance plane of the latter.

In the case of a perfect alignment of the waveguide's axis, Eq. (1.2) can be solved analytically, considering the respective beam's waists radii ω0 and ω1 (Eq. (1.3)), in the axes x and y, respectively.

(1.3)

From this equation, the mode‐matching condition can be determined: the maximum coupling (i.e. minimum CL) is obtained for ω0x = ω1x and ω1y = ω1y. Whether the considered external waveguide is a laser diode, an optical fiber, or another PIC, an optimum packaging or probe test of a given PIC will target a minimum CL by achieving this condition.

In addition, an analytical expression of η can also be obtained in the case of optical axis misalignment (caused by an offset or a tilt): this leads to the knowledge of the alignment tolerances of the system, which is a key parameter to be considered at the packaging or the test level. A convenient way to evaluate alignment tolerance is to calculate the misalignment (tilt or offset) resulting in a 1 dB excess CL (called “1 dB tolerance”). For lateral misalignment of circular beams (perpendicularly to the optical z‐axis) the 1 dB tolerance is given by Eq. (1.4)[10], with waists expressed in micrometers.

(1.4)

Depending on the PIC fabrication technology and the nature of the optical waveguide, it may be not possible to reach the mode‐matching condition. Knowing the waist parameters will however enable to calculate optimum coupling and alignment tolerances by solving the analytical equations or by simulating coupling by using dedicated software (beam propagation modeling or physical optical propagation module from optical design softwares).

1.2.2 Coupling Structures

Coupling structures are PIC features enabling the light extraction/injection from/into the PIC, possibly including some spot size converter (SSC) function to achieve the mode‐matching condition when connection to an optical fiber or another external waveguide is needed. Indeed, in many cases, the used integrated waveguide exhibit mode waists much smaller compared to the waist of the external waveguide due to the use of high index material for the photonic waveguide (e.g. Si or InP) – in the case of silicon photonics, it can be submicrometric. The most critical configuration is for pigtailing (coupling to a single‐mode optical fiber) as the fiber's waist (aka mode field radius or MFR) of a standard single‐mode fiber (SMF) is typically about 5 μm in the telecommunication wavelength range.

One can distinguish between three types of coupling structures [11–13]. Depending on the used configuration, mode‐matching condition (and thus minimum CL), operating wavelength range, polarization‐dependent loss (PDL), misalignment tolerance, and manufacturing scalability may be different.

1.2.2.1 Edge Coupler

This kind of structure enables lateral (in plane) direct coupling to an optical fiber or a laser diode by locally modifying the beam waist of the guided mode at the proximity of the PIC facet, if required. It is a broad wavelength solution, with low PDL (<1 dB). Several edge couplers are reported in literature, depending on the waveguide technology. Waveguides with large cross sections (approx. 10 × 10 μm) exhibit large waists and can be directly coupled to a SMF by dicing and polishing the chip facet. For SiN, InP, or thick SOI waveguides, simple edge coupling without any spot size conversion leads to the use of lensed fiber to achieve the mode‐matching condition (waists are typically in the 1–3 μm range). For silicon photonics relying on thin SOI (typically 220 nm thick), SSC is required to achieve waists compatible with commercialy available lensed or flat cleaved fibers.

Spot size conversion is obtained by:

gradually increasing the physical size of the waveguide (

3D adiabatic taper

) along light propagation axis (

z

‐axis).

using

inverted tapers

, gradually reducing the lateral waveguide size in the

z

‐axis, down to the minimum possible size at the tip (defined by the used lithographic node), resulting in a decrease of the effective index and thus a less confined mode.

use of

metamaterial structures

exhibiting low effective index.

adiabatically transferring of the optical power to a

super waveguide

made of another material of lower index (e.g. silicon nitride on the top of a tapered silicon waveguide).

All these different structures (Figure 1.3) provide beam enlargement, with alignment tolerances directly related to the beam size; however, a suitable surface quality of the facet requires polishing at the die level (after dicing or cleaving) or a final etching process step performed at the wafer level. In any case, wafer‐level test remains challenging.

Figure 1.3 Edge coupling structure obtained by inverted taper design.

Source : S. Bernabé, CEA‐Leti.

1.2.2.2 Vertical Grating Coupler (VGC)

Vertical grating coupler (VGC) relies on diffractive elements integrated at the end of a PIC waveguide (Figure 1.4), deflecting the propagating beam out of plane, at nearly 90° (current designs target 82°), while intrinsically converting the beam size. This feature is very popular in silicon photonics‐based circuits, as the high index contrast of silicon waveguide core to silica cladding allows high diffraction efficiency of periodical or quasi‐periodical gratings. VGC enables mode matching with SMF, making wafer‐level test and multifiber packaging much more convenient compared to edge couplers. Additionally, VGCs can be placed at any location on the PIC surface, and do not require any post‐process such as polishing or cleaving. VGC exhibits limited bandwidth (<30 nm) and polarization dependency which can be improved to <0.5 dB by designing two‐dimensional structures, sometimes referred to as 2D‐VGC. These structures, close to photonic crystals arrays, act as polarization splitters/combiners, with typical CL of 3.5 dB [12].

Figure 1.4 Scheme and SEM view of a single polarization grating coupler (SPGC).

Source: S. Bernabé, CEA‐Leti.

Arrays of VGC can also be used to enable coupling to a multi core fiber (MCF).

1.2.2.3 Evanescent Coupling

This approach, which allows efficient wavelength‐dependent coupling between two adiabatically tapered waveguides (Figure 1.5), has been basically used to perform rough testing of earlier generations of waveguide. It relies on the evanescent coupling in a region where the two deconfined modes overlap.

Figure 1.5 Evanescent coupling between two PICs with adiabatic couplers.

Source: S. Bernabé, CEA‐Leti.

Through optimization of tapered designs, it is now possible to use it to achieve efficient coupling from a buried waveguide in the PIC to an external waveguide positioned above it, at an optimum distance. This external waveguide can be embedded in a flex substrate, or be a polished or tapered fiber. This configuration typically exhibits large (>50 nm) 1 dB tolerance along the waveguide optical axis (z‐axis), and is intrinsically broadband in terms of spectral bandwidth [11].

1.2.3 Wafer‐level Test

In the past years, wafer‐level test strategies have been developed to test PICs with similar processes as for semiconductor chips. Particularly, wafer‐level test aims at enabling a deep range of measurements and tests at the end of the chip fabrication process, allowing a screening of the fabricated chips and identification of known good dies (KGD) before the packaging steps. Here also, the specificity of PICs in terms of optical I/Os prevents from directly applying test techniques developed for microelectronics circuits – i.e. probe tester‐based wafer‐level test. These well‐known test methods need to be slightly adapted, depending on the type of used coupling structures and the complexity of electro‐optical (E/O) tests to be performed.

Using VGC as coupling structure is the most common case for silicon photonics PICs. In this configuration, it is possible to adapt standard electrical probe testers by adding optical probes, i.e. bare optical fiber or FA (fiber array) to launch or collect the light to or from the PIC (Figure 1.6). This allows the test of existing test structures embedded in the PIC, or to directly test some functionalities of the circuit itself, at the wafer level, before dicing.

Figure 1.6 Optical on‐wafer test of silicon photonics PICs using a V‐groove fiber array. The wafer is hold on the prober chuck using vaccum.

Source: P. Jayet, CEA‐Leti.

The accuracy of the positioning system needs to be higher than that for a pure electronic test station. 1 μm accuracy over a 300 mm wafer instead of 5 μm is needed to guarantee the accurate positioning of a standard SMF on the top of a grating coupler. As a result, relying on the movement of the wafer vs. chuck only is not sufficient, and the optical probe has to be moved accurately too, by attaching it to a high‐resolution (10 nm) multi‐axis micro positioning system, e.g. a piezoelectric actuator. Practically, the test sequence will use both the displacement of the chuck to switch from a PIC to the following; however, for each PIC, a realignment of the fiber probe to the optical port is needed, through the additional micro‐positioning system. The alignment sequence typically starts with the 2D scan of the beam profile out of the PIC, followed by a Gaussian fit, which allows to determine the position for optimum coupling efficiency. Piezoelectric microactuators may be controlled by a driver which is able to simultaneously control the moves and acquire synchronously an electrical signal proportional to the coupled power. This signal can also be used to maintain the coupling in real time, thanks to an additional digital signal processor (DSP) unit using dedicated algorithm [14, 15].

Using FAs exhibits several advantages: scalability (simultaneous handle and test using typically 8 fibers, potentially up to 128), robustness, lower sensitivity to vibrations, and possibility an efficient use of polarization‐maintaining fibers. However, an additional degree of freedom in rotation is needed. In this case, two fibers have to be aligned on two optical ports, requiring a rotation adjustment. In addition, an accurate control of the parallelism of the fiber array toward the PIC surface may require one or two additional rotation degrees of freedom, making six axis positioning system (e.g. hexapod) the best solution for such configurations.

Until recently, applying the above approach to edge coupling structures was a challenge, as the edge emission requires the PIC to be diced first before any optical test, forbidding wafer‐level test. Solutions have been developed to enable the use of wafer probe testers relying on optical probes embedding reflectors [16]. This requires front‐side cavities to be processed during the PIC fabrication process, at the tip of the fiber coupler structure. This cavity has to be large enough to allow the insertion of a beveled probe to be inserted (Figure 1.7), typically 200 μm wide and 150 μm deep. This probe can be a glass waveguide array with a 45° reflector at the end, for example, a waveguide array to fiber transposer (WAFT) interface from Teem Photonics. This transposer array acts simultaneously as a reflector, a spot size convertor, and a pitch convertor to test dense waveguide arrays and connect them to standard 250 μm pitch fiber ribbons. Using this technique, measurement range >60 dB has been demonstrated.

Figure 1.7 Wafer‐level test of PICs with edge couplers using reflective glass probes.

Source : S. Bernabé, CEA‐Leti.

Additional to the mechanical challenges described in this section, efficient electro‐optic measurements also require some modification of standard test and measurement systems. Indeed, in addition to electrical measurement devices, optical measurements have to be performed, particularly spectrum acquisition. This is achieved by using a tunable laser source at the input of the device under test (DUT) and a wideband photodetector at the output. The overall characterization time of a typical step‐by‐step measurement can be reduced by the use of a triggered sweeped approach, which can drastically reduce the acquisition time. In this configuration, a tunable laser source sweeps freely in a determined wavelength range. A wavelength meter (usually a fiber interferometer) delivers a signal used to trigger an optical meter acquisition and record data in a buffer. The data are recovered only at the end of the laser sweep. Using this setup, it is possible to obtain spectra with a 1 p.m. resolution and 100 nm bandwidth within 10 seconds. Optical measurement can be combined to any electrical test to perform E/O measurement, e.g. response of a photodiode vs. input wavelength, DC phase shifter transmission, or even RF characteristics of an electro‐optic modulator by applying RF signals employing RF probes connected to a vector network analyzer (VNA), simultaneously measuring the modulated optical signal (Figure 1.8).

Figure 1.8 Automated probe tester with dedicated test and measurement instrument for electro‐optical test (a) and close view of a PIC under simultaneous RF + optical test (b).

Source: P. Grosse, CEA‐Leti.

1.2.4 Module Packaging

Wafer‐level test, described in the previous section, enables a KGD approach, by picking the chips meeting the targeted specifications for further module integration. The next assembly step generally consists in dicing then die attach and electrical interconnect to a board. The related challenges of electrical‐optical integration, thermal management, and mechanical stability of the package, when so many different materials are involved, are also significant design considerations [17].

The design of an integrated photonics package is an iterative process. The typical design steps after the PIC is already designed are the following: first of all the material to work with should be selected, then the thermomechanical aspects should be taken into consideration, and lastly, the RF behavior of the package should be optimized. Depending on the target application using the PIC, some packages might require to comply with a certain standardization form factor, it might need to be hermetical or it might be used for high‐power applications, requiring a certain mechanism to dissipate the heat form the package. Therefore, material selection is crucial in the package design and is fully linked to the application. To ensure the reliability of the packages, the thermomechanical design is fundamental. Figure 1.9 shows an example of such thermomechanical simulation environment, where a high‐speed PIC package has been modeled employing a commercially available software.

Figure 1.9 FEM thermomechanical simulation model of a wire‐bond‐based PIC package module with the typical material deformation maps due to mechanical stress and/or heat within the package.

Source: B. Sirbu/Fraunhofer IZM.

The typical aspects to be considered for the mechanical design step are among others the characteristics of the components, which kind of assembly process and which materials are going to be used during the assembly process, and of course the thermal constraints of the package. The thermal aspect is particularly important when it comes to the PIC packaging as many of the employed building blocks on the PICs such as lasers and ring resonators are extremely sensitive to any kind of thermal cross talks resulting in an unwanted functionality of the designed PIC. Moreover, thermal instabilities can turn into mechanical stresses due to the coefficient of thermal expansion (CTE) differences of the materials that eventually can affect the functionality and integrity of the package. Therefore this aspect cannot be neglected during the package design. Thermal stability of the PIC packages is typically done employing thermoelectric coolers (TEC) and thermistors.

The final aspect which should be taken into consideration in the successive package design iterations is the RF behavior. Figure 1.10 shows an example of a simulation model used to optimize the RF characteristics of a PIC package involving several parts which have to work together such as the PCB design, Si/Glass interposer where the PIC is assembled and the wire‐bonds or bumps interconnecting the interposer to the PCB.

Figure 1.10 HF simulation model of a PIC package with the typical S‐parameter curves of the HF traces on the package (involving transmission lines on PCB, Si Interposer, and wire‐bonds).

Source: B. Sirbu/Fraunhofer IZM.

Packaging design rules (PDR) are extremely important in this case, since they are dictating the package specifications with eventual channel limitations, pitch between the electrical lines, maximum I/O counts, or the impedance of the connectors on the package. Electrical interfaces are necessary for optoelectronic components, for power distribution, and data signal transmission. For HF applications, the electrical interfaces have to comply with some dynamic characteristics such as propagation delay, attenuation, noise, crosstalk, and the rise and fall times to ensure the signal integrity requirements of the package. For this purpose, the impedance‐matched transmission lines are crucial to minimize reflections and propagation losses. Additionally, the power integrity aspects for the supporting ASICs shall be considered with respect to co‐packaging.

As it can be seen, satisfying all the electrical, optical, and thermomechanical design considerations of integrated photonic devices requires a holistic approach to photonic packaging. The expected performances of the designed modules will have to be confirmed through testing: first, the separate modules are normally individually characterized to confirm their expected behavior, and finally, the entire package is characterized once all assembly steps are finalized.

1.2.5 Fiber Optic Assembly (Pigtailing)

Fiber optic assembly, commonly known as pigtailing, is generally relying on an active alignment of the external waveguide to the PIC, using an accurate six‐axis positioning system, and by monitoring the coupled power – just as during the wafer‐level test step. However, once the maximum optical power is reached, the optimum position has to be permanently frozen. This is done either by using UV‐curing adhesives or laser welding. Several categories of optical assemblies have to be distinguished though [18].

1.2.5.1 PIC Alignment to a Lensed Fiber

This method is used in the edge coupling configuration (Figure 1.11), where the PIC I/O characteristic mode size (waist) is not matching a standard SMF MFR, due to limitation of the PIC waveguide fabrication technology (e.g. InP‐based PICs). To ensure mode matching, a high numerical aperture fiber is needed, which can be a lensed fiber. Several technologies can be used to obtain such a fiber: laser machined lensing, chemical etching, fiber tapering using thermal processes, or Gradissimo structure, achieving a focusing lens at the tip of the fiber by splicing a short rod of graded index fiber. Coupling losses (s) around 1 dB with 3 dB spectral bandwidth of several hundreds of nanometers have been reported [19]; however, the value is highly dependent on the mode matching to the lensed fiber.

1.2.5.2 PIC Butt Coupling to a Standard Cleaved Single‐mode Fiber

This method is quite popular when the mode‐matching condition is reached. It is the case by using VGCs at the optical I/O of a silicon photonics PIC, or edge coupler at the optical I/O of PICs made from technologies allowing wide spot sizes (c. 10 μm) at the output (e.g. glass waveguide based circuit, lithium niobate circuit, thick SOI). This method is widely used in commercial products, especially parallel optics modules requiring a fiber ribbon to be assembled in a single step, using a fiber array (Figure 1.12). UV‐curing epoxy is used to fasten the assembly. Using optimized apodized VGC, CL as small as 1 dB has been reported after alignment and fixing, with lateral offset tolerance of +/−2 μm [20].

Figure 1.11 Lensed fiber to silicon photonics chip coupling.

Source: S. Bernabé, CEA‐Leti.

Figure 1.12 Butt coupling assembly of a silicon photonics PIC and a V‐groove fiber array.

Source: O.Castany, CEA‐Leti.

Efficient (<1.5 dB CL, PDL < 0.5 dB) coupling between thin SOI silicon photonics circuits and standard cleaved fiber have been demonstrated too [21] by using optimized spot size converting edge couplers, leading to potential multifiber alignment of fibers using this configuration.

1.2.5.3 Lens Coupling Scheme

This approach (Figure 1.13), widely used for the packaging of single chip laser diodes for optical fiber networks, achieves the mode‐matching condition to a SMF by inserting an optical system of magnification M = ω1/ω0. It can be made of a single focusing lens or a dual‐lens optical train. This second option is a good approach when an optical isolator has to be put in the optical beam to limit any optical feedback to the PIC. The first lens is used to collimate the beam, allowing the isolator to be put in the collimated beam, and the second lens is acting as a focusing lens to form the image of the PIC optical port at the input of the fiber. In reference [22], microlenses are used on both a VGC array and a FA array, fiber‐to‐PIC grating‐coupling has been achieved with a CL of 1.7 dB (i.e. a coupling efficiency of 68%) at 1300 nm, and a 1 dB alignment tolerance of ±30 μm).

Figure 1.13 Microlens array assembled on the top a silicon photonics PIC to perform beam collimation.

Source: O. Castany, CEA‐Leti.

1.2.5.4 Optical Waveguide Interposer Coupling

An intermediate integrated waveguide can also be inserted between the PIC and the optical fiber, potentially acting as a SSC (e.g. glass waveguide obtained by ion‐exchange process). In this case, active alignment using UV‐curing adhesive remains the main option for assembly. An external waveguide, for example, a polymer waveguide on a flexible substrate can also be used to perform evanescent coupling between a PIC and an external fiber ribbon (Figure 1.14).

Figure 1.14 Glass interposer connected to a PIC, using (a) edge coupling approach (b) evanescent coupling.

Source: A. Billat/Teem Photonics.

Using a three‐stage coupler made of a Si–SiN–glass stack, <1.9 dB CLs have been demonstrated [23] at the SiN–glass transition, with low PDL (<0.4 dB) over a wide spectral range (>100 nm). Assembly has been performed using a flip‐chip precision bonder from SET.

1.2.6 Emerging Trends for Module Mass Manufacturing

Driven by silicon photonics technology, PIC‐based modules are now able to address applications requiring volume manufacturing (e.g. data centers, LIDARs) and in a second step dense integration of complementary metal‐oxide‐semiconductor (CMOS) and photonic circuitry for next‐generation computing (e.g. manycore architectures using an internal optical bus). Indeed, silicon photonics comes with the promise of integrating CMOS electronics and photonics by using either monolithic integration or hybrid approaches, changing the paradigm of PICs by leveraging the semiconductor ecosystem in terms of design tools (electronic design automation – EDA) and foundries, with the related scalability in terms of circuit complexity and mass manufacturing capability. Even though legacy packages, inherited from telecommunication single laser diode package, are still used for small layout and prototyping (“Gold Box” approach) [24], they are making way to cheaper approach such as PIC‐on‐board approach, where the PIC is typically glued and wire‐bonded to a PCB for the DC/HF connectivity [25]. Figures 1.15 and 1.16 show an example of both approaches.

Figure 1.15 Gold box package developed within the EU‐founded iPhos project.

Source: B. Sirbu/Fraunhofer IZM.

Figure 1.16 PIC‐on‐board package developed within the EU‐founded 5G‐PHOS project.

Source: B. Sirbu/Fraunhofer IZM.

The expected next milestones of this evolution have been described in more detail in [13]:

Improved manufacturing flow for front panel modules (datacom) and emerging high‐volume markets (e.g. LiDARs, …).

The integration of PICs in modules currently relies on legacy technologies, with inherent limitations in terms of throughput and thus cost. To address this, an adoption and optimization of all existing assembly and test technologies are required for the mass fabrication of modules, despite their high level of integration and complexity. The existing building blocks are leveraging new packaging approaches for the simplification of the assembly while rendering it simultaneously more robust. Obviously, the reduction of fabrication cost can be reached by pushing the boundaries of optoelectronic packaging automation from stand‐alone assembly machines to integrated assembly lines, considering a new assembly flow. This is obtained by leveraging vision‐assisted alignment at every step of the assembly process to drastically reduce assembly time for any assembly step which do not deserve accurate submicrometric alignment. For example, in the European Project MASSTART, a silicon photonics‐based transceiver (400 Gbps) has been developed, intended to be packaged in a standard QSFP‐DD chassis (Figure 1.17).

The optical engine, which is the basis of the module, is made of seven optical components (1 laser array, two lens arrays, one isolator, one prism, the PIC, and one fiber array). These various components are assembled on a silicon optical bench (SiOB) using mostly vision‐assisted techniques (“passive steps”), active alignment steps are used for the laser lens array and fiber array only.

Development and adoption of next‐generation small footprint modules, i.e. Optical Engines and Co‐package modules (CPO).

In a next step, the emerging applications such as high‐speed optical networks, high‐performance computing, and storage applications benefit from packaging of photonics devices and electronic chips (e.g. ethernet switches, CPU, FPGA) together in a single package. This approach is known as co‐package optics (CPO) [26, 27]. This rapidly growing technology is leading to the reduction of power consumption, thermal effects, and the required footprints. An area of considerable potential for CPO is in the high‐speed industrial interconnect sector, where classical SerDes approaches may run out of steam over the coming decade. As high‐speed interconnects become ubiquitous – in aerospace, video, and military applications – the market for CPO‐based interconnects will increase.

Especially, in the field of data center interconnects, the data rate of network switches and transceivers is doubling every 18 months [13]