Microwave Amplifier and Active Circuit Design Using the Real Frequency Technique E-Book

Pierre Jarry

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: Wiley - IEEE
• Sprache: Englisch

Seitenzahl: 283

Veröffentlichungsjahr: 2016

Beschreibung

Describes the use of the Real Frequency Technique for designing and realizing RF/microwave amplifiers and circuits This book focuses on the authors' Real Frequency Technique (RFT) and its application to a wide variety of multi-stage microwave amplifiers and active filters, and passive equalizers for radar pulse shaping and antenna return loss applications. The first two chapters review the fundamentals of microwave amplifier design and provide a description of the RFT. Each subsequent chapter introduces a new type of amplifier or circuit design, reviews its design problems, and explains how the RFT can be adapted to solve these problems. The authors take a practical approach by summarizing the design steps and giving numerous examples of amplifier realizations and measured responses. * Provides a complete description of the RFT as it is first used to design multistage lumped amplifiers using a progressive optimization of the equalizers, leading to a small number of parameters to optimize simultaneously * Presents modifications to the RFT to design trans-impedance microwave amplifiers that are used for photodiodes acting as high impedance current sources * Discusses the methods using the RFT to optimize equalizers made of lossy distributed networks * Covers methods and examples for designing standard linear multi-stage power amplifiers and those using arborescent structures * Describes how to use the RFT to design multi ]stage active filters * Shows the flexibility of the RFT to solve a variety of microwave circuit design problems like the problem of passive equalizer design for Radar receivers * Examines a possible method for the synthesis of microwave antennas using the RFT Microwave Amplifier and Active Circuit Design Using the Real Frequency Technique is intended for researchers and RF and microwave engineers but is also suitable for advanced graduate students in circuit design. Dr. Beneat and Dr. Jarry are members of the editorial board of Wiley's International Journal of RF and Microwave Computer Aided Engineering. They have published seven books together, including Advanced Design Techniques and Realizations of Microwave and RF Filters (Wiley-IEEE 2008), Design and Realizations of Miniaturized Fractals RF and Microwave Filters (Wiley 2009), Miniaturized Microwave Fractal Filters--M2F2 (Wiley 2012), and RF and Microwave Electromagnetism (Wiley-ISTE 2014).

Leseprobe

Table of Contents

Cover

Title Page

Foreword

Preface

Acknowledgments

1 Microwave Amplifier Fundamentals

1.1 Introduction

1.2 Scattering Parameters and Signal Flow Graphs

1.3 Reflection Coefficients

1.4 Gain Expressions

1.5 Stability

1.6 Noise

1.7

ABCD

Matrix

1.8 Distributed Network Elements

References

2 Introduction to the Real Frequency Technique

2.1 Introduction

2.2 Multistage Lumped Amplifier Representation

2.3 Overview of the RFT

2.4 Multistage Transducer Gain

2.5 Multistage VSWR

2.6 Optimization Process

2.7 Design Procedures

2.8 Four-Stage Amplifier Design Example

2.9 Transistor Feedback Block for Broadband Amplifiers

2.10 Realizations

References

3 Multistage Distributed Amplifier Design

3.1 Introduction

3.2 Multistage Distributed Amplifier Representation

3.3 Multistage Transducer Gain

3.4 Multistage VSWR

3.5 Multistage Noise Figure

3.6 Optimization Process

3.7 Transistor Bias Circuit Considerations

3.8 Distributed Equalizer Synthesis

3.9 Design Procedures

3.10 Simulations and Realizations

References

4 Multistage Transimpedance Amplifiers

4.1 Introduction

4.2 Multistage Transimpedance Amplifier Representation

4.3 Extension to Distributed Equalizers

4.4 Multistage Transimpedance Gain

4.5 Multistage VSWR

4.6 Optimization Process

4.7 Design Procedures

4.8 Noise Model of the Receiver Front End

4.9 Two-Stage Transimpedance Amplifier Example

References

5 Multistage Lossy Distributed Amplifiers

5.1 Introduction

5.2 Lossy Distributed Network

5.3 Multistage Lossy Distributed Amplifier Representation

5.4 Multistage Transducer Gain

5.5 Multistage VSWR

5.6 Optimization Process

5.7 Synthesis of the Lossy Distributed Network

5.8 Design Procedures

5.9 Realizations

References

6 Multistage Power Amplifiers

6.1 Introduction

6.2 Multistage Power Amplifier Representation

6.3 Added Power Optimization

6.4 Multistage Transducer Gain

6.5 Multistage VSWR

6.6 Optimization Process

6.7 Design Procedures

6.8 Realizations

6.9 Linear Power Amplifiers

References

7 Multistage Active Microwave Filters

7.1 Introduction

7.2 Multistage Active Filter Representation

7.3 Multistage Transducer Gain

7.4 Multistage VSWR

7.5 Multistage Phase and Group Delay

7.6 Optimization Process

7.7 Synthesis Procedures

7.8 Design Procedures

7.9 Simulations and Realizations

References

8 Passive Microwave Equalizers for Radar Receiver Design

8.1 Introduction

8.2 Equalizer Needs for Radar Application

8.3 Passive Equalizer Representation

8.4 Optimization Process

8.5 Examples of Microwave Equalizers for Radar Receivers

References

9 Synthesis of Microwave Antennas

9.1 Introduction

9.2 Antenna Needs

9.3 Antenna Equalizer Representation

9.4 Optimization Process

9.5 Examples of Antenna-Matching Network Designs

References

Appendix A: Multistage Transducer Gain

A.1 Multistage Transducer Gain Demonstration

A.2 Target Multistage Transducer Gain

Appendix B: Levenberg–Marquardt–More Optimization Algorithm

B.1 Levenberg–Marquardt–More Optimization Algorithm

References

Appendix C: Noise Correlation Matrix

C.1 Definition

C.2 Noise Correlation Matrix for Interconnection of Two Two-ports

C.3 Two-port System Made of a Loaded Two-Port Connected in Parallel

C.4 Two-Port System Made of a Loaded Two-port Connected in Series

Appendix D: Network Synthesis Using the Transfer Matrix

D.1 Definitions

D.2 Extracting a Transfer Matrix

D.3 Network Synthesis

Index

End User License Agreement

List of Tables

Chapter 02

Table 2.1 Measured scattering parameters of the transistor

Table 2.2 Scattering parameters of the CFX31X GaAs FET

Table 2.3 Scattering parameters of the transistor feedback block

Chapter 03

Table 3.1 Measured

S

parameters of the Fujitsu FHX04X MESFET

Table 3.2 Measured noise parameters of the Fujitsu FHX04X MESFET

Table 3.3 Measured

S

parameters of the Fujitsu FSC-10LG HEMT

Table 3.4 Measured noise parameters of the Fujitsu FSC-10LG HEMT

Table 3.5 Measured

S

parameters of the Fujitsu FSC-10LG HEMT

Table 3.6 Measured noise parameters of the Fujitsu FSC-10LG HEMT

Table 3.7 Measured

S

parameters of the NEC NE24283A HJ FET

Table 3.8 Measured noise parameters of the NEC NE24283A HJ FET

Table 3.9 Measured and simulated characteristics of the three-stage 5.925–6.425 GHz amplifier

Chapter 05

Table 5.1 Scattering parameters for the NEC 72084A GaAs FET transistor

Table 5.2 Scattering parameters for the NEC 71083 GaAs FET transistor

Chapter 06

Table 6.1

S

parameters for the transistors

Table 6.2 Inductor (

nH

) and capacitor ( 

pF

) values for the equalizers

Chapter 07

Table 7.1 Measured

S

parameters of the NEC NE20283A FET transistor

Table 7.2 Measured

S

parameters of the Fujitsu FHX04X MESFET

Chapter 08

Table 8.1 Polynomials coefficients for the sixth order, no transmission zeros equalizer

Table 8.2 Polynomials coefficients for the sixth order, one symmetrical transmission zero equalizer

List of Illustrations

Preface

Figure 0.1 Summary of the organization of the book.

Chapter 01

Figure 1.1 High-speed signals must be amplified in a satellite repeater.

Figure 1.2 A FET modeled as a two-port network.

Figure 1.3 Scattering matrix of a two-port system terminated on characteristic impedance

Z

0

.

Figure 1.4 Signal flow graph representation of a two-port network.

Figure 1.5 Input reflection coefficient and input impedance.

Figure 1.6 Reflection coefficients of a two-port when terminated on arbitrary loads.

Figure 1.7 Gain definitions.

Figure 1.8 Signal flow graph representation for defining the gain.

Figure 1.9 Representation in the case of a unilateral amplifier

.

Figure 1.10 Stability of a two-port.

Figure 1.11 Active device and source and load impedances.

Figure 1.12 Noise figure of the cascade of two active devices.

Figure 1.13 Noise figure of the cascade of three active devices.

Figure 1.14 Noise figure of the cascade of

k

active devices.

Figure 1.15 Notations for defining the

ABCD

matrix of a two-port system.

Figure 1.16 Impedance placed in series.

Figure 1.17 Admittance placed in parallel.

Figure 1.18 Two-port connected to load impedance

Z

L

.

Figure 1.19 Two-port connected to load admittance

Y

L

.

Figure 1.20 Cascade of two systems.

Figure 1.21 Two systems connected in parallel.

Figure 1.22 Two systems connected in series.

Figure 1.23 Two-port system made of admittance loaded two-port connected in parallel.

Figure 1.24 Two-port system made of impedance loaded two-port connected in series.

Figure 1.25 Uniform transmission line.

Figure 1.26 The unit element.

Figure 1.27 Input impedance of a UE loaded on impedance

Z

L

.

Figure 1.28 Input admittance of a UE loaded on impedance

Y

L

.

Figure 1.29 Short-circuited stub placed in series.

Figure 1.30 Short-circuited stub placed in parallel.

Figure 1.31 Open-circuited stub placed in series.

Figure 1.32 Open-circuited stub placed in parallel.

Figure 1.33 First low-pass Kuroda identity.

Figure 1.34 Second low-pass Kuroda identity.

Figure 1.35 First high-pass Kuroda identity.

Figure 1.36 Second high-pass Kuroda identity.

Chapter 02

Figure 2.1 Multistage lumped amplifier representation.

Figure 2.2 Equalizer design as the double matching problem.

Figure 2.3 Transducer gain for

k

equalizer–transistor stages terminated on

Z

0

.

Figure 2.4 Transducer gain for the first stage terminated on

Z

0

.

Figure 2.5 The design procedure starts from the source with a first equalizer–transistor stage.

Figure 2.6 Once the first equalizer is defined, the second equalizer–transistor stage is added.

Figure 2.7 The procedure is repeated until the

k

th equalizer–transistor stage is added.

Figure 2.8 The final step is to add an additional equalizer to compensate for an arbitrary load

Z

L

.

Figure 2.9 Four-stage amplifier structure used in the example.

Figure 2.10 Optimized transducer gain of intermediary and final stages.

Figure 2.11 Optimized input and output VSWR.

Figure 2.12 Lumped realization of the four-transistor amplifier example.

Figure 2.13 Resistive adaptation at the input and output of the transistor.

Figure 2.14 Transistor with resistive feedback.

Figure 2.15 Transistor with reactive feedback.

Figure 2.16 Modified resistive feedback.

Figure 2.17 General transistor feedback block.

Figure 2.18 Transistor feedback block.

Figure 2.19 Three-stage amplifier structure used in the RFT.

Figure 2.20 Hybrid three-stage 4 MHz to 6 GHz GaAs FET amplifier.

Figure 2.21 Measured and simulated gain and VSWR of the hybrid FET amplifier.

Figure 2.22 Response of the hybrid three-stage FET amplifier to a 5 Gbits/s pulse.

Figure 2.23 Two-stage monolithic amplifier.

Figure 2.24 Measured and simulated gain and VSWR of the two-stage monolithic amplifier.

Figure 2.25 HEMT driver amplifier circuit.

Figure 2.26 Simulated and measured gain of the HEMT driver amplifier circuit.

Chapter 03

Figure 3.1 Multistage distributed amplifier representation.

Figure 3.2 Transducer gain for

k

equalizer–transistor stages terminated on

Z

0

.

Figure 3.3 Transducer gain for the first stage terminated on

Z

0

.

Figure 3.4 Noise figure of the first stage.

Figure 3.5 Bias circuit.

Figure 3.6 Bias circuit modeled as a two-port.

Figure 3.7 Loaded two-port to model the bias circuit.

Figure 3.8 Cascade of the elements in the bias circuit.

Figure 3.9 Extraction of one UE.

Figure 3.10 Extraction of a cascade of UEs.

Figure 3.11 Extraction of stub and cascade of UEs.

Figure 3.12 Equating a UE with a UE with two admittances in parallel.

Figure 3.13 Replacing the admittance in parallel with an open-circuited stub in parallel.

Figure 3.14 UEs with characteristic impedances that are too low.

Figure 3.15 Replacing the UEs with a UE with two admittances in parallel.

Figure 3.16 Replacing the admittances in parallel by open-circuited stubs in parallel.

Figure 3.17 Equating the UE with a UE with two impedances in series.

Figure 3.18 Replacing the impedance in series with a short-circuited stub in series.

Figure 3.19 UEs with characteristic impedances that are too high.

Figure 3.20 Replacing UEs with a UE with two impedances in series.

Figure 3.21 Replacing the impedances in series by short-circuited stubs in series.

Figure 3.22 Optimizing the first equalizer.

Figure 3.23 Optimizing the second equalizer.

Figure 3.24 Optimization of the

k

th equalizer.

Figure 3.25 Optimizing the

equalizer.

Figure 3.26 Three-stage 2–8 GHz amplifier using distributed equalizers.

Figure 3.27 Simulated responses of the three-stage 2–8 GHz amplifier using distributed equalizers.

Figure 3.28 Three-stage 1.15–1.5 GHz amplifier using distributed equalizers.

Figure 3.29 Simulated responses of the three-stage 1.15–1.5 GHz amplifier using distributed equalizers.

Figure 3.30 Three-stage 1.15–1.5 GHz amplifier using equalizers with noncommensurate distributed elements and open stubs (Touchstone

®

optimized).

Figure 3.31 Layout of the three-stage 1.15–1.5 GHz amplifier using noncommensurate distributed equalizers.

Figure 3.32 Measured and simulated gains for the three-stage 1.15–1.5 GHz amplifier.

Figure 3.33 Measured and simulated noise figure for the three-stage 1.15–1.5 GHz amplifier.

Figure 3.34 Three-stage 5.925–6.425 GHz amplifier using distributed equalizers.

Figure 3.35 Layout of the 5.925–6.425 GHz amplifier.

Figure 3.36 Picture of the 5.925–6.425 GHz amplifier.

Figure 3.37 Measured gain of the 5.925–6.425 GHz amplifier.

Chapter 04

Figure 4.1 Multistage transimpedance amplifier.

Figure 4.2 Definitions and properties of the admittance matrix.

Figure 4.3 First transistor–equalizer stage loaded by

Z

L

.

Figure 4.4 Transimpedance gain of

k

transistor–equalizer stages.

Figure 4.5 VSWR for

k

transistor–equalizer stages.

Figure 4.6 Defining the target transimpedance gain for the first stage.

Figure 4.7 Optimizing the first equalizer.

Figure 4.8 Defining the target transimpedance gain for the second stage.

Figure 4.9 Optimizing the second equalizer.

Figure 4.10 Defining the target transimpedance gain for the last stage

k

.

Figure 4.11 Optimizing the last equalizer

k

.

Figure 4.12 Receiver front-end equivalent circuit with noises sources.

Figure 4.13 Lumped two-stage transimpedance amplifier.

Figure 4.14 Distributed two-stage transimpedance amplifier.

Figure 4.15 Simulated transimpedance gain and output return loss for the lumped realization.

Z

t

is the trans-impedance gain and

S

22

is the return loss.

Figure 4.16 Simulated transimpedance gain and output return loss for the distributed realization.

Z

t

is the trans-impedance gain and

S

22

is the return loss (same idea as Fig. 4.15).

Figure 4.17 Simulated input noise current density

when varying inductor

L

f

.

Chapter 05

Figure 5.1 An equalizer is made of a lossy distributed network.

Figure 5.2 Building block of the lossy distributed network.

Figure 5.3 Real network

N

.

Figure 5.4 Image network

.

Figure 5.5 Connecting the real and image networks in parallel.

Figure 5.6 Multistage lossy distributed amplifier representation.

Figure 5.7 Roots of

are complex conjugate and symmetrical around imaginary axis for lossless distributed equalizers.

Figure 5.8 Roots of

are complex conjugate and but no longer symmetrical around imaginary axis for lossy distributed equalizers.

Figure 5.9 Transducer gain for

k

equalizer–transistor stages terminated on

Z

0

.

Figure 5.10 Transducer gain for the first stage terminated on

Z

0

.

Figure 5.11 Richard’s theorem for cascade of lossless UEs.

Figure 5.12 Extracting a parallel resistor and lossless UE from the input impedance of a lossy distributed network.

Figure 5.13 Lossy UE synthesis example.

Figure 5.14 Optimizing the first equalizer.

Figure 5.15 Optimizing the second equalizer.

Figure 5.16 Optimization of the

k

th equalizer.

Figure 5.17 Optimizing the

equalizer.

Figure 5.18 Single-stage amplifier with input and output equalizers.

Figure 5.19 Layout of the single-stage 100 MHz to 5 GHz amplifier.

Figure 5.20 Single-stage and two-stage broadband amplifiers using lossy distributed equalizers.

Figure 5.21 Single-stage amplifier measured and simulated gains.

Figure 5.22 Single-stage amplifier measured and simulated return losses.

Figure 5.23 Two-stage amplifier using three lossy distributed equalizers.

Figure 5.24 Two-stage amplifier simulated gain and return losses.

Figure 5.25 Two-stage amplifier measured gain.

Figure 5.26 Two-stage amplifier measured VSWRs.

Chapter 06

Figure 6.1 Multistage power amplifier representation.

Figure 6.2 Scattering parameter representation for an active two-port device.

Figure 6.3 One-dimensional cubic spline interpolation.

Figure 6.4 Grid concept for spline interpolation.

Figure 6.5 Two-dimensional interpolation of

S

21

using only nine reference points.

Figure 6.6 Last transistor stage connected to load

Z

L

.

Figure 6.7 Situation at the second equalizer.

Figure 6.8 Matching the source impedance.

Figure 6.9 Defining the input and output VSWR.

Figure 6.10 Last transistor stage loaded by

Z

L

.

Figure 6.11 Optimizing equalizer

E

k

.

Figure 6.12 Single-stage power amplifier.

Figure 6.13 Added power simulations using RFCAD-POWER and load-pull simulations using HPADS.

Figure 6.14 Measured and simulated added power.

Figure 6.15 Measured and simulated PAE.

Figure 6.16 Measured and simulated gain.

Figure 6.17 Measured and simulated input return loss.

Figure 6.18 Three-stage power amplifier.

Figure 6.19 Measured and simulated added power.

Figure 6.20 Measured and simulated PAE.

Figure 6.21 Measured and simulated gain.

Figure 6.22

n

identical amplifier modules in parallel.

Figure 6.23 Maximum unilateral transducer gain for one module

M

i

(

S

).

Figure 6.24

n

identical modules in parallel characterized by scattering matrix Σ.

Figure 6.25 Arborescent power amplifier using four identical amplifier modules.

Figure 6.26 Equivalent configuration.

Figure 6.27 Capacitors for equalizers

E

1.

Figure 6.28 Inductors for equalizers

E

1.

Figure 6.29 Arborescence of 2 and 4 paths with 3 cascaded stages.

Figure 6.30 Optimized responses of the linear power amplifier.

Chapter 07

Figure 7.1 Multistage active filter representation.

Figure 7.2 Transducer gain for

k

equalizer–transistor stages terminated on

Z

0

.

Figure 7.3 Transducer gain for the first stage terminated on

Z

0

.

Figure 7.4 The normalized to 1 Ω equalizer. The unit of an inductance is the Henry (H) and the unit of a capacitance is the Farad (F).

Figure 7.5 Optimizing the first equalizer.

Figure 7.6 Optimizing the second equalizer.

Figure 7.7 Optimization the

k

th equalizer.

Figure 7.8 Optimizing the

equalizer.

Figure 7.9 Synthesized two-stage low-pass active filter.

Figure 7.10 Simulated gain and VSWR of the low-pass active filter.

Figure 7.11 Simulated group delay (ns) of the low-pass active filter.

Figure 7.12 Synthesized single-stage bandpass active filter.

Figure 7.13 Simulated gain and VSWR of the single-stage bandpass active filter.

Figure 7.14 Simulated group delay of the single-stage bandpass active filter.

Figure 7.15 Single-stage bandpass active filter.

Figure 7.16 Simulated gain of the active filter.

Figure 7.17 Simulated input return loss of the active filter.

Figure 7.18 Simulated output return loss of the active filter.

Figure 7.19 GaAs MMIC bandpass active filter.

Figure 7.20 Measured and simulated gain of the MMIC active filter.

Figure 7.21 Measured and simulated input return loss of the MMIC active filter.

Figure 7.22 Measured and simulated output return loss of the MMIC active filter.

Chapter 08

Figure 8.1 Target |

S

21

( 

jω

)|

dB

response for the equalizer.

Figure 8.2 Transducer gain for the first stage terminated on

Z

0

.

Figure 8.3 Passive equalizer structure.

Figure 8.4 Target |

S

21

|

dB

response for the equalizer provided by CNES.

Figure 8.5 |

S

21

|

dB

responses: target

and equalizer

.

Figure 8.6 Difference error (dB) between target and equalizer response.

Figure 8.7 |

S

21

|

dB

responses: target

, equalizer with no transmission zeros

, equalizer with two transmission zeros .

Figure 8.8 |

S

21

|

dB

responses: target

, equalizer with transmission zero at 8.0 GHz

, equalizer with transmission zero at 8.02 GHz , equalizer with transmission zeros at 8.03 GHz .

Chapter 09

Figure 9.1 Undesirable returns during transmission.

Figure 9.2 Optimizing an equalizer between circulator and antenna.

Figure 9.3 Antenna-matching equalizer.

Figure 9.4 Return loss without equalizer (dashed line) and with equalizer (solid line).

Figure 9.5 Star antenna equalizer circuit for the 250–350 MHz band.

Figure 9.6 Measured return loss of the star antenna with equalizer circuit in the 250–350 MHz band.

Figure 9.7 Measured |

S

11

|

dB

for the horn antenna without equalizer from 100 to 1200 MHz.

Figure 9.8 Horn antenna equalizer circuit for the 390–440 MHz sub-band.

Figure 9.9 Measured return loss of horn antenna with equalizer circuit for 390–440 MHz sub-band.

Figure 9.10 Simulated insertion and return losses for each of the 21 sub-bands using seventh-order equalizers.

Appendix A

Figure A.1

represents the first

equalizer–transistor stages and

Z

G

.

Figure A.2 Adding the

k

th equalizer–transistor stage to find the gain of the

k

first stages.

Figure A.3 Scattering parameters for the cascade of two scattering matrices.

Figure A.4 First adding the

k

th equalizer.

Figure A.5 Adding the

k

th transistor.

Figure A.6 Starting point for the recursive formula: The first equalizer–transistor pair loaded on

Z

G

.

Figure A.7 Adding a last

equalizer to compensate for an arbitrary load

Z

L

.

Figure A.8 Reflection coefficients used in the transducer power gain.

Figure A.9 Defining the maximum gain for the first equalizer–transistor stage.

Figure A.10 Defining the maximum gain when adding the second equalizer–transistor pair.

Appendix B

Figure B.1 Finding the zero crossing of the

ϕ

(

λ

) function.

Appendix C

Figure C.1 Modeling a noisy two-port as a noiseless two-port with external noise sources.

Figure C.2 Two noisy two-ports.

Figure C.3 Equivalent noisy two-port.

Figure C.4 Two systems connected in cascade.

Figure C.5 Two systems connected in parallel.

Figure C.6 Two systems connected in series.

Figure C.7 Two-port system made of a loaded two-port connected in parallel.

Figure C.8 Two-port system made of a loaded two-port connected in series.

Appendix D

Figure D.1 Lossless two-port and incident and reflected waves.

Figure D.2 Parallel admittance.

Figure D.3 Series impedance.

Figure D.4 Ideal transformer.

Figure D.5 Series inductor.

Figure D.6 Parallel capacitor.

Figure D.7 Parallel inductor.

Figure D.8 Series capacitor.

Figure D.9 Series

LC

cell.

Figure D.10 Parallel

LC

cell.

Guide

Cover

Table of Contents

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MICROWAVE AMPLIFIER AND ACTIVE CIRCUIT DESIGN USING THE REAL FREQUENCY TECHNIQUE

Pierre Jarry and Jacques N. Beneat

Copyright © 2016 by John Wiley & Sons, Inc. All rights reserved

Published by John Wiley & Sons, Inc., Hoboken, New JerseyPublished simultaneously in Canada

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Library of Congress Cataloging-in-Publication Data

Names: Jarry, Pierre, 1946– author. | Beneat, Jacques, 1964–Title: Microwave amplifier and active circuit design using the real frequency technique / Pierre Jarry and Jacques N. Beneat.Description: Hoboken : John Wiley & Sons, Inc., 2016. | Includes bibliographical references and index.Identifiers: LCCN 2015040505 | ISBN 9781119073208 (hardback)Subjects: LCSH: Microwave amplifiers–Design and construction. | Electric filters, Active–Design and construction. | BISAC: TECHNOLOGY & ENGINEERING / Microwaves.Classification: LCC TK7871.2 .J37 2016 | DDC 621.381/325--dc23 LC record available at http://lccn.loc.gov/2015040505

Foreword

It has been a privilege for me to read through the manuscript of the Microwave Amplifier and Active Circuit Design Using the Real Frequency Technique. I found that the authors have been very thorough in putting together this outstanding book containing a unique blend of theory and practice. I sensed that the authors are very passionate about the design of microwave circuits, which is also evidenced from their other recent books.

The book provides an extensive use of an impedance matching methodology, known as the real frequency technique (RFT), in numerous applications. The topics treated include the RFT itself, design of a wide variety of multistage amplifiers, active filters, passive equalizers for radar pulse shaping, and antenna impedance matching applications. All topics are self-contained and also include practical aspects. Extensive analysis and optimization methods for these topics are discussed. The design techniques are well explained by means of solved examples.

The book is divided into nine chapters covering the basics of amplifiers, an overview of RFT, multistage distributed amplifiers, the use of RFT to design trans-impedance microwave amplifiers, the optimization of equalizers employing lossy distributed networks, the use of RFT to design multistage power amplifiers, the design of multistage active filters, the design of equalizers for radar pulse shaping, and antenna impedance matching. To solve impedance matching-related design problems using RFT from specifications to realization of the end product, the book provides a unique integration of analysis/optimization aspects. I found that the book is well balanced and treats the material in depth. With emphasis on theory, design, and practical aspects applied to numerous day-to-day applications, the book is suitable for graduate students, teachers, and design engineers.

Congratulations Profs. Jarry and Beneat on this excellent book that I am confident will be very well received in the RF and microwave community for many years to come.

Inder J. BahlRoanoke, VANovember 2015

Preface

Microwave and radio-frequency (RF) amplifiers play an important role in communication systems, and due to the proliferation of radar, satellite, and mobile wireless systems, there is a need for design methods that can satisfy the ever-increasing demand for accuracy, reliability, and fast development times. This book provides an original design technique for a wide variety of multistage microwave amplifiers and active filters, and passive equalizers for radar pulse shaping and antenna return loss applications. This technique is referred to as the real frequency technique (RFT). It has grown out of the authors own research and teaching and as such has a unity of methodology and style, essential for a smooth reading.