Multi-Mode / Multi-Band RF Transceivers for Wireless Communications E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: Wiley - IEEE
• Sprache: Englisch

Seitenzahl: 955

Veröffentlichungsjahr: 2011

Beschreibung

* Summarizes cutting-edge physical layer technologies for multi-mode wireless RF transceivers. * Includes original contributions from distinguished researchers and professionals. * Covers cutting-edge physical layer technologies for multi-mode wireless RF transceivers. * Contributors are all leading researchers and professionals in this field.

Leseprobe

CONTENTS

Cover

Half Title page

Title page

Copyright page

Preface

Contributors

Part I: Transceiver Concepts and Design

Chapter 1: Software-Defined Radio Front Ends

1.1 Introduction

1.2 System-Level Considerations

1.3 Wideband LO Synthesis

1.4 Receiver Building Blocks

1.5 Transmitter Building Blocks

1.6 Calibration Techniques

1.7 Full SDR Implementation

1.8 Conclusions

References

Chapter 2: Software-Defined Transceivers

2.1 Introduction

2.2 Radio Architectures

2.3 SDR Building Blocks

2.4 Example of an SDR Transceiver

References

Chapter 3: Adaptive Multi-Mode RF Front-End Circuits

3.1 Introduction

3.2 Adaptive Multi-Mode Low-Power Wireless RF IC Design

3.3 Multi-Mode Receiver Concept

3.4 Design of A Multi-Mode Adaptive RF Front End

3.5 Experimental Results for the Image-Reject Down-Converter

3.6 Conclusions

References

Chapter 4: Precise Delay Alignment Between Amplitude and Phase/Frequency Modulation Paths in a Digital Polar Transmitter

4.1 Introduction

4.2 RF Polar Transmitter in Nanoscale CMOS

4.3 Amplitude and Phase Modulation

4.4 Mechanisms to Achieve Subnanosecond Amplitude and Phase Modulation Path Alignments

4.5 Precise Alignment of Multi-Rate Direct and Reference Point Data Modulation Injection in Adpll

References

Chapter 5: Overview of Front-End RF Passive Integration into SoCs

5.1 Introduction

5.2 The Concept of a Receiver Translational Loop

5.3 Feedforward Loop Nonideal Effects

5.4 Feedforward Receiver Circuit Implementations

5.5 Feedforward Receiver Experimental Results

5.6 Feedback Notch Filtering for a WCDMA Transmitter

5.7 Feedback-Based Transmitter Stability Analysis

5.8 Impacts of Nonidealities in Feedback-Based Transmission

5.9 Transmitter Building Blocks

5.10 Feedback-Based Transmitter Measurement Results

Appendix

References

Chapter 6: ADCs and DACs for Software-Defined Radio

6.1 Introduction

6.2 ADC and DAC Requirements in Wireless Systems

6.3 Multi-Standard Transceiver Architectures

6.4 Evaluating Reconfigurability

6.5 ADCs for Software-Defined Radio

6.6 DACs for Software-Defined Radio

6.7 Conclusions

References

Part II: Receiver Design

Chapter 7: OFDM Transform-Domain Receivers for Multi-Standard Communications

7.1 Introduction

7.2 Transform-Domain Receiver Background

7.3 Transform-Domain Sampling Receiver

7.4 Digital Baseband Design for The TD Receiver

7.5 A Comparative Study

7.6 Simulations

7.7 Bandwidth Product Requirement For an OP-AMP in a Charge-Sampling Circuit

7.8 Sparsity of (GHG)−1

7.9 Applications

7.10 Conclusions

References

Chapter 8: Discrete-Time Processing of RF Signals

8.1 Introduction

8.2 Scaling of an MOS Switch

8.3 Sampling Mixer

8.4 Filter Synthesis

8.5 Noise in Switched-Capacitor Filters

8.6 Circuit-Design Considerations

8.7 Perspective and Outlook

References

Chapter 9: Oversampled ADC Using VCO-Based Quantizers

9.1 Introduction

9.2 VCO-Quantizer Background

9.3 SNDR Limitations for VCO-Based Quantization

9.4 VCO Quantizer ∑Δ ADC Architecture

9.5 Prototype ∑Δ ADC Example with a VCO Quantizer

9.6 Conclusions

References

Chapter 10: Reduced External Hardware and Reconfigurable RF Receiver Front Ends for Wireless Mobile Terminals

10.1 Introduction

10.2 Mobile Terminal Challenges

10.3 Research Directions Toward a Multi-Band Receiver

10.4 Multi-Mode Receiver Principles and RF System Analysis for A W-CDMA Receiver

10.5 W-CDMA, GSM/GPRS/EDGE Receiver Front End Without an Interstage Saw Filter

10.6 Highly Integrated GPS Front End for Cellular Applications in 90-nm CMOS

10.7 RX Front-END Performance Comparison

References

Chapter 11: Digitally Enhanced Alternate Path Linearization of RF Receivers

11.1 Introduction

11.2 Adaptive Feedforward Error Cancellation

11.3 Architectural Concepts

11.4 Alternate Feedforward Path Block Design Considerations

11.5 Experimental Design of an Adaptively Linearized UMTS Receiver

11.6 Experimental Results of an Adaptively Linearized UMTS Receiver

11.7 Conclusions

References

Part III: Transmitter Techniques

Chapter 12: Linearity and Efficiency Strategies for Next-Generation Wireless Communications

12.1 Introduction

12.2 Power Amplifier Function

12.3 Power Amplifier Efficiency Enhancement

12.4 Techniques for Linearity Enhancement

12.5 Conclusions

References

Chapter 13: Cmos RF Power Amplifiers for Mobile Communications

13.1 Introduction

13.2 Challenges

13.3 Low Supply Voltage

13.4 Average Efficiency, Dynamic Range, and Linearity

13.5 Polar Modulation

13.6 Distortion in a Polar-Modulated POwer Amplifier

13.7 Design And Implementation of a Polar-Modulated Power Amplifier for Gsm-Edge

13.8 Conclusions

References

Chapter 14: Digitally Assisted RF Architectures: Two Illustrative Designs

14.1 Introduction

14.2 Cartesian Feedback: the Analog Problem

14.3 Digital Assistance for Cartesian Feedback

14.4 Multipliers, Squarers, Mixers, and Vgas: The Analog Problem

14.5 Digital Assistance for Analog Multipliers

14.6 Summary

Appendix: Stability Analysis for Cartesian Feedback Systems

References

Part IV: Digital Signal Processing for RF Transceivers

Chapter 15: RF Impairment Compensation for Future Radio Systems

15.1 Introduction and Motivation

15.2 Typical RF Impairments

15.3 Impairment Mitigation Principles

15.4 Case Studies in I/Q Imbalance Compensation

15.5 Conclusions

References

Chapter 16: Techniques for the Analysis of Digital Bang-Bang PLLs

16.1 Introduction

16.2 Digital Bang-Bang Pll Architecture

16.3 Analysis of the Nonlinear Dynamics of the BBPLL

16.4 Analysis of the BBPLL with Markov Chains

16.5 Linearization of the BBPLL

16.6 Comparison of Measurements and Models

References

Chapter 17: Low-Power Spectrum Processors for Cognitive Radios

17.1 Introduction

17.2 Paradigm Shift from SDR to CR

17.3 Challenge and Trends in Rfic/System

17.4 Analog Signal Processing

17.5 Spectrum Sensing

17.6 Multi-Resolution Spectrum Sensing

17.7 Mrss Performance

17.8 Conclusions

References

Index

MULTI-MODE/MULTI-BAND RF TRANSCEIVERS FOR WIRELESS COMMUNICATIONS

Copyright © 2011 by John Wiley & Sons, Inc. All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.

Published simultaneously in Canada.

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Library of Congress Cataloging-in-Publication Data:

Multi-mode/multi-band RF transceivers for wireless communications : advanced techniques, architectures, and trends / edited by Gernot Hueber and Robert Bogdan Staszewski.p.cm.Includes bibliographical references and index.ISBN 978-0-470-27711-91. Radio–Transmitter-receivers. 2. Wireless communication systems–Equipment and supplies–Design and construction. 3. Cellular telephones–Design and construction.4. Wireless LANs–Equipment and supplies–Design and construction. I. Hueber, Gernot, 1972– II. Staszewski, Robert Bogdan, 1965–TK6564.3.M85  2011384.5–3–dc22

2010001881

CONTRIBUTORS

PETER ASBECK, University of California at San Diego, La Jolla, California

GIO CAFARO, Motorola Labs, Plantation, Florida

KOEN CORNELISSENS, Katholieke Universiteit Leuven, Leuven, Belgium

JAN CRANINCKX, IMEC, Leuven, Belgium

NICOLA DA DALT, Infineon Technologies, Villach, Austria

HOOMAN DARABI, Broadcom Corporation, Irvine, California

JOEL L. DAWSON, Massachusetts Institute of Technology, Cambridge, Massachusetts

ALI HAJIMIRI, California Institute of Technology, Pasadena, California

SEBASTIAN HOYOS, Texas A&M University, College Station, Texas

EDWARD A. KEEHR, California Institute of Technology, Pasadena, California

DONALD KIMBALL, University of California at San Diego, La Jolla, California

LAWRENCE LARSON, University of California at San Diego, La Jolla, California

JOY LASKAR,Georgia Tech, Atlanta, Georgia

KYUTAE LIM,Georgia Tech, Atlanta, Georgia

BORIVOJE NIKOLI, University of California, Berkeley, California

PIETER PALMERS, Katholieke Universiteit Leuven, Leuven, Belgium

MICHAEL H. PERROTT, Massachusetts Institute of Technology, Cambridge, Massachusetts

PATRICK REYNAERT, Katholieke Universiteit Leuven, Leuven, Belgium

ROBERT BOGDAN STASZEWSKI, Texas Instruments, Dallas, Texas; currently at Delft University of Technology, Delft, The Netherlands

BOB STENGEL, Motorola Labs, Plantation, Florida

MICHIEL STEYAERT, Katholieke Universiteit Leuven, Leuven, Belgium

MATTHEW Z. STRAAYER, Massachusetts Institute of Technology, Cambridge, Massachusetts

ALEXANDER TASIC, Qualcomm, San Diego, California

MIKKO VALKAMA, Tampere University of Technology, Tampere, Finland

KHURRAM WAHEED, Texas Instruments, Dallas, Texas; currently at BitWave Semiconductors, Lowell, Massachusetts

RENALDI WINOTO, University of California, Berkeley, California

NAVEEN K. YANDURU, Texas Instruments, Dallas, Texas; currently at University of Texas at Dallas, Richardson, Texas

Preface

Current and future mobile terminals become increasingly complex because they have to deal with a variety of frequency bands and communication standards. Achieving multi-band/multi-mode functionality is especially challenging for the radio frequency (RF)-transceiver section, due to limitations in terms of frequency-agile RF components that meet the demanding cellular performance criteria at costs that are attractive for mass-market applications. The focus of this volume is on novel transceiver concepts for multi-mode/multi-band cellular systems from the antenna to baseband. One approach is based on the integration of digital signal processing capabilities implemented locally on the RF integrated circuit. The utilization of digital signal processing capabilities is in line with the ongoing trend toward minimum-feature-sized RF-CMOS in the cellular market, which makes it extremely attractive in terms of flexibility, power consumption, and costs. Moreover, advances in the field of antennas, RF-front-end modules and novel analog signal processing architectures are covered to give a consolidated outlook on future concepts for cellular radios.

This volume summarizes cutting-edge physical-layer technologies for multi-mode wireless RF transceivers, specifically RF, analog, and digital circuits and architectures, anticipating the major trends and needs of the future wireless system developments. Firsthand materials from distinguished researchers and professionals from both academia and industry are collected. Furthermore, this volume offers a comprehensive treatment of the topic, presenting state-of-the-art technologies and insight covering all the essential transceiver building blocks to be used in future multi-mode (third generation and beyond) wireless communication systems.

G. HUEBER

R. B. STASZEWSKI

PART I

Transceiver Concepts and Design

Chapter 1

Software-Defined Radio Front Ends

JAN CRANINCKX

IMEC, Leuven, Belgium

1.1 INTRODUCTION

The ultimate dream of every software-defined radio (SDR) front-end architect is to deliver a radio-frequency (RF) transceiver that can be reconfigured into every imaginable operating mode, in order to comply with the requirements of all existing and even upcoming communication standards. These include a large range of modes for cellular (2G–2.5G–3G and further), WLAN (802.11a/b/g/n), WPAN (Bluetooth, Zigbee, etc.), broadcasting (DAB, DVB, DMB, etc.), and positioning (GPS, Galileo) functionalities. Obviously, each of them has different center frequency, channel bandwidth, noise levels, interference requirements, transmit spectral mask, and so on. As a consequence, the performances of all building blocks in the transceiver must be reconfigurable over an extremely wide range, requiring ultimate creativity from the SDR designer.

Reconfigurability is a requirement for SDR functionality, but often one forgets that it can also be an enabler for low power consumption. Indeed, once flexibility is built into a transceiver, it can be used to adapt the performance of a radio to the actual circumstances instead of those implied by the worst-case situation of the standard. Since linearity, filtering, noise, bandwidth, and so on, can be traded for power consumption in the SDR, a smart controller is able to adapt the radio at runtime to the actual performance required, and hence can reduce the average power consumption of the SDR.

In this chapter, several important innovations and concepts are presented that bring this ultimate dream closer to reality. These include circuits for wideband local oscillator (LO) synthesis, multifunctional receiver and transmitter blocks, and novel ADC (analog-to-digital converter) implementations. The result of all this is integrated in the world’s first SDR transceiver covering the frequency range from 174 MHz to 6 GHz, implemented in a 1.2-V 0.13-μ CMOS technology.

1.2 SYSTEM-LEVEL CONSIDERATIONS

A first choice to be made is the radio architecture to be used. In past decades, lots of studies and examples have been presented on heterodyne, homodyne, low-IF (intermediate frequency), wideband-IF, and other architectures, all having certain benefits and problems for a certain application. Which one to choose? In view of SDR, this question perhaps becomes a little easier to answer. Indeed, when the characteristics of all possible standards are taken into account, not a single intermediate frequency can be found that suits them all. And having multiple IFs and the associated (external) filtering stages increases the hardware cost of the SDR, which cannot be tolerated. So direct-conversion architectures are the right choice for the job. All of the well-known problems, such as dc offsets, I/Q mismatch, 1/f noise, and power amplifier (PA) pulling, that have limited the proliferation of zero-IF CMOS radios into mainstream products have been better understood in recent years, and it will enable the design of a low-cost front end.

A schematic vision of what the final SDR will look like is represented in Fig. 1.1. For a low cost in a large-volume consumer market, the active transceiver core is implemented in a plain CMOS technology. It includes a fully reconfigurable direct-conversion receiver, transmitter, and two synthesizers [for frequency-domain duplex (FDD) operation]. The functions that cannot be implemented in CMOS are included on the package substrate. These are related primarily to the interface between the active core and the antenna. They must provide high-Q bandpass filtering or even duplexing, impedance-matching circuits, and power amplification. In the remainder of the chapter we focus primarily on the transceiver implementation.

FIGURE 1.1 Conceptual view of an SDR transceiver front end.

The hard works starts with determining performance specifications for each block in the chain. The total budget for gain, noise, linearity, and so on, must be divided over all blocks, ensuring that all possible test cases are covered, and this must be done for every standard. Having very flexible building blocks helps a great deal, of course, but making a smart system analysis at this point is crucial to obtaining an optimal SDR solution.

A custom MATLAB tool has been developed to do this exercise [1]. It takes in a netlist that describes all building blocks, with the performance characteristics and gain ranges, and simulates on a behavioral level the complete chain for a list of different test cases. Figure 1.2 shows a screenshot. The performance under all circumstances can thus be evaluated, and the building block performance can be tuned to fulfill all requirements. Gain ranges and signal filtering must be set such that the signal levels are an optimal trade-off between noise and distortion. Although being a difficult exercise, the analysis can show that with the built-in flexibility, a software-defined radio can achieve state-of-the-art performance very close to that of dedicated single-mode solutions. In the next sections we go deeper into the design of some crucial building blocks.

FIGURE 1.2 System-level analysis tool.

1.3 WIDEBAND LO SYNTHESIS

To generate all required LO signals in the range 0.1 to 6 GHz, several frequency-generation techniques have been proposed to relax the tuning range specifications of a voltage-controlled oscillator (VCO). They use division, mixing, multiplication, or a combination of these [2]. However, to make these systems efficient in terms of phase noise and power consumption, the VCO tuning range still has to be maximized. In the following section we discuss the design of such a wideband VCO, and the architecture required to generate all LO signals is discussed in Section 1.3.2. The target frequency band of the VCO is around 4 GHz, so that it does not coincide with any of the major RF frequency bands used. The actual LO frequency will be obtained by further division and mixing. Since the VCO frequency differs from the RF frequency, most direct-conversion problems will be relaxed or avoided.