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- Herausgeber: John Wiley & Sons
- Kategorie: Wissenschaft und neue Technologien
- Sprache: Englisch
A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes Architectures and Applications therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades. Multi-Processor System-on-Chip 2 covers application-specific MPSoC design, including compilers and architecture exploration. This second volume describes optimization methods, tools to optimize and port specific applications on MPSoC architectures. Details on compilation, power consumption and wireless communication are also presented, as well as examples of modeling frameworks and CAD tools. Explanations of specific platforms for automotive and real-time computing are also included.
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Seitenzahl: 421
Veröffentlichungsjahr: 2021
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Table of Contents
Cover
Title Page
Copyright
Foreword
Acknowledgments
PART 1: MPSoC for Telecom
1 From Challenges to Hardware Requirements for Wireless Communications Reaching 6G
1.1. Introduction
1.2. Breadth of workloads
1.3. GFDM algorithm breakdown
1.4. Algorithm precision requirements and considerations
1.5. Implementation
1.6. Conclusion
1.7. Acknowledgments
1.8. References
2 Towards Tbit/s Wireless Communication Baseband Processing: When Shannon meets Moore
2.1. Introduction
2.2. Role of microelectronics
2.3. Towards 1 Tbit/s throughput decoders
2.4. Conclusion
2.5. Acknowledgments
2.6. References
PART 2: Application-specific MPSoC Architectures
3 Automation for Industry 4.0 by using Secure LoRaWAN Edge Gateways
3.1. Introduction
3.2. Security in IIoT
3.3. LoRaWAN security in IIoT
3.4. Threat model
3.5. Trusted boot chain with STM32MP1
3.6. LoRaWAN gateway with STM32MP1
3.7. Discussion and future scope
3.8. Acknowledgments
3.9. References
4 Accelerating Virtualized Distributed NVMe Storage in Hardware
4.1. Introduction
4.2. Motivation: NVMe storage for the cloud
4.3. Design
4.4. Implementation
4.5. Results
4.6. Conclusion
4.7. References
5 Modular and Open Platform for Future Automotive Computing Environment
5.1. Introduction
5.2. Outline of this approach
5.3. Results
5.4. Use case
5.5. Conclusion
5.6. References
6 Post-Moore Datacenter Server Architecture
6.1. Introduction
6.2. Background: today’s blades are from the desktops of the 1980s
6.3. Memory-centric server design
6.4. Data management accelerators
6.5. Integrated network controllers
6.6. References
PART 3: Architecture Examples and Tools for MPSoC
7 SESAM: A Comprehensive Framework for Cyber–Physical System Prototyping
7.1. Introduction
7.2. An overview of the SESAM platform
7.3. VPSim: fast and easy virtual prototyping
7.4. Hybrid prototyping
7.5. FMI for co-simulation
7.6. Conclusion
7.7. References
8 StaccatoLab: A Programming and Execution Model for Large-scale Dataflow Computing
8.1. Introduction
8.2. Static dataflow
8.3. Dynamic dataflow
8.4. Dataflow execution models
8.5. StaccatoLab
8.6. Large-scale dataflow computing?
8.7. Acknowledgments
8.8. References
9 Smart Cameras and MPSoCs
9.1. Introduction
9.2. Early VLSI video processors
9.3. Video signal processors
9.4. Accelerators
9.5. From VSP to MPSoC
9.6. Graphics processing units
9.7. Neural networks and tensor processing units
9.8. Conclusion
9.9. References
10 Software Compilation and Optimization Techniques for Heterogeneous Multi-core Platforms
10.1. Introduction
10.2. Dataflow modeling
10.3. Source-to-source-based compiler infrastructure
10.4. Software distribution
10.5. Results
10.6. Conclusion
10.7. References
List of Authors
Author Biographies
Index
End User License Agreement
List of Tables
Chapter 1
Table 1.1. Processing requirement corners as per standard specification
Table 1.2. Kernel parameters for corner use cases
Table 1.3. Selected GFDM implementation variants
Table 1.4. Kernel profile: cycles, memory accesses, and density
Table 1.5. GFDM: required frequency budget and performance on our vDSP
Chapter 2
Table 2.1. Implementation properties of various coding schemes
Chapter 8
Table 8.1. A comparison of large FFTs mapped onto a GPU and an FPGA
Table 8.2. A comparison of the four back-pressure schemes of Figure 8.18
Table 8.3. A summary of the StaccatoLab execution model
Chapter 10
Table 10.1. Retargeting MAPS towards MPSoC platforms
Guide
Cover
Table of Contents
Title Page
Copyright
Foreword
Acknowledgments
Begin Reading
List of Authors
Author Biographies
Index
End User License Agreement
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To my parents, sisters and husband, the loves and pillars of my life.
Liliana ANDRADE
I express my profound gratitude to Karine, my parents and all my family, for their help and support throughout all these years.
Frédéric ROUSSEAU
SCIENCES
Electronics Engineering, Field Director – Francis Balestra
Design Methodologies and Architecture,Subject Head – Ahmed Jerraya
Multi-Processor System-on-Chip 2
Applications
Coordinated by
Liliana Andrade
Frédéric Rousseau
First published 2020 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.
Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:
ISTE Ltd
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www.iste.co.uk
John Wiley & Sons, Inc.
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USA
www.wiley.com
© ISTE Ltd 2020
The rights of Liliana Andrade and Frédéric Rousseau to be identified as the authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988.
Library of Congress Control Number: 2020940076
British Library Cataloguing-in-Publication Data
A CIP record for this book is available from the British Library
ISBN 978-1-78945-022-4
ERC code:
PE6 Computer Science and Informatics
PE6_1 Computer architecture, pervasive computing, ubiquitous computing
PE6_10 Web and information systems, database systems, information retrieval and digital libraries, data fusion
PE7 Systems and Communication Engineering
PE7_2 Electrical engineering: power components and/or systems
Foreword
Ahmed JERRAYA
Cyber Physical Systems Programs, CEATech, Grenoble, France
Multi-core and multi-processor SoC (MPSoC) concepts started in the late 1990s, mainly to mitigate the complexity of application-specific integrated circuits (ASICs) and to bring some flexibility. The integration of instruction-set processors into ASIC design aimed both to structure the architecture and to allow for programmability. The concept was adopted for general-purpose CPU and GPU in the second phase. Among the pioneers of MPSoC design, we can list the MPA architecture from ST that used eight specific cores to implement MPEG4 in 1998. This evolved 10 years later to give rise to MPPA, the Kalray’s general-purpose MPSoC architecture. Another pioneer is the emotion engine from Sony that used five cores (two DSP and three RISC) to build the application processor for the PlayStation (PS2). This also evolved and later converged to bring the CELL architecture (developed jointly by Sony, IBM and Toshiba) in 2005. In 2000, Lucent announced Daytona (quad SPARC V8), and in 2001, Philips designed the famous Viper architecture that combined a MIPS architecture and a DSP (Trimedia). In 2004, TI introduced the OMAP architecture that combined an ARM and a DSP. Using MPSoC to build specific architectures is continuing, and almost every SoC produced today is a multi (or many) core architecture. An important evolution took place in 2005 with the ARM MPCore, the first general-purpose quad core. This was followed by several commercial, general-purpose multi-cores, including Intel Core Duo Pentium, AMD Opteron, Niagra Spark, the Cell processor (8 Cell cores + PowerPC, ring network).
MPSoC started a new computing era, but brought a twofold challenge: building multi-core HW that can be used easily by SW designers, and building distributed SW that fully exploits HW capabilities. To deal with these challenges, the design communities from Academia and Industry began a series of conferences and workshops to rethink classical distributed computing. The study of new methods, models and tools to deal with these new distributed HW and SW architectures generated new concepts, such as the interconnect architectures called network-on-chip (NoC). The MPSoC Forum, created in 2001, was the first interdisciplinary forum that brought together the leading thinkers from the different fields to design multi-core and multi-processor SoC. Over the last 20 years, MPSoC was a unique opportunity for me to meet so many of the world’s top researchers and to communicate with them in person, in addition to enjoying the high-quality conference programs. The confluence of academic and industrial perspectives, and hardware and software, makes MPSoC not “yet another conference”. I have learned how emerging SW and HW design technologies and architectures can benefit from advanced semiconductor manufacturing technologies to build energy-efficient multi-core architectures that can serve advanced computing (image, vision and cloud) and distributed networked systems. This book, in two volumes (Architectures and Applications), was published to celebrate the 20th anniversary of MPSoC with outstanding contributions from previous MPSoC events.
This first volume on architectures covers the key components of MPSoC: processors, memory, interconnect and interfaces.
Acknowledgments
Liliana ANDRADE and Frédéric ROUSSEAU
Université Grenoble Alpes, CNRS, Grenoble INP, TIMA, 38000 Grenoble, France
The editors are indebted to the MPSoC community who made this book possible. First of all, they acknowledge the societies that supported this project. EDAA and IEEE/CAS partially funded the organization of the first two events. Since its creation, IEEE/CEDA has sponsored the event. Industrial sponsors played a vital role in keeping MPSoC alive for the last 20 years; special thanks to Synopsys, Arteris, ARM, XILINX and Socionext. The event was created by a nucleus of several people who now form the steering committee (Ahmed Jerraya, Hannu Tenhunen, Marilyn Wolf, Masaharu Imai and Hiroto Yasuura). A larger group has, for the last 20 years, been working to form the community (Nicolas Ventroux, Jishen Zhao, Tsuyoshi Isshiki, Frédéric Rousseau, Anca Molnos, Gabriela Nicolescu, Hiroyuki Tomiyama, Masaaki Kondo, Hiroki Matsutani, Tohru Ishihara, Pierre-Emmanuel Gaillardon, Yoshinori Takeuchi, Tom Becnel, Frédéric Pétrot, Yuan Xie, Koji Inoue, Masaaki Kondo, Hideki Takase and Raphaël David). The editors would like to acknowledge the outstanding contribution of the MPSoC speakers, and especially those who contributed to the chapters of this book. Finally, the editors would like to thank the people who participated in the careful reading of this book (Breytner Fernandez and Bruno Ferres).
