NAND Flash Memory Technologies E-Book

Seiichi Aritome

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: IEEE Press Series on Microelectronic Systems
• Sprache: Englisch

Seitenzahl: 727

Veröffentlichungsjahr: 2015

Beschreibung

* Offers a comprehensive overview of NAND flash memories, with insights into NAND history, technology, challenges, evolutions, and perspectives * Describes new program disturb issues, data retention, power consumption, and possible solutions for the challenges of 3D NAND flash memory * Written by an authority in NAND flash memory technology, with over 25 years' experience

Leseprobe

IEEE Press445 Hoes LanePiscataway, NJ 08854

IEEE Press Editorial BoardTariq Samad, Editor in Chief

George W. Arnold   Vladimir Lumelsky    Linda ShaferDmitry Goldgof        Pui-In Mak               Zidong WangEkram Hossain        Jeffrey Nanzer         MengChu ZhouMary Lanzerotti    Ray Perez             George Zobrist

Kenneth Moore, Director of IEEE Book and Information Services (BIS)

Technical Reviewers

Joe E Brewer, PE, Electronic Engineering ConsultantChandra Mouli, Director, R&D Device Technology, Micron Technology Inc, Boise ID, USAGabriel Molas, CEA LETI Minatec, Grenoble, France

NAND FLASH MEMORY TECHNOLOGIES

SEIICHI ARITOME

Copyright © 2016 by The Institute of Electrical and Electronics Engineers, Inc.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved Published simultaneously in Canada

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Library of Congress Cataloging-in-Publication Data is available.

ISBN: 978-1-119-13260-8

CONTENTS

Foreword

Preface

Acknowledgments

About the Author

1 Introduction

1.1 Background

1.2 Overview

References

2 Principle of NAND Flash Memory

2.1 NAND Flash Device and Architecture

2.2 Cell Operation

2.3 Multilevel Cell (MLC)

References

3 NAND Flash Memory Devices

3.1 Introduction

3.2 LOCOS Cell

3.3 Self-Aligned STI Cell (SA-STI Cell) with FG Wing

3.4 Self-Aligned STI Cell (SA-STI Cell) without FG Wing

3.5 Planar FG Cell

3.6 SideWall Transfer Transistor Cell (SWATT Cell)

3.7 Advanced NAND Flash Device Technologies

References

4 Advanced Operation for Multilevel Cell

4.1 Introduction

4.2 Program Operation for Tight

V

t

Distribution Width

4.3 Page Program Sequence

4.4 TLC (3 Bits/Cell)

4.5 QLC (4 Bits/Cell)

4.6 Three-Level (1.5 bits/cell) NAND flash

4.7 Moving Read Algorithm

References

5 Scaling Challenge of NAND Flash Memory Cells

5.1 Introduction

5.2 Read Window Margin (RWM)

5.3 Floating-Gate Capacitive Coupling Interference

5.4 Program Electron Injection Spread

5.5 Random Telegraph Signal Noise (RTN)

5.6 Cell Structure Challenge

5.7 High-Field Limitation

5.8 A few electron phenomena

5.9 Patterning Limitation

5.10 Variation

5.11 Scaling impact on Data Retention

5.12 Summary

References

6 Reliability of NAND Flash Memory

6.1 Introduction

6.2 Program/Erase Cycling Endurance and Data Retention

6.3 Analysis of Program/Erase Cycling Endurance and Data Retention

6.4 Read Disturb

6.5 Program Disturb

6.6 Erratic Over-Program

6.7 Negative

V

t

shift phenomena

6.8 Summary

References

7 Three-Dimensional NAND Flash Cell

7.1 Background of Three-Dimensional NAND cells

7.2 BiCS (Bit Cost Scalable technology) / P-BiCS (Pipe-shape BiCS)

7.3 TCAT (Terabit Cell Array Transistor)/V-NAND (Vertical-NAND)

7.4 SMArT (Stacked Memory Array Transistor)

7.5 VG-NAND (Vertical Gate NAND Cell)

7.6 Dual Control gate—Surrounding Floating gate Cell (DC-SF cell)

7.7 Advanced DC-SF cell

References

8 Challenges of Three-Dimensional NAND Flash Memory

8.1 Introduction

8.2 Comparison of 3D NAND cells

8.3 Data Retention

8.4 Program Disturb

8.5 Word-Line RC delay

8.6 Cell Current Fluctuation

8.7 Number of Stacked Cells

8.8 Peripheral Circuit Under Cell Array

8.9 Power Consumption

8.10 Future Trend of 3D NAND Flash Memory

References

9 Conclusions

9.1 Discussions and conclusions

9.2 Perspective

References

Index

IEEE Press Series on Microelectronic Systems

EULA

List of Tables

Chapter 1

Table 1.1

Chapter 3

Table 3.1

Table 3.2

Table 3.3

Table 3.4

Table 3.5

Chapter 5

Table 5.1

Chapter 6

Table 6.1

Table 6.2

Chapter 7

Table 7.1

Table 7.2

Table 7.3