Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing E-Book

Jayasimha Atulasimha

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 784

Veröffentlichungsjahr: 2016

Beschreibung

Nanomagnetic and spintronic computing devices are strong contenders for future replacements of CMOS. This is an important and rapidly evolving area with the semiconductor industry investing significantly in the study of nanomagnetic phenomena and in developing strategies to pinpoint and regulate nanomagnetic reliably with a high degree of energy efficiency. This timely book explores the recent and on-going research into nanomagnetic-based technology.

Key features:

• Detailed background material and comprehensive descriptions of the current state-of-the-art research on each topic.
• Focuses on direct applications to devices that have potential to replace CMOS devices for computing applications such as memory, logic and higher order information processing.
• Discusses spin-based devices where the spin degree of freedom of charge carriers are exploited for device operation and ultimately information processing.
• Describes magnet switching methodologies to minimize energy dissipation.
• Comprehensive bibliographies included for each chapter enabling readers to conduct further research in this field.

Written by internationally recognized experts, this book provides an overview of a rapidly burgeoning field for electronic device engineers, field-based applied physicists, material scientists and nanotechnologists. Furthermore, its clear and concise form equips readers with the basic understanding required to comprehend the present stage of development and to be able to contribute to future development. Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing is also an indispensable resource for students and researchers interested in computer hardware, device physics and circuits design.

Leseprobe

In memory of my late great-uncle, N. Seshagiri,who inspired my career in science and technology.Jayasimha AtulasimhaIn memory of my uncle.Supriyo Bandyopadhyay

NANOMAGNETIC AND SPINTRONIC DEVICES FOR ENERGY-EFFICIENT MEMORY AND COMPUTING

Edited by

Jayasimha Atulasimha and Supriyo BandyopadhyayVirginia Commonwealth University, US

This edition first published 2016 © 2016 John Wiley & Sons Ltd.

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Library of Congress Cataloging-in-Publication Data

Nanomagnetic and spintronic devices for energy-efficient memory and computing / edited by Jayasimha Atulasimha and Supriyo Bandyopadhyay.  pages cm Includes bibliographical references and index. ISBN 978-1-118-86926-0 (cloth) 1. Magnetic memory (Computers) 2. Spintronics. 3. Nanoelectronics. I. Atulasimha, Jayasimha, editor. II. Bandyopadhyay, S., editor. TK7895.M3N27 2016 621.39′73--dc23

2015033564

A catalogue record for this book is available from the British Library.

Cover image: The cover shows magnetic force micrographs of an array of 100-nm sized nanomagnets exhibiting single-domain behavior. Image courtesy of the Atulasimha group and Bandyopadhyay group.

Contents

About the Editors and Acknowledgments

List of Contributors

Foreword

Preface

CHAPTER 1 Introduction to Spintronic and Nanomagnetic Computing Devices

1.1 Spintronic Devices

1.2 Nanomagnetic Devices

1.3 Thinking beyond Traditional Boolean Logic

References

CHAPTER 2 Potential Applications of all Electric Spin Valves Made of Asymmetrically Biased Quantum Point Contacts

2.1 Introduction

2.2 Quantum Point Contacts

2.3 Spin Orbit Coupling

2.4 Importance of Spin Relaxation in 1D Channels

2.5 Observation of a 0.5 Conductance Plateau in Asymmetrically Biased QPCs in the Presence of LSOC

2.6 Intrinsic Bistability near Conductance Anomalies

2.7 QPC Structures with Four In-plane SGs: Toward an All Electrical Spin Valve

2.8 Future Work

2.9 Summary

2.10 Acknowledgments

References

CHAPTER 3 Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems

3.1 Spin-Transistor and Pseudo-Spin-Transistor

3.2 Energy-Efficient Logic Applications of Spin-Transistors

3.3 Nonvolatile SRAM Technology

3.4 Application of Nonvolatile Bistable Circuits for Memory Systems

References

CHAPTER 4 Spin Transfer Torque: A Multiscale Picture

4.1 Introduction

4.2 The Physics of Spin Transfer Torque

4.3 First Principles Evaluation of TMR and STT

4.4 Magnetization Dynamics

4.5 Summary: Multiscaling from Atomic Structure to Error Rate

4.6 Acknowledgments

References

CHAPTER 5 Magnetic Tunnel Junction Based Integrated Logics and Computational Circuits

5.1 Introduction

5.2 GMR Based Field Programmable Devices

5.3 MTJ Based Field Programmable Devices

5.4 Information Transformation between Gates

5.5 MTJ Based Logic-in-Memory Devices

5.6 Magnetic Quantum Cellular Automata

5.7 All-Spin Based Magnetic Logic

5.8 Summary

5.9 Acknowledgment

References

CHAPTER 6 Magnetization Switching and Domain Wall Motion Due to Spin Orbit Torque

6.1 Introduction

6.2 Theory

6.3 Magnetic Switching Driven by Spin Orbit Torque

6.4 Domain Wall Motion Driven by Spin Orbit Torque

6.5 Applications of Spin Orbit Torque

6.6 Conclusion

References

CHAPTER 7 Magnonic Logic Devices

7.1 Introduction

7.2 Magnonic Logic Devices

7.3 Spin Wave-Based Logic Gates and Architectures

7.4 Discussion and Summary

References

CHAPTER 8 Strain Mediated Magnetoelectric Memory

8.1 Introduction

8.2 Concept of Unequivocal Strain- or Stress-Switched Nanomagnetic Memory

8.3 LLG Simulations – Macrospin Model

8.4 LLG Simulations – Eshelby Approach

8.5 Stochastic Error Analysis

8.6 Preliminary Experimental Results

8.7 Conclusions

8.8 Acknowledgments

References

CHAPTER 9 Hybrid Spintronics-Strainronics

9.1 Introduction

9.2 Nanomagnetic Memory Switched with Strain

9.3 Straintronic Clocking of Nanomagnetic Logic

9.4 Summary and Conclusions

References

CHAPTER 10 Unconventional Nanocomputing with Physical Wave Interference Functions*

10.1 Overview

10.2 Spin Waves Physical Layer for WIF Implementation

10.3 Elementary WIF Operators for Logic

10.4 Binary WIF Logic Design

10.5 Multivalued WIF Logic Design

10.6 Microprocessors with WIF: Opportunities and Challenges

10.7 Summary and Future Work

Note

References

Index

Supplemental Images

EULA

List of Tables

Chapter 3

Table 3.1

Table 3.2

Chapter 5

Table 5.1

Chapter 7

Table 7.1

Chapter 8

Table 8.1

Table 8.2

Table 8.3

Chapter 10

Table 10.1

Table 10.2

Table 10.3

Table 10.4

Table 10.5

Table 10.6

Table 10.7

Table 10.8

Table 10.9

Table 10.10

Table 10.11