Nanoscale CMOS E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Fachliteratur
• Sprache: Englisch

Seitenzahl: 1029

Veröffentlichungsjahr: 2013

Beschreibung

This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future - in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices. This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies. It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling. The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy.

Leseprobe

Table of Contents

Introduction

Part 1: Novel Materials for Nanoscale CMOS

Chapter 1: Introduction to Part 1

1.1. Nanoscale CMOS requirements

1.2. The gate stack - high-κ dielectrics

1.3. Strained channels

1.4. Source-drain contacts

1.5. Bibliography

Chapter 2: Gate Stacks

2.1. Gate-channel coupling in MOSFETs

2.2. Properties of dielectrics

2.3. Interfaces states and bulk oxide traps

2.4. Two ternary compounds: GdSiO and LaSiO

2.5. Metal gate technology

2.6. Future outlook

2.7. Bibliography

Chapter 3: Strained Si and Ge Channels

3.1. Introduction

3.2. Relaxation of strained layers

3.3. High Ge composition Si1-xGex buffers

3.4. Ge channel devices

3.5. Acknowledgements

3.6. Bibliography

Chapter 4: From Thin Si/SiGe Buffers to SSOI

4.1. Introduction

4.2. Nucleation of dislocations

4.3. Strain relaxation and strain transfer mechanisms

4.4. Overgrowth of strained Si and layer optimization

4.5. Characterization of the elastic strain

4.6. SSOI wafer fabrication

4.7. SSOI as channel material for MOSFET devices

4.8. Summary

4.9. Bibliography

Chapter 5: Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration

5.1. Introduction

5.2. Challenges associated with the source/drain extrinsic contacts

5.3. Extraction of low Schottky barriers

5.4. Modulation of Schottky barrier height using low temperature dopant segregation

5.5. State-of-the-art device integration

5.6. Conclusion

5.7. Acknowledgements

5.8. Bibliography

Part 2: Advanced Modeling and Simulation for Nano-MOSFETs and Beyond-CMOS Devices

Chapter 6: Introduction to Part 2

6.1. Modeling and simulation approaches for gate current computation

6.2. Modeling and simulation approaches for drain current computation

6.3. Modeling the end of the roadmap nMOSFET with alternative channel material

6.4. NEGF simulations of nanoscale CMOS in the effective mass approximation

6.5. Compact models for advanced CMOS devices

6.6. Beyond CMOS

6.7. Bibliography

Chapter 7: Modeling and Simulation Approaches for Gate Current Computation

7.1. Introduction

7.2. Calculation of the tunneling probability

7.3. Tunneling in nonconventional devices

7.4. Trap-assisted tunneling

7.5. Models for gate current computation in commercial TCAD

7.6. Comparison between modeling approaches

7.7. Bibliography

Chapter 8: Modeling and Simulation Approaches for Drain Current Computation

8.1. Boltzmann transport equation for MOS transistors

8.2. Method of moments

8.3. Subband macroscopic transport models

8.4. Comparison with device-SMC

8.5. Conclusions

8.6. Bibliography

Chapter 9: Modeling of the End of the Roadmap nMOSFET with Alternative Channel Material

9.1. Introduction: replacing silicon as channel material

9.2. State-of-the-art in the modeling of alternative channel material devices

9.3. Critical analysis of the literature using analytical models

9.4. Conclusions

9.5. Bibliography

Chapter 10: NEGF for 3D Device Simulation of Nanometric Inhomogenities

10.1. Introduction

10.2. Variabilities for nanoscale CMOS

10.3. Full quantum treatment of spatial fluctuations in ultra-scaled devices

10.4. Bibliography

Chapter 11: Compact Models for Advanced CMOS Devices

11.1. Introduction

11.2. Electrostatics modeling issues

11.3. Transport modeling issues

11.4. 1D compact models

11.5. Ultimate MuGFET modeling issues: ballistic current and quantum confinement

11.6. Velocity saturation and channel length modulation modeling

11.7. Hydrodynamic transport model

11.8. Charge and capacitance modeling

11.9. Short-channel effects

11.10. RF and noise modeling

11.11. Acknowledgements

11.12. Bibliography

Chapter 12: Beyond CMOS

12.1. Introduction

12.2. Atomistic modeling of carbon-based FETs

12.3. Numerical simulation of CNT-FETs

12.4. Effective mass modeling of carbon nanotube FETs

12.5. CNT versus graphene nanoribbon FETs

12.6. Full-quantum treatment of elastic and inelastic scattering in Si and SiC GAA nanowire FETs

12.7. Conclusions

12.8. Bibliography

Part 3: Nanocharacterization Methods

Chapter 13: Introduction to Part 3

Chapter 14: Accurate Determination of Transport Parameters in Sub-65 nm MOS Transistors

14.1. Impact of transport on device performance in the drift-diffusion regime

14.2. Standard extraction techniques and their adaptation to short-channel transistors

14.3. Alternative extraction techniques

14.4. Out of equilibrium transport

14.5. Conclusions

14.6. Bibliography

Chapter 15: Characterization of Interface Defects

15.1. Characterization using the capacitance-voltage (C-V) response

15.2. Characterization using the conductance-voltage (G-V) response

15.3. Charge pumping

15.4. Low frequency noise

15.5. Bibliography

Chapter 16: Strain Determination

16.1. Introduction

16.2. Characterization requirements

16.3. Characterization techniques

16.4. Strain description

16.5. Bibliography

Chapter 17: Wide Frequency Band Characterization

17.1. Modified split-CV technique for reliable mobility extraction

17.2. Small-signal electrical characterization of FinFETs: impact of access resistances and capacitances

17.3. Substrate-related output conductance degradation

17.4. Small-signal electrical characterization of Schottky barrier MOSFETs

17.5. Bibliography

List of Authors

Index

First published 2010 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.

Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:

ISTE Ltd27-37 St George’s RoadLondon SW19 4EUUKJohn Wiley & Sons, Inc.111 River StreetHoboken, NJ 07030USAwww.iste.co.ukwww.wiley.com

© ISTE Ltd 2010

The rights of Francis Balestra to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988.

Library of Congress Cataloging-in-Publication Data

Nanoscale CMOS: innovative materials, modeling, and characterization / edited by Francis Balestra.

p. cm.

Includes bibliographical references and index.

ISBN 978-1-84821-180-3

1. Metal oxide semiconductors, Complementary--Materials. I. Balestra, Francis.

TK7871.99.M44I545 2010

621.39'732--dc22

2010012627

British Library Cataloguing-in-Publication Data

A CIP record for this book is available from the British Library

ISBN: 978-1-84821-180-3

Introduction

Microelectronics, based on CMOS (complementary metal oxide semiconductor) technology, is the essential hardware enabler for electronic product and service innovation in key growth markets, such as communications, calculating, consumer electronics, automotive, avionics, automated manufacturing, health and environment. The global semiconductor industry underpins 16% of the world’s total economy and is growing every year. The worldwide market for electronic products is estimated at more than $1,100 billion, and the related electronics services market at more than $6,500 billion. These product and service markets are enabled by a $280 billion market for semiconductor components and an associated $80 billion market for semiconductor equipment and materials. The new era of nanoelectronics, which started at the beginning of the current millennium with the smallest patterns in state-of-the-art silicon-based devices below 100 nanometers, is enabling an exponential increase in system complexity and functionality.

Nanoelectronics enables the development of smart electronic systems by switching, storing, receiving and transmitting information. In respect to its societal relevance, the ubiquitous nanoelectronics is also closely linked to the notion of ambient intelligence, which is a vision of the future where people are surrounded by intelligent intuitive interfaces that are embedded in all kinds of objects and an environment that is capable of recognizing and responding to the presence of different individuals in a seamless way.

Since the invention of the transistor in 1947 at Bell Labs, followed by the first silicon transistor in 1954 and the concept of integrated circuits in 1958 in Texas Instruments, progress in the field of microelectronics has been tremendous, which has revolutionized the society. In these last 50 years, dramatic advances have been achieved in the packing density of transistors, resulting since the 1970s in a density of transistors on an integrated chip (IC) will doubles every two years (Moore’s law). At the beginning of the 1970s, the first microprocessor had only about 2,000 transistors (10 µm gate length), the world’s first two-billion transistor processor was reported in 2008 in 65 nm CMOS technology. The technology node will drop down to 9 nm in 2024. Meanwhile, development goes on apace with the 32 nm node coming on stream in late 2009. Today, the annual fabrication of MOSFET (metal oxide semiconductor field effect transistor) per person is about one billion.

The same trend is observed for memories. The DRAM (dynamic random access memory) capacity has been raised from 1 kb in 1970 to more than 2 Gb at present. Three billion transistor SRAM test chips have also been recently announced. For nonvolatile memories, a recent record of 64 Gb has been demonstrated. This increase in transistor count and memory capacity has led to increased processing power, measured now in thousands of MIPS (millions of instructions per second).

A dramatic increase in the transistor performance, measured as the ON to OFF ratio of drain current in DC mode, while lowering the supply voltage, has been obtained during recent decades. In AC mode, cut-off frequencies of several hundred GHz have been recently measured in bulk and SOI (silicon-on-insulator) CMOS technologies.

Moore’s law also means decreasing cost per function, the transistor price has dropped at an average rate of about 1.5 per year (about 108 since the beginning of the semiconductor industry).

However, according to the International Technology Roadmap for Semiconductors [ITR 09] and ENIAC Strategic Research Agenda [SRA 07], there are big challenges to overcome in order to continue progress in the same direction. Si will remain the main semiconductor material for the foreseeable future, but the required performance improvements for the end of the roadmap for high performance, low and ultra-low power applications as well as memories will lead to a substantial enlargement of the number of new materials, technologies and device architectures.

SOI substrates are interesting candidates for the manufacturing of mainstream semiconductor products such as microprocessors, low-power devices or memories [CRI 09]. The classic CMOS architecture is approaching its scaling limits, “end-of-roadmap” alternative devices are also being investigated. Amongst the different types of SOI-based devices proposed, one clearly stands out for the end of the roadmap: the multigate field-effect transistor (multigate- or double-gate- or gate-all-around- or Fin-FET), enabling better electrostatic control of the channel(s), hence a more aggressive scalability and reduced leakage currents, higher driving currents and speed, reduced variability and enriched functionality. The International Technology Roadmap for Semiconductors recognizes the importance of these devices.

In the sub-10 nm range, “beyond-CMOS” devices, based on nanowires, nanodots, carbon electronics or other nanodevices, could play an important role and could be integrated on CMOS platforms in order to pursue integration down to nanometer structures.

Therefore, new generations of nanoelectronic ICs present increasingly formidable multidisciplinary challenges at the most fundamental level (novel materials, new physical phenomena, ultimate technological processes, etc.). This long-term research is fundamental to prepare the path for future nanoelectronic technologies, as a 15 to 20 year time frame is usually necessary between the first validation of a new innovative idea and its full demonstration and acceptance into complex systems.

The three parts of this book have been written by scientists, from universities and research centers, strongly involved in teaching and research programs related to nanoelectronic devices; because of their expertise and international commitment, they are very well informed on the state-of-the-art of the physics and technologies and the evolution of nanoelectronic materials and components.

This book offers a comprehensive review of the state-of-the-art in innovative materials, advanced modeling and novel characterization methods for nanoscale CMOS dedicated to researchers, engineers and students. In the field of new materials, which has been a major drive to find new ways to enhance the performance of semiconductor technologies, this text covers three areas that will provide a dramatic impact on the approaches to future CMOS - global and local strained and alternative materials for high-speed channels on bulk substrate and insulator, very low access resistance and various high dielectric constant gate stacks for power scaling. It also focuses on the most reliable modeling and simulation methods of the electrical properties of ultimate MOSFETs, including ballistic transport, gate leakage, atomistic simulation and compact models for single- and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise and Raman spectroscopy.

Part 1 reviews some of the progress being made in the key areas of new materials for nanoscale transistors that could be incorporated in future technology nodes. Chapter 2 focuses on general issues of high-k dielectrics and metal gates, and points out a range of different materials that will be able to circumvent fundamental limitations in various applications. Chapter 3 reviews the current state-of-the-art for strained silicon and then discuss the route to higher strain and Ge channels, based on global strain tuning buffers. Interesting approaches for the realization of thin virtual substrates and strained silicon on oxide (SSOI) wafers and devices are described in Chapter 4. The conversion of the biaxial strain to uniaxial strain in order to develop nanowire FETs is also shown. The objective of Chapter 5 was to introduce recent developments in the field of Schottky barrier engineering and integration in nonconventional MOSFET architectures. Low temperature dopant segregation at the silicide-semiconductor interface is also analysed as a useful methodology to lower the barrier height. Practical implementation scenarios are described for p- and n-type devices and both static and high frequency performances of Schottky-barrier MOSFETs are also presented.

Part 2 outlines some of the progress being made in the key areas of simulation of nanoscale transistors including the simulation of drain and gate leakage currents, the role of alternative channel materials, the application of a full-quantum transport approach in the simulation of ultimate silicon nanodevices, the progress in the field of compact models for nano-CMOS and the advanced simulation approaches for beyond-CMOS devices. Chapter 7 illustrates how to calculate gate current in non conventional devices such as double gate SOI MOSFETs and addresses the problem of analyzing tunneling in 2D and 3D devices. An overview about trap-assisted tunneling is given. Finally, a comparison between different approaches for gate current computation applied to a template gate stack featuring high-k dielectric is reported. In Chapter 8, the general semi-classic modeling framework for drain current computation is introduced together with the methodology for the derivation of the moments of the Boltzmann transport equation. A systematic comparison of drain current simulations for long channel as well as nano scale MOSFETs obtained either with the Monte Carlo method or with the moment-based models is also addressed. In Chapter 9, the results of the theoretical evaluation of the performance of ultra-scaled nMOSFET with alternative channel material are presented. Both results from efficient and accurate semi-analytical models and by using state-of-the-art simulation tools are investigated. The simplicity of analytical models enable a better understanding of the relative importance of the various mechanisms which contribute to the overall device performance. Chapter 10 deals with the investigation of interface roughness and random discrete dopants, and related variability in nanoscale MOSFETs, which requires fully 3D quantum transport simulations. Then, we review and present several recent developments in compact modeling of nanoscale MOSFETs, in particular multigate devices. Electrostatic and transport modeling issues as well as the development of unified charge control models for different types of multigate MOSFETs are considered. Specific compact modeling issues for ultimate MOSFETs, including velocity saturation, channel length modulation, ballistic transport and quantum confinement, are also discussed. In Chapters 11 and 12, two different types of beyond-CMOS devices, based on carbon nanotubes or graphene and gate-all-around transistors based on silicon or 3C silicon carbide nanowires, are analyzed using 3D device simulator able to solve the full band Schrödinger equation with open boundary conditions in the nonequilibrium Green’s function (NEGF) framework coupled with the 3D Poisson equation.

In Part 3, the main nanocharacterization techniques for nanoscale devices are investigated. Chapter 14 shows the need to develop a reliable extraction method for transport parameters, which is playing a key role in device performance, and to correlate these electrical properties to materials and processing options. The aim of this chapter is to give an overview of how standard extraction methods have been progressively adapted to account for MOS transistors evolution, what their limits are, and which alternative methods may be used for highly scaled structures. In Chapter 15, we consider accurate methods for characterizing the density and energy distribution of interface states and trap density in the semiconductor/oxide system using measurements of capacitance or conductance of MOS structures, as well as charge pumping and low frequency noise. Chapter 16 shows the methods leading to a reliable evaluation of the channel strain for future nanoscale CMOS. In Chapter 17, we point out the importance of an accurate wideband characterization technique, well adapted to advanced MOS devices, in order to understand their static and dynamic behaviors, and thus to monitor and optimize the fabrication process steps for further reducing the impact of parasitic elements.

Francis BALESTRA

Acknowledgements

We would like to acknowledge David Leadley for coordinating Part 1, Enrico Sangiorgi for coordinating Part 2, and Denis Flandre for coordinating Part 3 of the book. All the Members of the Sinano Institute and the Partners of the Nanosil and Sinano Networks of Excellence are also gratefully acknowledged for their support.

Bibliography

[CRI 09] CRISTOLOVEANU S. and BALESTRA F., “Introduction to SOI technology and transistors”, in J. GAUTIER (Ed.), Physics and Operation of Silicon Devices and Integrated Circuits, ISTE-Wiley, London, UK, New York, USA, 2009.

[ENI 07] http://www.eniac.eu/web/downloads/SRA2007.pdf

[ITR 09] http://www.itrs.net/Links/2009ITRS/Home2009.htm

Part 1

Novel Materials for Nanoscale CMOS