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- Herausgeber: John Wiley & Sons
- Kategorie: Wissenschaft und neue Technologien
- Sprache: Englisch
Understand the future of computing with this accessible, wide-ranging introduction to a promising field
Miniaturization and the emergence of nanotechnology have together constituted the most revolutionary development in recent decades of computing research and innovation. Nanomagnetic computing and logic have allowed engineers and programmers to move beyond the Complementary Metal-Oxide-Semiconductor (CMOS) and their associated methods into a new world of cutting-edge computing technology.
Nanoscale Computing offers the first-ever single-authored textbook on this vital subject, introducing the fundamentals of nanoscale computing, their suitability to the traditional limitations of CMOS computing, and their growing number of applications. The result is a key text for students, professionals, and researchers alike.
Nanoscale Computing readers will also find:
- An emphasis on practical applications, both current and future
- Detailed discussion of topics including nanomagnetic logic, edge computing, and more
- End of chapter quizzes and additional tutorials to facilitate learning
Nanoscale Computing is ideal for researchers and technology experts, as well as graduate and undergraduate students working in computer science, nanotechnology, magnetics, electronics, semiconductors, electron devices, circuits/systems, and multi-interdisciplinary related fields.
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Veröffentlichungsjahr: 2024
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Table of Contents
Cover
Table of Contents
Title Page
Copyright
Dedication
About the Author
Preface
Acknowledgements
Acronyms
Introduction
About the Companion Website
1 Introduction to Nanoscale Computing
1.1 Overview of Nanoscale Computing
1.2 Evolution Beyond CMOS
1.3 Edge AI Devices: A Driving Force
1.4 Architecture and Material Design
1.5 Scope of the Book
1.6 Conclusion
References
2 Limitations of CMOS Technology
2.1 Challenges in Traditional CMOS Technology
2.2 Implications for Computing Systems
2.3 Technological and Economic Challenges
2.4 Bridging to Nanoscale Computing
2.5 Educational Emphasis
References
3 Fundamentals of Nanomagnetic Logic
3.1 Introduction to Nanomagnetic Logic
3.2 Fundamentals of Coupling Mechanisms in Nanomagnetic Logic
3.3 Design and Operation of Nanomagnetic Logic Gates
3.4 Signal Processing in Nanomagnetic Logic
3.5 Energy Considerations and Efficiency
3.6 Educational Emphasis
References
4 Nanomagnetic Logic Architectures
4.1 Overview of Nanomagnetic Logic Architectures
4.2 Major Nanomagnetic Logic Architectures
4.3 Fundamentals of NML Architecture
4.4 Parallel and Pipelined Architectures
4.5 Reconfigurable Nanomagnetic Architectures
4.6 Conclusion
References
5 Material Design for Nanoscale Computing
5.1 Importance of Material Selection in Nanoscale Computing
5.2 Magnetic Materials for Nanomagnetic Logic
5.3 Nonmagnetic Materials in Nanoscale Computing
5.4 Multiferroic and Spintronic Materials
References
6 Nanoscale Computing at the Edge: AI Devices and Applications
6.1 Introduction to Edge Computing
6.2 Intersection of Nanoscale Computing and Edge AI
6.3 Applications of Edge AI in Nanoscale Computing
6.4 Edge AI in Robotics and Autonomous Systems
6.5 Conclusion
References
7 Hybrid Computing Systems and Emerging Applications
7.1 Introduction to Hybrid Computing
7.2 Nanomagnetic-CMOS Hybrid Architectures
7.3 Neuromorphic Hybrid Systems
7.4 Educational Emphasis
References
8 Challenges, Conclusions, Road-Map, and Future Perspectives
8.1 Challenges in Nanoscale Computing
8.2 Environmental Impact
8.3 Integration with Other Technologies
8.4 Nanoscale Computing Technologies Roadmap
8.5 Conclusions and Key Findings
8.6 Research Opportunities and Directions
References
Index
End User License Agreement
List of Tables
Chapter 1
Table 1.1 Key Evolution in the History of Semiconductors
Chapter 3
Table 3.1 Key Evolution in the History of NML
Chapter 4
Table 4.1 Nanomagnetic Logic Review
List of Illustrations
Chapter 1
Figure 1.1 IEEE rebooting computingFile:IEEE Rebooting Computing TaskForce L...
Figure 1.2 IRDS perspective on Beyond CMOS – next-generation computing parad...
Figure 1.3 Intersection of quantum and nanoscale technologies File:Technolog...
Figure 1.4 Understanding the size of nano-scale definition [from glucose mol...
Figure 1.5 Biological and technological scales compared File:Biological and ...
Figure 1.6 (a, b) Real-time analogy to compare and understand the world of a...
Figure 1.7 Real-time analogy to compare and understand the evolution of NC F...
Figure 1.8 (a,b) 75 Years of transistors and the 100 year of spin – dual his...
Figure 1.9 75 Years of transistors and the 100 year of spin – dual historica...
Figure 1.10 (a,b) 100 Years of spin — historical perspective — hand in hand ...
Figure 1.11 Information processing paradigm–conceptual illustration using na...
Figure 1.12 The infographic summarizes the results of a literature review, s...
Figure 1.13 Nano IoT.
Figure 1.14 Interconnected themes and concepts of this book - ISBN – 9781394...
Chapter 2
Figure 2.1 Semi-log graph of 125 years of Moore’s Law.File: 51391518506_7453...
Figure 2.2 Source tied to the body to ensure no body bias. (a) Subthreshold,...
Figure 2.3 MOS capacitor on p-type silicon showing inversion and depletion l...
Figure 2.4 As channel length decreases, the barrier to be surmounted by an...
Figure 2.5 Cross section of a metal-oxide-semiconductor field-effect transis...
Figure 2.6 Moore’s Law – Computer History Museum.File: Moore’s Law – Compute...
Figure 2.7 Semi-log graph of 125 years of Moore’s Law.File: 51391518506_7453...
Figure 2.8 Quantum confinement is responsible for the increase of energy dif...
Figure 2.9 A generic potential energy well. In quantum physics, potential en...
Figure 2.10 NAND gate with four inputs in transistor–transistor logic; seven...
Figure 2.11 Thermal conductivity of thermal interface materials and thermal ...
Figure 2.12 Heat sink with thermal resistances used to calculate thermal per...
Figure 2.13 An ideal voltage inverting amplifier with an impedance connectin...
Figure 2.14 A laptop PC clock generator, based on the Silego chip. File: Sil...
Chapter 3
Figure 3.1 Molecular power 39. Effect of magnetic field on diamagnets and pa...
Figure 3.2 Spins precess around B̲effective, and if B̲effective meets the ad...
Figure 3.3 A chain of magnetic dots 110 nm in diameter. Information is passe...
Figure 3.4 Schematic visualization of how microscopic dipoles assemble to fo...
Figure 3.5 Visualization of the Dzyloshinskii Moriya antisymmetric exchange....
Figure 3.6 (a) Energy landscape of a single nanomagnet with increasing amo...
Figure 3.7 Spins precess around B̲effective, and if B̲effective meets the ad...
Figure 3.8 Magnetic fields and created by a bar magnet. Top: the magneti...
Figure 3.9 Curves for Curie temperature (solid) and saturation magnetization...
Figure 3.10 Comparison of the magnetic -field and -field inside and outsid...
Figure 3.11 The four building blocks for electrically embedded ferromagnetic...
Figure 3.12 Adiabatic switching of the nanomagnet line. Part (a) illustrates...
Figure 3.13 The energy of a nanomagnet as a function of the angle between ma...
Figure 3.14 Comsol simulation of clock wires. (a) Clock wires model, upper v...
Chapter 4
Figure 4.1 This plot shows the resistance as a function of the angle of an a...
Figure 4.2 Magnetic Moment File: Momento Magnetico 02.svg https://commons.wi...
Figure 4.3 A spin valve in the high resistance state. File: High-resistance....
Figure 4.4 Diagram showing the possible spin angular momentum values for 1/2...
Figure 4.5 A simplified MRAM cell structure. File: MRAM-Cell-Simplified.svg ...
Figure 4.6 Schematic diagram of the high- and low-resistance states in a spi...
Figure 4.7 Splitting of density of electron states in ferromagnetic and nonm...
Figure 4.8 Schematic of the inverse spin Hall effect in graphene. File: Inve...
Figure 4.9 The top figure (a) represents a Stern Gerlach type experiment, as...
Figure 4.10 Current-in-plane (CIP) and current-perpendicular-to-plane (CPP) ...
Figure 4.11 Giant magnetoresistance. File: GMR layers.svg https://commons.wi...
Figure 4.12 Micromagnetic simulation showing the functionality of a combinat...
Figure 4.13 Spin-wavefunction. File: Spin-wavefunction.svg https://commons.w...
Figure 4.14 A simplified explanation of spin-transfer torque using the Stone...
Figure 4.15 Schematic view of a magnetic tunnel junction. File: Magnetic Tun...
Figure 4.16
Fermi interaction of NMR:
Arrows represents nuclear spin (), an...
Figure 4.17 Angular dependence of the AMR. File: AMR-angular.svg https://com...
Figure 4.18 Usage of spin valve in magnetic random access memory (MRAM). 1. ...
Figure 4.19 A spinning proton producing a magnetic field which is comparable...
Figure 4.20 Spin orientation in the direction of material magnetization. Fil...
Chapter 5
Figure 5.1 A cobalt nanoparticle coated with layers of graphene. File: Cobal...
Figure 5.2 The image illustrates the entanglement of two qubits prepared in ...
Figure 5.3 Spintronic sandwich with two possible states – parallel and antip...
Figure 5.4 Schematic of spin transfer torque in metallic junctions. File: ST...
Figure 5.5 Schematic picture of the four possible domain states of a ferroel...
Figure 5.6 (a) The Hall-voltage hysteresis loops of the as-grown sample and ...
Figure 5.7 Continuous flow through magnetic-assisted reaction. File: Magneti...
Figure 5.8 In the pole model of a dipole, an
H
field (to the right) causes e...
Figure 5.9 Sketch of the tunnel current for tunnel magnetoresistance (TMR) F...
Figure 5.10 In 1909, Einstein proposed a thought experiment to demonstrate w...
Figure 5.11 Spins of electrons in a Bell’s theorem experiment File: Bell’s T...
Figure 5.12 Illustration of the right-hand rule a process for determining th...
Figure 5.13 Measurement-based techniques involve entangling a cluster of Qub...
Figure 5.14 Bar chart showing number of papers using the keyword terms magne...
Chapter 6
Figure 6.1 Taxonomy of edge computing applications. File:Figure 7 https://do...
Figure 6.2 Evolution of edge computing File:Figure 1 https://doi.org/10.1016...
Figure 6.3 Throughput and energy efficiency with input size changes. File:Fi...
Figure 6.4 Detail of the synapses File:Figure 12 https://doi.org/10.1016/j.m...
Figure 6.5 The diagram shows the detailed architecture for cloud and edge-ba...
Figure 6.6 Critical performance metrics of Fog continuum in Industry 5.0 app...
Figure 6.7 The three pillars of the AIDA architecture File:Figure 1 https://...
Figure 6.8 Internet of Things File:Graphical Abstract https://doi.org/10.101...
Figure 6.9 An overview of the main conceptual categories identified and thei...
Figure 6.10 The five pillars of an AI/AIoT-driven system: 1-sensing in charg...
Figure 6.11 A brief taxonomy of AI methods for Fog systems that extend the o...
Figure 6.12 The model of computation offloading at edge network. File:Figure...
Figure 6.13 This iconographic presents DARQ Technologies with the name and i...
Chapter 7
Figure 7.1 Magnetic permeability (not to scale): —flux density, —magnetic ...
Figure 7.2 Permeability study. Hybrid systems benefit from materials with hi...
Figure 7.3 Schematics of the discretization of a TIPNJ with a nanomagnet as ...
Figure 7.4 (a–f) The figure shows SEM and schematic images of a 1D Ising-lik...
Figure 7.5 Future projections and prediction intervals (95% prediction confi...
Figure 7.6 Schematics of coupled nanomagnet elements illustrating the princi...
Figure 7.7 (a–d) c-AFM images and corresponding logic circuit diagrams of tw...
Figure 7.8 A magnetic inductor transforms to an electric capacitor when the ...
Figure 7.9 Potential energy profile (energy as a function of magnetization o...
Figure 7.10 Schematic and magnetic hysteresis loops of nanomagnet elements i...
Figure 7.11 Structure of a NAND gate with a PZT film on a conducting n-Si s...
Figure 7.12 A magneto-elastic system for generating two random bits with con...
Figure 7.13 (a) Schematics of the bare and EAR Co/Pt layers. (b–d) Measured ...
Figure 7.14 Top view of different configurations of nanomagnet on a TIPNJ. (...
Chapter 8
Figure 8.1 Neuro-optimization with embedded analog-grade eFlash memories. Pa...
Figure 8.2 Technical challenges of nanoscale computing.
Figure 8.3 Diverse spin phenomena can act as energy interconversion rectifie...
Figure 8.4 Ethical challenges of nanocomputing.
Figure 8.5 Schematic diagram of three reservoir architectures: signal sub-sa...
Figure 8.6 Illustrations of reservoir computing and frustrated perpendicular...
Figure 8.7 Photograph of the devices fabricated as an array on a flexible s...
Figure 8.8 (a) Comparison between the fundamental element of a Seebeck effec...
Figure 8.9 The pinning energy profile, , for a transverse domain wall betwe...
Figure 8.10 (a) 3D illustration of the Bennett clocking system simulated in ...
Figure 8.11 (a) NMRC system diagram shows signals and energizing nanoma...
Figure 8.12 (a) Skyrmion (b) MTJ structure (variants of the readout schemes ...
Figure 8.13 (a) The MTJ temperature sensor structure involves a three-termin...
Figure 8.14 Schematic of a whisker flow sensor developed using thin-sheet ma...
Figure 8.15 Strain impacts magnetic anisotropy in FeRh/MgO bilayers. Minorit...
Figure 8.16 SD, spin diffusion; STT, spin-transfer torque; SHE, spin Hall ef...
Figure 8.17 Design and operation of skyrmion transistor driven by spin curre...
Figure 8.18 The diagram shows input data scaling to an applied magnetic fiel...
Figure 8.19 Morphology, PFM phase, and c-AFM images of vertex domains in BiF...
Figure 8.20 The schematic details the RQFP gate composed of AQFP gates, illu...
Figure 8.21 Speculative law of NML – quantum magnetic synergy.
Figure 8.22 Speculative laws of NML – entanglement fidelity and security res...
Figure 8.23 Energy consumption decrease projection.
Figure 8.24 Evolution of CMOS verus NML beyond CMOS with milestones. Mathema...
Figure 8.25 NML Growth Law (cf. Eq. 8.5).
Guide
Cover
Table of Contents
Title Page
Copyright
Dedication
About the Author
Preface
Acknowledgements
Acronyms
Introduction
About the Companion Website
Begin Reading
Index
End User License Agreement
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Nanoscale Computing
The Journey Beyond CMOS with Nanomagnetic Logic
Dr. Santhosh Sivasubramani
Indian Institute of Technology Hyderabad
Hyderabad, India
Copyright © 2025 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
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Library of Congress Cataloging-in-Publication Data:
Names: Sivasubramani, Santhosh, author.
Title: Nanoscale computing : the journey beyond CMOS with nanomagnetic logic / Santhosh Sivasubramani.
Description: Hoboken, New Jersey : Wiley, [2025] | Includes index.
Identifiers: LCCN 2024043576 (print) | LCCN 2024043577 (ebook) | ISBN 9781394263554 (hardback) | ISBN 9781394263578 (adobe pdf) | ISBN 9781394263561 (epub)
Subjects: LCSH: Nanotechnology. | Semiconductors.
Classification: LCC T174.7 .S5455 2025 (print) | LCC T174.7 (ebook) | DDC 620/.5–dc23/eng/20241118
LC record available at https://lccn.loc.gov/2024043576
LC ebook record available at https://lccn.loc.gov/2024043577
Cover Design: WileyCover Image: © Ali Kahfi/Getty Images
Dedicated to my
Grand Mother Paapa R
Grand Father Rajendran M
Mother Lakshmi R
Family &Professor Amit Acharyya
About the Author
Dr Santhosh Sivasubramani received his master’s and doctoral degrees from Indian Institute of Technology (IIT) Hyderabad, India. His PhD thesis work is on “Rebooting Computing: Nanomagnetic Logic based Computing Architecture Design Methodology” funded by Redpine Signals Inc., PhD Fellowship in the Department of Electrical Engineering. His MTech thesis work is on “Simulation and Experimental Investigation on Electronic Transport and Magnetic Properties of Graphene for its Applications in Nanomagnetic Computing.” His bachelor’s thesis work is on “Design Scheme of Maintaining Power System and Protecting Nuclear Reactor by Intelligent Robot Employed with Fuzzy Logic.”
Dr Santhosh also possess experience as an INUP Visiting Scholar at the Centre of Excellence in NanoElectronics, IIT Bombay, and as a Project Assistant – DEITY project on “IOT for Smarter Healthcare” Center for Cyber Physical Systems & IoT, Department of Electrical Engineering, IIT Hyderabad. He is also the Founder of RSL Quantum. Santhosh also have gained post-PhD/industrial experience as the Institute Post-Doctoral Research Fellow/Research Associate in the Advanced Embedded Systems and IC Design Laboratory, Department of EE, IIT Hyderabad, and as Research Scientist in the Nanomagnetics Research Lab, Redpine Signals India Pvt Ltd where he was involved in the generation of the IP portfolio (25 INTL. Patents Filed/4 US Patent Granted/2 US Pre-Grant Publication/3 IN Patents Granted/6 IN Pre-Grant Publication). He is also a freelance science journalist who reports for India Science Wire a DST initiative. Santhosh also served as the General Chair of IEEE Summer School on Nano 2022, 2023, 2024. Santhosh is also the key member/organizer/convener of the 1st/2nd/3rd/4th IEEE Hyderabad Nano Day, IEEE NTC World Nanotechnology Marathon 2021, IEEE NTC R10 YP DL/Webinar Series, IEEE NTC YP R10 Panel Discussion, IEEE NTC HSC Euro-Neuro/QuNa show (2021–2025), and volunteered for DST/AICTE – TEQIP, GIAN, SPARC, FDP, Sci-Tech Councils and on the academic/research – governing board of institutions/NGO organizations across India. SS is the Chair – IEC/IEEE 62659™ Standard for Nanomanufacturing – Large Scale Manufacturing for Nanoelectronics. SS is also the Rebooting Computing Architect.
Santhosh is also the Senior Member of IEEE and currently serve in various administrative voluntary roles:
Secretary – IEEE Standards Association – Nanotechnology Council (2021–Present);
Pro-Com/Advisory Com/Technical Com-Member 2021/22/23/24 AtC-AtG IEEE Magnetics Conference;
Advisory Committee – DST Star – National level Faculty Development Programme on Nano;
IEEE NTC YP Region 10 (Asia-Pacific) Representative (January 2021–Present);
Founding Chair – IEEE NTC Hyderabad Section Chapter (2021–Present);
Elected Secretary – IITH Alumni Association Governing Body (2021–2023);
IEEE NTC Technical Committee – TC12 Nanomagnetics/TC1 Nanorobotics and Nanomanufacturing;
Ad-Com Member IEEE Nanotechnology Council;
IEEE Communications Society Data Storage Technical Committee Member (2020–Present);
IEEE Computer Society Task Force on Rebooting Computing Member (2018–Present);
IEEE NTC Young Professionals India Representative (2020);
Reviewer for various IEEE, IOP, APS, RS, Elsevier Journals, Magazines and Transactions;
Awardee – IEEE MGA Young Professionals Achievement Award 2023;
IEEE STEM Champion Awardee 2024–2025; IEEE Transmitter Impact Creator-PV Initiative – 2023–2025;
IEEE STEM Inspire Grant Awardee – TryNano – Pre Univ School Girls Program – NanoQuest 2024;
IEEE SMC EDI Systems Engineering Education Initiative Grant Awardee 2024–2025.
Awards/Academic Recognitions: (a) Awarded with the Certificate of Appreciation for Research in Electrical Engineering, IIT Hyderabad. (b) Article “10.1109/TNANO.2018.2874206” has been featured in the top 10 list of articles, in the IEEE TNANO. (c) Selected for and participated in a fully sponsored on-site research visit to IMEC Belgium. (d) Nominee – INAE innovative student projects award (MTech Thesis). (e) Elected as Doctoral Council Representative, Student Gymkhana, IIT Hyderabad. (f) Recipient of Silver Medal from the Educational Minister, Government of Tamil Nadu for securing lead score in SSLC in the Educational District. (g) Article “10.1088/1361-6528/ab295a” has been featured in the INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2020/2021/2022/2023 EDITION BEYOND CMOS (IRDS™: Beyond CMOS) international focus group report. (h) Article “10.1038/s41598-020-63360-6” has been featured in the Top 100 in Materials Science 2020 by Nature Publishing Group SN Insights. (i) Participated and won first place in the South Indian Robo Championship League. (j) Selected for participation in DAE, IGCAR sponsored Nuclear Awareness Festival. (k) Associate Editor – IEEE International Conference on Nano 2022. (l) Track Chair 4 & 10 – IEEE INDICON 2023. (m) Session Chair – IEEE APCCAS. (n) IEEE NANO SDC 2024/2025 – Organizer – NANO Int Conf.
Preface
The continuous advancement of technology is driven by the need to process information more efficiently. The traditional transistor-based computing; Complementary metal-oxide-semiconductor (CMOS), powering the digital revolution, encounters a fundamental challenge at the atomic scale. As transistors shrink beyond nanometers, challenges such as leakage currents, heat dissipation, and miniaturization limitations alarm computing power growth. Nanoscale Computing: The Journey Beyond CMOS with Nanomagnetic Logic envisions the future of information processing under the umbrella of “Rebooting Computing.” This book is a fundamental textbook and an active guide, inviting readers to explore the historical perspective of 75 years of Transistor and 100 years of Spin. It leads to a domain where electrons step back, and spin becomes the key of logic. For students, whether undergraduate or graduate, this book helps them understand nanoscale computing from multiple view points. It explains basic ideas and shows where current technology has some problems, which might lead to new and creative solutions. Readers learn about nanomagnetic logic (NML), where tiny magnets are used for computing, which could make devices more powerful and efficient. For tech experts and researchers, the book serves as a conversation partner and fellow explorer. Together, they explore novel architectures beyond CMOS limitations, unveiling material design fundamentals crucial for next-generation logic. The exploration extends to edge AI, where nanomagnetic logic promises efficient interactions with the world. For the first of its kind, this book demonstrates transformative power of interdisciplinary collaboration, bridging theoretical concepts with practical applications. It showcases how nanoscale computing and nanomagnetic logic intersect with AI, presenting case studies in various fields, from medical diagnostics to environmental sensing. Acknowledging challenges, the book discusses hurdles like reliability, scalability, and integration with existing technologies. This discussion paves the way for future research and innovation, speculative laws on NML, ensuring the journey beyond CMOS extends beyond the book’s final page. The author highlights,“Performing AI computing on the edge with approximate nanomagnetic logic deployed on the magnetic ICs is an envisaged vision towards energy efficient sustainable futuristic computation. It aim towards UNSDGs-carbon net zero, directly impacting climate change mitigation strategies also lead by the IEEE as a forerunner.” This fundamental textbook is an invitation to be part of a Rebooting Computing revolution. It calls students to shape the future, encourages researchers to push boundaries, and challenges tech experts to turn imagination into reality. Turn the page, and let the journey into the future of computing begin. This book has been carefully crafted to meet the current demands of individuals interested in learning about technology and implementing it in their lives. Its contents have been meticulously developed over a period of five years, with special emphasis on new educational models aligned with UN SDG goals. For the first time, a fundamental textbook has been introduced with this approach, which will keep undergraduate students and readers engaged and thoughtfully provoked. This represents an experiment! With excitement and anticipation.
Hyderabad, 2024
Santhosh Sivasubramani
Acknowledgements
This book has undergone several stages, including ideation, process development, content curation, proofreading, flow/coherence checks, figure population, and fact-checking. It’s important to note that this was not a simple task, and this fundamental textbook has been carefully crafted to serve its purpose for undergraduates, graduates, and advanced readers alike. This five-year effort would not have been possible without the support of many individuals who have contributed directly and indirectly. This space is dedicated to acknowledging all of them and also to people who motivated me and supported throughout. My special thanks to Mr. Chandrasekaran Lakshmanan, former Head at VHN, India, Mr. Nagarajan, and Mr. Selvan Arputhraj for motivating me to enter the wonder-world of research. I convey my warm regards to Dr. S. Thabasu Kannan, former Director of PCET, India, Mr. Krishnamoorthy, Mr. Bakrutheen, Mr. JayaMurugan, and Mrs. Arul mozhi, who guided me. I thank Mrs. Jayalakshmi, who deserves a special appreciation. I am indebted to my PhD advisors Professors Amit Acharyya and Swati Ghosh Acharyya for their continuous support. Mere words cannot express my gratitude to Dr.Amit who mentored me and shaped me as an independent meticulous researcher/educationist and also had an impact on me in my personal life. This is my pleasure to acknowledge Mrs. Sanghamitra Debroy who helped me in all aspects of experimental research. Special thanks to Dr. Chandrajit Pal. I also acknowledge INUP, Centre of Excellence in Nanoelectronics at the IIT, Bombay, Dr. Nageshwari, and Ms. Gayathri Vaidhya. I acknowledge the support from IEEE Nanotechnology Council (NTC), IEEE NTC TC-12 Nanomagnetics, IEEE NTC Standards, IEEE NTC YP, IEEE P62659, IEEE EDS/YP, IEEE Standards, IEEE Young Professionals, IEEE Education Society, IEEE Magnetics Society, IEEE AtC-AtG, IEEE Communications Society Data Storage TC, IEEE Computer Society – Task Force on Rebooting Computing, IEEE MGA, IEEE Hyderabad Section, IEEE India Council, IEEE Region 10, and IIT Hyderabad Alumni Association. I extend my sincerest thanks to Ms Redpine Signals Inc., for the support. Special mention to Dr. Venkat Mattela CEO Ceremorphic Inc., I thank Mr. N Venkatesh, Silicon Labs, for his support. I thank and acknowledge the support and guidance from Professor and Chair of Department of ECE, UC Davis, Dr. M. Saif Islam. My special thanks to Dr. Vanlin Sathya and Dr. A.R. Aravinth Kumar. Special mention to Mr. Arun Ramamoorthy, Dr. Karthick Thangavelu. Special acknowledgment to my colleagues in AESICD Laboratory. Special mention to Mr. Rangesh, and Mr. N. Syed Ghouse. Special thanks to Mrs. Malini Raguraman, and Mr. Yedu Kondalu. I extend my sincerest thanks to Dr. Sparsh Mittal, Dr. Sushmee Badhulika, and Dr Rishad Shafik. Special thanks and appreciation to Mr. Kishore C. and Ms. Suma M. for their continuous support. I acknowledge my students and interns who have collectively contributed a lot. Finally, I offer my warmest thanks to my mom Lakshmi R., without whose support and inspiration it would not have been possible for me to devote five years of time, alongside my other primary commitments, to bring this book out. My wholehearted thanks to my family members – Mr. Rajendran M., Mrs. Paapa R., Mrs. Mariyammal R., Mr. Murugananthan A.G, Pavithra, Gayathri, Mr. Singaravel R., Mrs. Ponna S., Shwetha, Pradeep, Mr. Prabhakaran R., Mrs. Jothimani P., Sabarivasan, Karthik, Mrs. Meena K., Mr. Kumaresan B., Poornima, Harshini, Mrs. Priya R., Mr. Ramesh E., Sushil, and Dharoon.
Dr. Santhosh Sivasubramani
Acronyms
AD
Architectural Design
AFM
Atomic Force Microscopy
AI
Artificical Intelligence
ASIC
Application-Specific Integrated Chip
BC
Beyond CMOS
CMOS
Complementary Metal-Oxide Semiconductor
CNT
Carbon Nano Tube
CPU
Central Processing Unit
DIBL
Drain-Induced Barrier Lowering
DVFS
Dynamic Voltage and Frequency Scaling
DW
Domain Wall
GPU
Graphics Processing Unit
IEC
Interlayer Exchange Coupling
IIOT
Industrial Internet of Things
IOT
Internet of Things
IRDS
The International Roadmap for Devices and Systems
LLG
Landau–Lifshitz–Gilbert
MD
Material Design
MLG
Majority Logic Gate
MRAM
Magnetic Random Access Memory
MTJ
Magnetic Tunnel Junction
NC
Nanoscale Computing
NML
Nanomagnetic Logic
NVM
Nonvolatile Memory
PCM
Phase-Change Memory
PCP
Performance Comparison Parameters
QC
Quantum Computing
QD
Quantum Dot
RC
Rebooting Computing
SCE
Short-Channel Effect
SOT
Spin–Orbit Torque
STM
Scanning Tunnelling Microscopy
STT
Spin-Transfer Torque
SW
Spin Wave
TMR
Tunneling Magnetoresistance
Introduction
This book is being written with the purpose of addressing a diverse audience, including graduate and undergraduate students, as well as tech experts and researchers. This book offers an exciting exploration of cutting-edge technology that goes beyond traditional computing methods. It gets into the nanoscale computing and introduces the concept of nanomagnetic logic, which has the potential to revolutionize how we process information.
Detailed Rundown of Subjects Treated:
Nanoscale Computing Basics:
The book starts with an accessible introduction to nanoscale computing, explaining the fundamental principles and significance of operating at such tiny scales, under the umbrella of “Rebooting Computing.”
Limitations of CMOS:
Readers will learn about the challenges faced by traditional computing methods and the challenges in achieving higher performance and efficiency.
Nanomagnetic Logic:
This is where the excitement builds up. Nanomagnetic logic is introduced as a game-changing concept that relies on the magnetic properties of nanoscale materials to process information in innovative ways.
Beyond CMOS Architectures:
The book ventures deep into various architectural designs that go beyond CMOS, showcasing how nanomagnetic logic can be integrated into next-generation computing systems.
Edge AI Devices:
The practical applications come into focus as the book explores how nanomagnetic logic can advance edge AI devices. This includes discussions on AI-driven technologies that can operate closer to the data source, enabling faster and more efficient processing.
This book stands out from competing titles because of its unique emphasis on the intersection of nanomagnetic logic with AI and architecture for edge devices. It bridges the gap between theoretical concepts and real-world applications, making it suitable for a broader range of readers, including both beginners and seasoned tech professionals. One of the book’s highlights is its emphasis on the applications of nanomagnetic logic in edge AI devices. It explores the integration of nanomagnetic logic in AI-driven technologies and provides case studies demonstrating its advantages. Additionally, hybrid computing systems that combine nanomagnetic logic with CMOS are explored, presenting a promising direction for energy-efficient computing. The challenges and future directions of nanoscale computing are also addressed, including reliability, scalability, and integration with existing technologies. The book concludes with a glimpse into the potential applications of nanomagnetic logic in emerging technologies, such as neuromorphic computing, IoT, bio-nanoelectronics, and environmental sensing leading to rebooting computing.
Chapters’ arrangement is as follows:
Chapter 1 introduces the foundational concepts of nanoscale computing, tracing its historical trajectory and practical significance. It begins by examining the connections between nanoscale computing and the rebooting computing initiative, emphasizing the need for a re-evaluation of traditional computing methods. The chapter then explores the limitations of CMOS technology and introduces nanomagnetic logic as a potential solution. It also discusses the role of edge AI devices in driving advancements in nanoscale computing and addresses architectural considerations and material design strategies. Lastly, the chapter outlines the objectives of the book and the key points it aims to cover.
Chapter 2 examines the practical constraints of traditional CMOS technology, discussing challenges including scaling limits, power consumption, and performance bottlenecks. It explores their implications on computing systems, including reduced processing power and energy efficiency concerns. The chapter also addresses technological and economic challenges, emphasizing the importance of adaptability and innovation. Additionally, it introduces nanomagnetic logic as a potential solution, outlining its advantages over CMOS. Educational emphasis is placed on delivering accessible technical content suitable for undergraduate audiences.
Chapter 3 provides a foundational understanding of nanomagnetic logic, starting with its basic principles and historical context. It explores essential elements such as coupling mechanisms, material selection, and spin dynamics crucial for designing logic gates. Signal processing aspects, generation, detection, and propagation, are examined alongside energy considerations and efficiency strategies. The chapter prioritizes accessible explanations for undergraduates, supplemented with practical examples and applications to enhance understanding. It concludes with a chapter-end quiz aimed at reinforcing comprehension and facilitating student engagement in exploring the intricacies of nanomagnetic logic.
Chapter 4 gets into nanomagnetic logic architectures, providing a comprehensive examination of their evolution and design principles. It starts by outlining the importance of architectural considerations and progresses to explore major architectures for both combinational and sequential logics. The chapter analyzes fundamental aspects such as magnetic implementation, quantum considerations, and benchmarking concepts. It further investigates parallel and pipelined architectures, focusing on enhancing computational throughput. Additionally, reconfigurable architectures are discussed, including dynamic reconfiguration concepts and their applications. The chapter concludes with a summary of key architectures and offers a chapter-end quiz to reinforce understanding.
Chapter 5 introduces material design for nanoscale computing. It emphasizes material selection’s importance. The chapter explores magnetic and nonmagnetic materials. It discusses their unique characteristics and applications. Additionally, it covers challenges and optimization strategies. The integration of multiferroic and spintronic materials is analyzed. Case studies in nanomagnetic logic computing are examined. The chapter concludes with future directions and a quiz.
Chapter 6 introduces nanoscale computing at the edge. It explores edge computing and defines its characteristics, and objectives. The chapter examines the intersection of nanoscale computing and edge AI, highlighting the role of nanomagnetic logic. It discusses AI integration in edge devices and its applications in IoT, healthcare, and robotics. Additionally, it offers a tutorial on developing edge AI applications, emphasizing hands-on learning. The chapter concludes by summarizing key concepts in edge AI, preparing for further discussions on hybrid computing in subsequent chapters.
Chapter 7 introduces hybrid computing systems and emerging applications. It defines hybrid computing systems, tracing their historical evolution and milestones. The chapter explores emerging applications driving hybrid systems, emphasizing the integration of nanomagnetic logic with other technologies. It delves into nanomagnetic–CMOS hybrid architectures, discussing benefits, performance enhancements, and applications. Additionally, it examines neuromorphic hybrid systems, focusing on advancements in cognitive computing and real-time learning. The chapter also explores emerging applications in industry, particularly in industrial automation, smart manufacturing, robotics, transportation, and agriculture. Lastly, it emphasizes demystifying hybrid computing concepts for educational purposes, preparing students for future industry challenges.
Chapter 8 introduces challenges, conclusions, a roadmap, and future perspectives in nanoscale computing. It outlines technical, educational, and policy challenges, emphasizing reliability, error rates, and scalability solutions. Additionally, it addresses the environmental impact and integration with other technologies like quantum computing, IoT, and edge AI. The chapter presents a roadmap for nanoscale computing technologies, discussing characteristics and conclusions. It explores research opportunities, inviting feedback and student involvement. Finally, it speculates on the mathematical trajectory plots concerning nanomagnetic logic, aiming to identify gaps in research and inspire future exploration in the field.
In conclusion, “Nanoscale Computing: The Journey Beyond CMOS with Nanomagnetic Logic: A Fundamental Textbook Advancing Edge AI Devices through Architecture and Material Design” under the umbrella of “Rebooting Computing” provides a comprehensive understanding of nanomagnetic logic and its applications, catering to a diverse audience of readers interested in cutting-edge technology.
About the Companion Website
This book is accompanied by a companion website:
www.wiley.com/go/sivasubramani/nanoscalecomputing1
This website includes:
Appendix A: End of Course Assessment Q&As - Chapter Wise
Appendix B: Fundamental - Micro-magnetic Simulation Tools
Appendix C: Architecture - Micro-magnetic Simulation Codes
Appendix D: Material Modeling Simulation Tools and Codes
1Introduction to Nanoscale Computing
Specific, Measurable, Achievable, Relevant, and Time-bound (SMART) learning objectives and goals for Chapter 1 are to:
Understand the historical development of nanoscale computing (NC) and its synergies with the rebooting computing (RC) initiative.
Define and explain the significance and applications of NC.
Comprehend the challenges posed by traditional complementary metal-oxide-semiconductor (CMOS) technology.
Familiarize the emergence of nanomagnetic logic (NML) as an alternative to CMOS.
NC is an emerging field which processes information at tiny scales. This is setting up the trend in technological innovations, which couldn’t have been possible earlier in information processing. NC is a multi-interdisciplinary field which changes the way we perceive and process information. It deals with the design and development of nanometer-scale components which can perform complex high-performance computations on the go. Novel material exploration, including carbon nanotube (CNT), graphene, and nanodots alongside novel fabrication techniques, is one of the key elements of NC. These material explorations could potentially replace or complement the silicon-based components used in traditional computing devices with their remarkable thermal and electric properties. This comprehends to the bigger goal of designing smaller, energy-efficient devices for RC. NC is also home to quantum computing, which performs computation by exploiting the principles of quantum mechanics. Qubits exist in dual states simultaneously, enabling quantum computers to process information beyond the capabilities of traditional computing. Superconducting circuits, trapped ions, and topological qubits are key nanoscale approaches for developing qubits to perform computationally intensive tasks. Though NC possesses enormous potential in designing and developing next-generation computing platforms for edge artificial intelligence (AI) devices, significant challenges are associated with overcoming them, ensuring energy-efficient operations without degradation in performance.
This chapter will talk about the brief overview in Section 1.1, the evolution Beyond CMOS in Section 1.2, edge AI devices as a driving force in Section 1.3, the architectural and material design in Section 1.4 and concludes the chapter detailing the scope of the book alongside the themes and the interactive assignment for encouraging readers in Sections 1.5 and 1.6. This ensures readers to actively participate in the new initiative of redefining educational models, serving as a motivation for undergraduate students and also a potential learning via fun exercise for advanced readers.
1.1 Overview of Nanoscale Computing
This section introduces the readers to the overview of NC. It briefly talks about the synergies in NC and rebooting computing (RC) in Section 1.1.1, defines the NC in Section 1.1.2 and historical development and the significance/applications in Section 1.1.3. Now let’s read through the synergies and intertwined perspective.
1.1.1 Synergies in Nanoscale Computing and the Rebooting Computing Initiative
RC is an IEEE initiative to rethink the design and build of computers (cf. Figure 1.1). Von Neumann’s architecture, introduced in the 1940s, is the basis for traditional computers, and it has started implications due to scaling concerns arising. RC aims to design and develop “from soup to nuts” – holistically in how computing is perceived, mitigating the challenges posed by the aforementioned.
NC and RC are intertwined areas focused on overcoming the limitations posed by traditional computing technologies. An extensive synergistic complement list of each other’s goals and vision is as follows:
Energy Efficiency
New Computing Paradigms
Figure 1.1 IEEE rebooting computingFile:IEEE Rebooting Computing TaskForce Logo.png https://commons.wikimedia.org/wiki/File:IEEE_Rebooting_Computing_TaskForce:Logo.png.
Source: IEEE Logo.
Scalability
Emerging Technologies
Performance Enhancement
Integrating nanoscale components into RC architectures paves the path toward advancing technologies.
1.1.1.1 Redefining Computing: Exploring the Interconnection
One significant aspect of this synergy is the exploration of (a) alternative materials and (b) fabrication techniques. RC encourages integrating these innovations into a broader framework, emphasizing the need for more efficient and powerful computing. RC recognizes the potential of quantum computing and deploys strategies for research and development. At the nanoscale, quantum effects bring in uncertainties and computational errors. RC acknowledges the need for resilient computing that works with fault tolerance. Thus, NC and RC collectively contribute to developing novel information-processing technologies.
The International Roadmap for Devices and Systems (IRDS) rightly articulates the emphasis on the Beyond CMOS computing paradigm and its corresponding application pulls, as depicted in the Figure 1.2. The device’s specification lies in the range of 100 up to 1 nm. To realize Beyond CMOS, the major three pillars of focus are as follows:
Emerging Architectures
Emerging Materials
Emerging Devices/Process
Figure 1.2 IRDS perspective on Beyond CMOS – next-generation computing paradigms File:Beyond CMOS IRDS.jpg https://commons.wikimedia.org/wiki/File:Beyond_CMOS_IRDS.jpg.
Source: Errolhunt/Wikimedia Commons/CC BY 4.0.
Figure 1.3 Intersection of quantum and nanoscale technologies File:Technology applications of quantum nanoscience.jpg https://commons.wikimedia.org/wiki/File:Technology_applications_of_quantum_nanoscience.jpg.
Source: Rickinasia/Wikimedia Commons/CC BY-SA 4.0.
This book talks about all of these three focus pillars throughout. As depicted in Figure 1.3, the intersection of quantum, an individual future direction initiative from IEEE, with the NC, emerges as a critical area of consideration and development touching base on basic science and technology nodes. This book covers a detailed run-through on quantum computing (QC) in later advanced chapters reflecting its goals and visions aligned toward RC. In the subsequent section, let’s understand more details on the NC (cf. Section 1.1.2).
1.1.2 Understanding Nanoscale Computing
In this section, we will get into more detail about understanding the NC. This section comprises the following subsections: Section 1.1.2.1 defines the scale, Section 1.1.2.2 contextualizes nanoscale technologies, Section 1.1.2.3 underscores its relevance to modern computing, and Section 1.1.2.4 presents a real-time analogy — for the clarity of the readers.
1.1.2.1 Defining the Scale
The three major factors determining the definition of scale for NC are as follows:
Size
Quantum effects
Fabrication methods
The fundamental three measurable parameters emerging as a key component in the NC paradigm are as follows:
Control of information
Different properties from its macroscopic counterparts
Reliability and efficiency
As aforesaid, NC refers to manipulating and controlling information at the nanometer scale, involving structures and devices operating on the order of nanometers. For understanding, one nanometer equals one billionth of a meter cf. Figure 1.4. At this minuscule size, the behavior of materials and devices differs significantly from their macroscopic counterparts, leading to unique opportunities and challenges in computing. Quantum effects introduce superposition and entanglement, differing from the classical behaviors observed in macroscopic systems. This necessitates a paradigm shift in how we conceptualize and engineer. Additionally, the fabrication techniques employed in NC play a pivotal role. Conventional manufacturing methods are often inadequate for creating structures at such minute dimensions. Therefore, it paved the way for exploring innovative self-assembly techniques and bottom-up manufacturing. These methods involve precise control; by comprehending and advancing these fabrication techniques, scientists aim to build reliable and efficient NC components, further emphasizing the interdisciplinary nature of this field.
Figure 1.4 Understanding the size of nano-scale definition [from glucose molecules at 1 nm to virus at 100 nm, nanomaterials cover a wide range of sizes. Take a look at this informative diagram] File:Comparison of nanomaterials sizes.jpg https://commons.wikimedia.org/wiki/File:Comparison_of_nanomaterials_sizes.jpg.
Sureshbup/Wikimedia Commons/CC BY-SA 3.0
1.1.2.2 Contextualizing Nanoscale Technologies
A multidisciplinary approach drawing upon the principles from physics, materials science, engineering, and computer science is required to contextualize nanoscale technologies and creates a holistic framework for understanding and applications. Emphasis is placed on the requirement of collaborative efforts to overcome the challenges of thermal and energy considerations. As components shrink, (cf. Figure 1.5) efficient thermal management and energy-efficient design technologies are critical to ensure reliable operation.
1.1.2.3 Relevance to Modern Computing
The prime focal point with relevance to modern computing is revisiting data storage. Traditional storage mediums face challenges in handling the rising volume of generated data. NC offers a paradigm shift by exploring innovative data storage approaches, ensuring faster and more powerful storage nodes. The application of nanoscale technologies also promises exponentially increasing computational speed. This acceleration is vital in today’s scenarios, where complex calculations and simulations are integral in scientific research and AI systems. NC systems exhibit a significant reduction in energy requirements for their operation in alignment with the ongoing environmental considerations, positioning it as a sustainable and eco-friendly alternative. Global academicians and industrial fellows also emphasize the compatibility of nanoscale technologies with emerging trends and technology predictions. The advent of Large Language Models (LLMs), edge computing, cloud computing, and the Internet of Things (IoT) necessitates powerful computing systems that are inherently adaptable to diverse and dynamic environments. Nanoscale components, with their versatility and scalability, seamlessly align with these evolving computing architectures, as pointed out by the IEEE International Roadmap for Devices and Systems.
Figure 1.5 Biological and technological scales compared File:Biological and technological scales compared-en.svg https://commons.wikimedia.org/wiki/File:Biological_and_technological_scales_compared-en.svg.
Source: Guillaume Paumier/Wikimedia Commons/CC BY 2.5.
1.1.2.4 Analogy
Think of the nanoscale as the world of ants. If traditional computing is like building structures for humans, NC is like creating complex ant colonies. The scale is tiny, but the complexity and organization are interesting (cf. Figure 1.6).
1.1.3 Historical Development
In this section, we will get into more detail about the historical development of the NC. This section comprises the following subsections: Section 1.1.3.1 defines the evolutionary milestones, Section 1.1.3.2 presents pioneering nanoscale technologies and key advances leading to NML, Section 1.1.3.3 presents a real-time analogy for the clarity of the readers, and Section 1.1.3.4 provides the significance/application. This sets the readers on the pathway of progression in the NC, unveiling the chronicle of breakthroughs, innovations, and transformations that help shape this field.
1.1.3.1 Evolutionary Milestones
Physicist Richard Feynman’s 1959 speech is the starting point for exploring NC. He outlined his vision for influencing matter at the atomic and molecular levels. This gave rise to the idea of nanotechnology. He envisioned nanotechnology even before the term was coined. With the famous saying, “Seeing is Believing”, the revolution in navigating NC began with the development of scanning tunneling microscopy (STM) in the 1980s, which made it possible for scientists to view and work with individual atoms. An increase in investment, with governments and industry players contributing billions to improve chip production and technological capabilities, is a significant ongoing evolutionary milestone. Uncertainties regarding the ongoing geopolitical tensions also affect the semiconductor industry globally alongside the expanding use cases of AI and LLMs, driving up demand for specialized, high-performance CPUs and GPUs. Concerns about security and sustainability, including environmental issues and the growing significance of cybersecurity, are crucial in determining the path taken. Developments in brain–computer interfaces, quantum computing, and NML pave the way for a revolution in the next-generation computing industry and fundamentally alter how human–machine relationships are perceived, targeting Industry 4.0, 5.0, and Beyond (cf. Table 1.1).
Figure 1.6 (a, b) Real-time analogy to compare and understand the world of ants and the NC.
Source: (a) lirtlon/Adobe Stock Photos. (b) catalin/Adobe Stock Photos.
1.1.3.2 Pioneering Nanoscale Technologies
The design and development of CNT and the atomic force microscopy (AFM) opened up new avenues for NC. Due to their remarkable qualities, CNTs started to be considered for use in constructing nanoscale transistors.
The demonstration of CNT forecasted nanoscale materials to be tiny and more efficient than their microscopic graphite counterparts. This signaled a change from abstract concepts to real-world developments.
Key Advances Leading to Nanomagnetic Logic:
The investigation of nanomagnetic logic is one of the major developments in NC. With its unique nanoscale magnetic characteristics, this technology node offers an alternative to conventional semiconductor-based logic.
NML offers higher computational density and less power consumption than its counterpart, showcasing promise for enhanced device performance and deployment.
1.1.3.3 Analogy
Consider the development of smartphones as a walk-through time analogous to NC (cf. Figure 1.7). From bigger, simple cell phones to advanced smartphones with embedded features. Comparably, NC has progressed from simple architectures to extremely sophisticated systems.
1.1.3.4 Significance and Applications
Considering the viable significance of NC and its real-time applications, sensors emerge as a transformative healthcare measure, enabling focused and accurate medical diagnosis. NC has its consequences for energy storage, opening the door to developing batteries with higher efficiency and PCP. These highlight NC’s concrete advantages and its potential to solve urgent global issues. NC emerges as a technological paradigm change that answers the problems encountered by conventional computing. The use-cases, historical evolution, and relevance of NC highlight the same. The field of computing is set for rapid developments, leading to the expansion of what can be accomplished with the continuous investigation and utilization of the unique characteristics of matter at the nanoscale.
Table 1.1 Key Evolution in the History of Semiconductors
Source: Compiled by the author from various sources including: Computer History Museum.
Year
Key evolution
1821
Thermoelectric effect observed in semiconducting metals
1874
Point-contact semiconductor rectification discovered
1894
Use of crystals to detect radio waves
1926
Patent for a field-effect semiconductor device
1931
Alan Wilson’s “The Theory of Electronic Semiconductors”
1940
Discovery of the p–n junction and photovoltaic effects
1947
Development of the bipolar point-contact transistor
1951
Invention of the static induction transistor
1954
Design of the first silicon junction transistor
1956
Creation of prototype silicon devices
1958
Invention of the microcircuit featuring active components
1959
Invention of the planar manufacturing process
1959
Creation of the first MOSFET
1963
Development of CMOS fabrication process
1964
Introduction of the first widely used analog IC
1965
Gordon Moore introduces Moore’s Law
1965
Manufacturing of semiconductor read-only-memory chips
1967
Report on a floating gate MOSFET
1968
Development of silicon-gate technology for ICs
1971
Release of the Intel 4004 microprocessor
1971
Coining of the term “Silicon Valley”
1971
Introduction of erasable, programmable read-only memory
1974
Samsung’s entry into the semiconductor business
1977
Release of the Apple II personal computer
1978
Development of programmable array logic devices
1980
Creation of Flash Memory
1984
Demonstration of the first double-gate MOSFET
1984
Foundation of ASML, specializing in photolithography
1985
Creation of Qualcomm as a semiconductor and tech company
1986
Japan becomes the biggest supplier in the global market
1987
Founding of TSMC in Taiwan
1993
Foundation of Nvidia, specializing in graphics processing
1997
First meeting of the World Semiconductor Council
2000
Establishment of SMIC in Shanghai
2007
iPhone revolutionizes smartphones
2016
Google introduces Tensor Processing Unit for ML
2020
Global chip shortage leading to semiconductor reevaluation
Jan 2021
TSMC announces $100 billion investment for semiconductor expansion.
Aug 2021
SMIC invests $8.87 billion for self-sufficiency in chip production.
Oct 2021
Google unveils Tensor Processing Unit (TPU) v4 for machine learning.
Dec 2021
India launched the Semicon India Programme – India’s Semiconductor Mission (ISM) for self-reliant sustainability
Feb 2022
Intel announces plans for two new chip factories
Apr 2022
Samsung confirms $45 billion investment to expand logic chip production.
Jun 2022
US–China trade war continues to impact semiconductor industry.
Sep 2022
NVIDIA acquires Arm for $40 billion.
Nov 2022
International Chips and Science Act, providing $52 billion for semiconductor research.
Jan 2023
TSMC announces development of 3nm chip manufacturing process.
Mar 2023
India unveils $70 billion semiconductor incentive program.
Jun 2023
First quantum computers with commercial applications begin to emerge.
Sep 2023
EU Chips Act proposed, to invest €43 billion in semiconductor research.
Dec 2023
Cybersecurity issues related to chip design and manufacturing gain prominence.
2024 and Beyond
Continued global focus on supply chain diversification and domestic chip production.
2024 and Beyond
Emergence of specialized chips for AI, AR/VR, and autonomous vehicles.
2024 and Beyond
Growing momentum in sustainability efforts for eco-friendly green chip manufacturing.
Figure 1.7 Real-time analogy to compare and understand the evolution of NC File:Mobile Phone Evolution 1992–2014.jpg https://commons.wikimedia.org/wiki/File:Mobile_Phone_Evolution_1992_-_2014.jpg.
Source: Jojhnjoy / Wikimedia / Public Domain.
The key significant application-oriented keywords for further exploration are: Quantum Leap; Beyond Binary; Medical Marvels; Energy Efficiency; Interdisciplinary Innovation; Practical Progress.
1.2 Evolution Beyond CMOS
This section introduces the readers to the evolution Beyond CMOS. It briefly talks about the dual historical perspective of the 75 Years of Transistor and the 100 Years of Spin in Section 1.2.1, defines the traditional challenges in Section 1.2.2, and elaborately introduces the emergence of NML in Section 1.2.3. Now, let’s walk through the evolution and the emergence.
1.2.1 The 75 Years of Transistor and 100 Years of Spin: A Dual Historical Perspective
Over the decades, the transistor and spin have significantly impacted the development of technology. For the past 75 years, silicon-based CMOS technology has been at the forefront of electronic device development. Constant evolution and progress in transistor performance and energy efficiency have been the driving parameters since the first planar-gate MOSFET demonstration in the late 1950s. This has revolutionized the world of electronics we use today in this new post-COVID-19 digital era (Figures 1.8, 1.9, and 1.10).
In parallel, research on understanding spin-particles’ intrinsic angular momentum has been evolving. However, spintronics-based devices have just gained traction. The Datta-Das SPINFET, which used the spin of electrons to modify and control information in a transistor, marks a significant advancement. Compared to traditional CMOS technology, this achieves low-power and high-speed operation. Appelbaum and Monsma have proposed the transit time spin field-effect transistor in Silicon.
The relationship between spin and transistors is notable in the history of technology. For the past 75 years, the transistor, which can control and amplify electrical signals, has ruled contemporary computing. Utilizing the inherent qualities of particles, spin has created new avenues for information processing and storage. The combination of the transistor and spin allows advanced development in computing and communication. This emerging study area can completely change our thoughts on the fundamental building blocks of next-generation computing. The intertwining perspective of 75 years of transistors and 100 years of spin highlights advancing technology’s continuous evolution and integration.
Figure 1.8 (a,b) 75 Years of transistors and the 100 year of spin – dual historical perspective. a) File:Bardeen Shockley Brattain 1948.JPG https://commons.wikimedia.org/wiki/File:Bardeen_Shockley_Brattain_1948.JPG
Source: (a) AT&T; photographer: Jack St / Wikimedia / Public Domain.
b) File:Wolfgang Pauli.jpg https://commons.wikimedia.org/wiki/File:Wolfgang_Pauli.jpg
(b) CERN Document Server/CC BY-4.0.
Figure 1.9 75 Years of transistors and the 100 year of spin – dual historical perspective – prototype representations. a) File:Nachbau desersten Transistors.jpg https://commons.wikimedia.org/wiki/File:Nachbau_des_ersten_Transistors.jpg
Source: (a) Stahlkocher at German Wikipedia/Wikimedia/CC BY SA 3.0.
b) File:Spinor on the circle.png https://commons.wikimedia.org/wiki/File:Spinor_on_the_circle.png
Source: (b) Slawekb at English Wikipedia, CC BY-SA 3.0 https://creativecommons.org/licenses/by-sa/3.0, via Wikimedia Commons.
Figure 1.10 (a,b) 100 Years of spin — historical perspective — hand in hand theory and experimentation.
Source: a)File:SternGerlach2.jpg https://commons.wikimedia.org/wiki/File:SternGerlach2.jpg
(a) Peng/Wikimedia/CC BY SA 3.0.
b) ElectronSpinLeiden2017.jpg https://commons.wikimedia.org/wiki/File:ElectronSpinLeiden2017.jpg
Source: (b) Vysotsky/Wikimedia/CC BY SA 4.0.
1.2.2 Challenges of Traditional CMOS Technology
CMOS technology has been the backbone of the semiconductor industry, enabling the development of efficient electronic devices. However, as we go toward more complex applications and push the limits of miniaturization, significant issues result. This section will examine the obstacles researchers and engineers confront around three significant challenges: scaling, power dissipation, and performance. Subsequently, Section 1.2.2.1 details scaling limitations, Section 1.2.2.2 discusses power dissipation issues, and Section 1.2.2.3 provides a detailed brief on performance bottlenecks.
1.2.2.1 Scaling Limitations
The focus on the decreasing transistor size has propelled the industry forward. However, we face severe hurdles as we go closer to nanoscale levels. Quantum phenomena and fundamental physical limits traditional CMOS scaling. Quantum tunneling effects become more evident at such small scales, leading to increased leakage currents and decreased dependability. The three key parameters are as follows:
Quantum effects and variability
Gate oxide thickness and tunneling currents
Innovations beyond traditional CMOS
One critical issue is that transistor channel length approaches the de Broglie wavelength of electrons. Electron flow regulation becomes less predictable, resulting in variable transistor behavior and increased sensitivity to manufacturing fluctuations. Statistical variances are amplified by a reduction in the number of channel electrons, generating uncertainty in transistor properties. Overcoming these scalability constraints necessitates innovative materials and structures, instigating researchers to explore beyond traditional CMOS paradigms.
1.2.2.2 Power Dissipation Issues
With the growing demand for energy-efficient electronic devices, power dissipation becomes a crucial challenge. Power density increases as transistor sizes reduce, posing heat dissipation and energy consumption difficulties. Leakage current is a significant contributor to power dissipation. Subthreshold and gate leakage become increasingly prominent as transistor size shrinks in typical CMOS. Subthreshold leakage happens when a transistor conducts current despite being off-state. This phenomenon is amplified in nanoscale transistors, considerably impacting the system’s total power efficiency. The three key parameters are as follows:
Leakage currents and subthreshold conduction
Gate leakage and quantum tunneling
Power gating and dynamic voltage and frequency scaling (DVFS)
Furthermore, the gate oxide thickness reduction to overcome scaling constraints impacts overall power consumption. In order to address power dissipation, novel transistor topologies, low-power design methodologies, and improved materials are gaining momentum. Power gating and DVFS are used for the purpose of having its critiques.
1.2.2.3 Performance Bottlenecks
The interconnect delay is a key
