Phase-Locked Loops E-Book

Woogeun Rhee

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 541

Veröffentlichungsjahr: 2023

Beschreibung

Phase-Locked Loops Discover the essential materials for phase-locked loop circuit design, from fundamentals to practical design aspects A phase-locked loop (PLL) is a type of circuit with a range of important applications in telecommunications and computing. It generates an output signal with a controlled relationship to an input signal, such as an oscillator which matches the phases of input and output signals. This is a critical function in coherent communication systems, with the result that the theory and design of these circuits are essential to electronic communications of all kinds. Phase-Locked Loops: System Perspectives and Circuit Design Aspects provides a concise, accessible introduction to PLL design. It introduces readers to the role of PLLs in modern communication systems, the fundamental techniques of phase-lock circuitry, and the possible applications of PLLs in a wide variety of electronic communications contexts. The first book of its kind to incorporate modern architectures and to balance theoretical fundamentals with detailed design insights, this promises to be a must-own text for students and industry professionals. The book also features: * Coverage of PLL basics with insightful analysis and examples tailored for circuit designers * Applications of PLLs for both wireless and wireline systems * Practical circuit design aspects for modern frequency generation, frequency modulation, and clock recovery systems Phase-Locked Loops is essential for graduate students and advanced undergraduates in integrated circuit design, as well researchers and engineers in electrical and computing subjects.

Leseprobe

Table of Contents

Cover

Table of Contents

Title Page

Copyright

Dedication

Preface

About Authors

1 Introduction

1.1 Phase‐Lock Technique

1.2 Key Properties and Applications

1.3 Organization and Scope of the Book

Bibliography

Part I: Phase‐Lock Basics

2 Linear Model and Loop Dynamics

2.1 Linear Model of the PLL

2.2 Feedback System

2.3 Loop Dynamics of the PLL

2.4 Noise Transfer Function

2.5 Charge‐Pump PLL

2.6 Other Design Considerations

References

Note

3 Transient Response

3.1 Linear Transient Performance

3.2 Nonlinear Transient Performance

3.3 Practical Design Aspects

References

Notes

Part II: System Perspectives

4 Frequency and Spectral Purity

4.1 Spur Generation and Modulation

4.2 Phase Noise and Random Jitter

References

Note

5 Application Aspects

5.1 Frequency Synthesis

5.2 Clock‐and‐Data Recovery

5.3 Clock Generation

5.4 Synchronization

References

Notes

Part III: Building Circuits

6 Phase Detector

6.1 Non‐Memory Phase Detectors

6.2 Phase‐Frequency Detector

6.3 Charge Pump

References

7 Voltage‐Controlled Oscillator

7.1 Oscillator Basics

7.2 LC VCO

7.3 RING VCO

7.4 Relaxation VCO

References

Notes

8 Frequency Divider

8.1 Basic Operation

8.2 Circuit Design Considerations

8.3 Other Topologies

References

Note

Part IV: PLL Architectures

9 Fractional‐N PLL

9.1 Fractional‐N Frequency Synthesis

9.2 Frequency Synthesis with Delta‐Sigma Modulation

9.3 Quantization Noise Reduction Methods

9.4 Frequency Modulation by Fractional‐N PLL

References

Notes

10 Digital‐Intensive PLL

10.1 DPLL with Linear TDC

10.2 DPLL with 1‐Bit TDC

10.3 Hybrid PLL

References

Note

11 Clock‐and‐Data Recovery PLL

11.1 Loop Dynamics Considerations for CDR

11.2 CDR PLL Architectures Based on Phase Detection

11.3 Frequency Acquisition

11.4 DLL‐assisted CDR Architectures

11.5 Open‐Loop CDR Architectures

References

Note

Index

End User License Agreement

List of Tables

Chapter 2

Table 2.1 Relationship among

ζ, ω

u

, and

K

.

Chapter 3

Table 3.1 Static phase error performance of the type 1 and type 2 PLLs.

Chapter 5

Table 5.1 PLL specifications for GSM standard.

Chapter 10

Table 10.1 Architecture comparison.

List of Illustrations

Chapter 1

Figure 1.1 Accurate frequency control by a phase‐lock technique.

Figure 1.2 Three key applications of the PLL: (a) frequency synthesis; (b) C...

Figure 1.3 Other applications: (a) modulation; (b) demodulation; (c) carrier...

Chapter 2

Figure 2.1 Linear model of the PLL.

Figure 2.2 Understanding 1/

s

in the linear model of the PLL.

Figure 2.3 Linear model of the FLL.

Figure 2.4 Linear model of the PLL including a frequency divider.

Figure 2.5 Phase margin and gain margin.

Figure 2.6 Type 2 system with a system zero.

Figure 2.7 Open‐loop gain of the first‐order PLL with

F

(

s

) = 1.

Figure 2.8 Second‐order type 1 PLL with a lead‐lag filter.

Figure 2.9 Second‐order type 2 PLL with an active integrator.

Figure 2.10 Two‐path control of the type 2 PLL.

Figure 2.11 Transient behavior with

ζ

= 0.25, 0.5, 0.707, 1, and 2.

Figure 2.12 Visual insight on loop dynamics of the type 2 PLL.

Figure 2.13 Third‐order PLLs: (a) type 2 and (b) type 3.

Figure 2.14 Noise bandwidth.

Figure 2.15 Open‐loop gain and noise transfer functions.

Figure 2.16 Input jitter clean‐up PLL with low‐pass NTF.

Figure 2.17 Simulated noise performance of open‐loop and closed‐loop VCOs: (...

Figure 2.18 Effective

Q

of the PLL as a BPF.

Figure 2.19 Basic function of the PFD and charge pump.

Figure 2.20 Charge pump with an

RC

loop filter.

Figure 2.21 Fourth‐order type 2 CP‐PLL: (a) block diagram and (b) open‐loop ...

Figure 2.22 Role of

RC

parameters: (a)

ω

u

for NTF; (b)

ω

z

for stab...

Figure 2.23 Another role of the shunt capacitor.

Figure 2.24 Third‐order type 2 CP‐PLL.

Figure 2.25 Open‐loop gain of the third‐order type 2 CP‐PLL.

Figure 2.26 Monitoring on‐chip control voltage at the VCO input (case

A

) or ...

Figure 2.27 PLL design aspect in the open‐loop gain.

Chapter 3

Figure 3.1 Transient settling behavior of traditional PLLs.

Figure 3.2 Settling time with a frequency error.

Figure 3.3 Settling time of the second‐order type 2 PLL with a frequency ste...

Figure 3.4 Second‐order type 2 CP‐PLL.

Figure 3.5 Lock‐in, pull‐in, and hold‐in ranges.

Figure 3.6 Hold‐in range.

Figure 3.7 Pull‐in range: (a) beat‐tone generation by the PD and (b) pull‐in...

Figure 3.8 Lock‐in range.

Figure 3.9 Hangup effect: (a) PD with a sawtooth transfer function and (b) h...

Figure 3.10 Transient performance with a frequency‐step input: (a) type 1 an...

Figure 3.11 State‐variable model of the PLL.

Figure 3.12 Two‐path control in the second‐order type 2 CP‐PLL.

Figure 3.13 Transient settling behavior of an overdamped CP‐PLL.

Figure 3.14 Two‐path control with the dual charge pumps.

Figure 3.15 Simplified block diagram of the type 2 DPLL.

Figure 3.16 Slew‐rate comparison: (a) CP‐PLL and (b) op amplifier.

Figure 3.17 Transient settling behavior including the large‐signal region.

Figure 3.18 Settling time reduction with VCO pre‐tuning.

Chapter 4

Figure 4.1 Spectrum comparison of AM and narrowband FM signals.

Figure 4.2 SSB decomposition into FM and AM.

Figure 4.3 Effect of limiter on SSB signal.

Figure 4.4 Spur generation by VCO modulation.

Figure 4.5 DJ in the time domain and spurs in the frequency domain.

Figure 4.6 Effect of frequency division.

Figure 4.7 Effect of frequency multiplication.

Figure 4.8 Reference spur generation in PLL.

Figure 4.9 Reference spur reduction with the high‐order pole.

Figure 4.10 Phase offset due to leakage current.

Figure 4.11 Phase offset due to CP current mismatch: (a)

I

UP

=

I

DN

and (b)

I

Figure 4.12 Transient waveforms of

I

CP

and

V

CTR

with shunt capacitor.

Figure 4.13 Phase offset control by the mismatch of the charge pump currents...

Figure 4.14 Phase offset by the mismatch of the PFD delay.

Figure 4.15 Reference spur generation in the third‐order CP‐PLL.

Figure 4.16 Spectral information of a real‐time signal with a narrow BPF.

Figure 4.17 Measurement of phase noise.

Figure 4.18 Simplified block diagram of a spectrum analyzer.

Figure 4.19 Phase noise calculation from a spectrum analyzer plot.

Figure 4.20 Effect of frequency multiplication on phase noise.

Figure 4.21 Phase noise effect in digital communication systems.

Figure 4.22 Phase noise plot of the first‐order PLL.

Figure 4.23 RJ calculation from the spectrum.

Figure 4.24 PLL with various noise sources.

Figure 4.25 Phase noise contribution of each source at the output of the thi...

Figure 4.26 Finding the source of in‐band phase noise: (a) phase noise with ...

Figure 4.27 Finding the VCO noise contribution to in‐band phase noise.

Chapter 5

Figure 5.1 Key applications of the PLL with design aspects.

Figure 5.2 Direct frequency synthesis: (a) incoherent; (b) coherent; and (c)...

Figure 5.3 PLL‐based frequency synthesis: (a) block diagram and (b) key desi...

Figure 5.4 Example of a PLL having a large

N

to meet the frequency resolutio...

Figure 5.5 Frequency synthesis for fine resolution: (a) using a hybrid frequ...

Figure 5.6 Traditional fractional‐N PLL: (a) block diagram and (b) timing di...

Figure 5.7 Phase noise effect on transceiver performance.

Figure 5.8 In‐band blocking for GSM system.

Figure 5.9 Optical transceiver (SerDes) system.

Figure 5.10 Electrical link: (a) clock‐forwarding and (b) clock‐embedded met...

Figure 5.11 Traditional CDR circuit.

Figure 5.12 PLL‐based CDR circuit.

Figure 5.13 Jitter generation.

Figure 5.14 Jitter transfer property with perfect jitter filtering.

Figure 5.15 Jitter peaking and jitter accumulation.

Figure 5.16 Jitter tolerance.

Figure 5.17 Jitter tolerance: (a) measurement setup and (b) JTOL mask.

Figure 5.18 Design trade‐offs of the CDR PLL.

Figure 5.19 Comparison of CDR and frequency synthesis.

Figure 5.20 System design aspects in wireless and wireline systems.

Figure 5.21 Clock jitter consideration for a transmitter PLL: (a) RJ by tota...

Figure 5.22 Peak‐to‐peak jitter due to RJ.

Figure 5.23 Total jitter with RJ and DJ contribution.

Figure 5.24 CP‐PLL with two noise sources.

Figure 5.25 Phase noise contribution at PLL output.

Figure 5.26 Clock skew problem in chip‐to‐chip communication.

Figure 5.27 Clock de‐skewing by an on‐chip PLL.

Figure 5.28 Delay‐locked loop: (a) block diagram and (b) linear model.

Figure 5.29 Phase error propagation of the PLL and DLL with supply jump: (a)...

Figure 5.30 False‐lock problem of the DLL.

Figure 5.31 DLLs for frequency multiplication: (a) using an edge‐combining D...

Chapter 6

Figure 6.1 Multiplier PD.

Figure 6.2 XOR PD.

Figure 6.3 Flip‐flop PD.

Figure 6.4 S/H PD.

Figure 6.5 Sub‐sampling PD: (a) functional block diagram with a charge pump ...

Figure 6.6 PFD: (a) block diagram and operation principle and (b) PD charact...

Figure 6.7 Frequency acquisition aid by the PFD: (a) up and down outputs wit...

Figure 6.8 Dead‐zone effect of the PFD: (a) PFD‐induced and (b) charge‐pump‐...

Figure 6.9 PFD without dead‐zone.

Figure 6.10 (a) PFD characteristic at high frequency and (b) Δt

on

effect on ...

Figure 6.11 Charge pump design: (a) DC compliance voltage range under 5% mat...

Figure 6.12 Design flow of the charge pump circuit.

Figure 6.13 Circuit topologies of single‐ended charge pumps: (a) with drain ...

Figure 6.14 Current mirror with different modes in the drain‐switching charg...

Figure 6.15 Performance comparison with large gate capacitance for noise fil...

Figure 6.16 Schematic of a high‐performance source‐switching charge pump.

Figure 6.17 Semi‐differential charge pumps: (a) current‐steering switching a...

Figure 6.18 Schematic of a fully differential charge pump.

Figure 6.19 Functional diagram: (a) with phase locked and (b) with VCO phase...

Figure 6.20 Comparison of the MOS capacitor and accumulation‐mode varactor: ...

Figure 6.21 Effective capacitance of the symmetric accumulation‐mode varacto...

Figure 6.22 Conversion of a differential LPF to a single‐ended LPF model.

Figure 6.23 Second‐order type 1 CP‐PLL with the differential loop filter.

Figure 6.24 CP‐PLL with an XOR PD.

Figure 6.25 Simulation results of the CP‐PLL with other types of PDs: (a) co...

Chapter 7

Figure 7.1 On‐chip oscillators: (a) LC oscillator; (b) ring oscillator; and ...

Figure 7.2 Oscillation principle: (a) positive‐feedback condition and (b) fr...

Figure 7.3 LC resonator: (a) series model and (b) parallel model.

Figure 7.4 Impedance transformation: (a) inductor and (b) capacitor.

Figure 7.5 Loaded

Q

of the LC tank.

Figure 7.6 (a) LC tank with injected current noise and (b) frequency stabili...

Figure 7.7 Noise model of oscillator.

Figure 7.8 Effect of the internal noise and quality factor.

Figure 7.9 Typical phase noise performance of the VCO.

Figure 7.10 Effect of the external coupling noise.

Figure 7.11 LC VCO with cross‐couple transistors.

Figure 7.12 LC oscillator viewed as a two‐stage LC‐tuned amplifier with posi...

Figure 7.13 Amplifier with an LC‐tuned load after impedance transformation....

Figure 7.14 Oscillation with voltage‐ and current‐limiting modes.

Figure 7.15 Accumulation‐mode varactor: (a) physical structure and (b) volta...

Figure 7.16 Noise contribution of the cross‐coupled transistors.

Figure 7.17 Tail capacitance effect for

M

1

in the linear region.

Figure 7.18 Tail capacitance effect on waveform asymmetry.

Figure 7.19 Up‐conversion mechanism of the tail current noise by frequency m...

Figure 7.20 LC VCO circuit topologies: (a) with a tail current source; (b) w...

Figure 7.21 Class‐C LC VCO.

Figure 7.22 LC VCO with common‐mode noise filtering.

Figure 7.23 LC VCO with capacitor array and its tuning range.

Figure 7.24 Single‐input dual‐path VCO and its tuning range.

Figure 7.25 Loop dynamics of the PLL with the single‐input dual‐path VCO.

Figure 7.26 Ring oscillator: (a) single‐ended and (b) differential topologie...

Figure 7.27 Noise analysis of a single‐ended ring oscillator.

Figure 7.28 Noise analysis of a differential ring oscillator: (a) noise sour...

Figure 7.29 Single‐ended VCDL: (a) using a current‐starved inverter; (b) usi...

Figure 7.30 Differential VCDL with amplitude control: (a) using a diode load...

Figure 7.31 Differential VCDL based on the phase‐interpolated delay: (a) del...

Figure 7.32 Pseudo‐differential ring VCO with a latch and a varactor.

Figure 7.33 Relaxation oscillator with a ground capacitor.

Figure 7.34 Relaxation oscillator with a floating capacitor.

Figure 7.35 Relaxation oscillator with constant amplitude swing.

Chapter 8

Figure 8.1 Frequency division based on the prescaling technique.

Figure 8.2 Prescaler‐based counter versus synchronous counter.

Figure 8.3 Low‐power frequency divider for a fixed division ratio of 1,001....

Figure 8.4 General frequency division with the prescaler.

Figure 8.5 General frequency division with the prescaler: (a) calculation of...

Figure 8.6 2/3 dual‐modulus divider based on the pulse‐swallowing technique:...

Figure 8.7 4/5 dual‐modulus divider.

Figure 8.8 Dual‐modulus divider with nested prescalers.

Figure 8.9 Multi‐modulus dividers: (a) 3/4/5 prescaler and (b) 48/49/50 modu...

Figure 8.10 Single‐ended DFF: (a) with the static latch and (b) with the TSP...

Figure 8.11 2/3 prescaler with the TSPC logic circuits.

Figure 8.12 Divide‐by‐2 circuit with a master‐slave CML latch.

Figure 8.13 Design aspects of the CML divider.

Figure 8.14 Design of cascaded divide‐by‐2 circuits.

Figure 8.15 CML latch with an on‐chip current biasing circuit.

Figure 8.16 Programmable divider with the CML prescaler and standard counter...

Figure 8.17 CML DFF with an embedded OR gate.

Figure 8.18 32/33 dual‐modulus divider with a wrong MC signal path.

Figure 8.19 Generation of synchronous MC delay with asynchronous counters.

Figure 8.20 32/33 dual‐modulus divider with an improved MC signal path.

Figure 8.21 16/17 dual‐modulus divider: (a) with the conventional 4/5 presca...

Figure 8.22 Phase‐interpolated fractional divider.

Figure 8.23 (2

k

 + 

M

) multi‐modulus divider.

Figure 8.24 Miller divider.

Figure 8.25 Injection‐locked dividers: (a) based on the LC oscillator and (b...

Figure 8.26 ILO spectrum with injection‐lock range

ω

L

.

Chapter 9

Figure 9.1 Interpolative frequency division by oversampling.

Figure 9.2 Traditional fractional‐N PLL.

Figure 9.3 4‐Modulo fractional‐N PLL with a 2‐bit accumulator.

Figure 9.4 Phase compensation by the DAC and a 4‐modulo example.

Figure 9.5 Phase compensation by the DTC.

Figure 9.6 Multi‐phase fractional‐N division and a 4‐modulo example.

Figure 9.7 Fractional‐N division with pseudo‐random modulation.

Figure 9.8 Fractional‐N division with ΔΣ modulation.

Figure 9.9 Comparison of the PRM and the ΔΣ modulation.

Figure 9.10 Simplified block diagram of an early‐stage frequency synthesizer...

Figure 9.11 ΔΣ ADC with a 1‐bit quantizer: (a) block diagram and (b) transie...

Figure 9.12 Equivalent sampled‐data model.

Figure 9.13 Spectral density of the quantization noise.

Figure 9.14 Second‐order modulator.

Figure 9.15 Modulation quantization noise with different OSRs.

Figure 9.16 Transient waveforms: (a) the first‐order modulator and (b) the s...

Figure 9.17 Cascaded modulator.

Figure 9.18 Third‐order MASH modulator.

Figure 9.19 Third‐order SLDSM with a 1‐bit quantizer.

Figure 9.20 Third‐order SLDSM with a 3‐bit quantizer.

Figure 9.21 Input range comparison of the single‐bit and the multi‐bit quant...

Figure 9.22 SLDSM characteristics: (a) pole‐zero plot and (b) NTF comparison...

Figure 9.23 Comparison of the output‐bit patterns: (a) MASH and (b) SLDSM.

Figure 9.24 Phase noise due to quantization noise (

f

s

= 10 MHz).

Figure 9.25 Phase noise contribution in the type‐2 fourth‐order fractional‐N...

Figure 9.26 Comparison of quantization noise effect with three PLLs: (a) wit...

Figure 9.27 Dynamic range consideration in ΔΣ fractional‐N division.

Figure 9.28 Comparison of multi‐bit ΔΣ ADC and fractional‐N PLL: (a) ΔΣ ADC ...

Figure 9.29 Output phase noise of the ΔΣ fractional‐N PLL with a third‐order...

Figure 9.30 Integer‐boundary spur generation by coupling.

Figure 9.31 Quantization noise reduction: (a) by charge compensation and (b)...

Figure 9.32 Fractional‐N PLL with the hybrid FIR filtering technique.

Figure 9.33 Hybrid FIR filtering: (a) combined

s

‐domain and

z

‐domain models ...

Figure 9.34 Performance comparison: (a) output spectra and (b) control volta...

Figure 9.35 Digital FIR filter: (a) block diagram and (b) transfer function ...

Figure 9.36 Finite‐modulo fractional‐N PLL with the S/H PD and hybrid FIR fi...

Figure 9.37 Simulated control voltages of 8‐modulo fractional‐N PLL with and...

Figure 9.38 Frequency modulation by the ΔΣ fractional‐N PLL.

Figure 9.39 Two‐point modulation.

Figure 9.40 Simplified linear model of the two‐point modulator.

Figure 9.41 Nonideal effects of gain and delay mismatches.

Chapter 10

Figure 10.1 Digital‐intensive PLL.

Figure 10.2 Time‐to‐digital converter: (a) a block diagram and (b) timing di...

Figure 10.3 DPLL modeling with time‐continuous approximation.

Figure 10.4 Phase‐domain model of the DPLL.

Figure 10.5 CP‐PLL analogy.

Figure 10.6 Loop dynamics with charge pump analogy: (a) equivalent linear mo...

Figure 10.7 TDC resolution effect on the phase noise and bandwidth.

Figure 10.8 TDC with enhanced resolution: (a) pseudo‐differential‐delay TDC ...

Figure 10.9 TDC variation examples: (a) with a gated ring oscillator; (b) wi...

Figure 10.10 DCO topologies: (a) switched‐array based and (b) DAC based.

Figure 10.11 LC DCO schematic.

Figure 10.12 Ring DCO schematic: (a) using an inverter matrix and (b) using ...

Figure 10.13 DCO resolution effect on phase noise.

Figure 10.14 DPLL with a 1‐bit TDC.

Figure 10.15 BB‐DPLL model with quantization‐induced jitter only.

Figure 10.16 Limit‐cycle jitter with and without loop latency (first‐order l...

Figure 10.17 BBPD characteristic with input jitter.

Figure 10.18 BB‐DPLL model with random jitter included.

Figure 10.19 ΔΣ fractional‐N BBPLL: (a) peak phase error due to modulation (...

Figure 10.20 BB‐DPLL with the DTC for linearized PD gain.

Figure 10.21 In‐band noise reduction with the 1‐bit output SLDSM.

Figure 10.22 Two‐stage architecture comparison: (a) cascaded integer‐N linea...

Figure 10.23 Phase‐domain low‐pass filtering method: (a) with the nested PLL...

Figure 10.24 Comparison of the 1‐point and 2‐point modulations in the BB‐DPL...

Figure 10.25 TDC resolution variation over supply voltage.

Figure 10.26 Semi‐digital PLL with a hybrid loop control.

Figure 10.27 Linear model of the HPLL.

Figure 10.28 Practical implementation of the hybrid loop control: (a) with d...

Chapter 11

Figure 11.1 PLL‐based CDR: (a) conceptual block diagram and (b) design trade...

Figure 11.2 Jitter transfer and jitter peaking characteristics of the CDR PL...

Figure 11.3 Jitter‐tracking characteristic of the PLL in comparison with JTR...

Figure 11.4 Jitter tolerance: (a) JTOL and jitter‐tracking characteristics o...

Figure 11.5 Converting NRZ to an RZ‐like signal: (a) differentiator and squa...

Figure 11.6 Hogge PD: (a) block schematic and its use in the CP‐PLL and (b) ...

Figure 11.7 Phase offset in the Hogge PD.

Figure 11.8 Data pattern dependency in the Hogge PD (

V

c

waveform exaggerated...

Figure 11.9 Triwave Hogge PD.

Figure 11.10 Binary phase detection: (a) DFF for binary phase detection and ...

Figure 11.11 Alexander PD.

Figure 11.12 Binary PD gain.

Figure 11.13 Limit cycle jitter: (a) BBPLL with loop latency and (b) increas...

Figure 11.14 Half‐rate Alexander PD.

Figure 11.15 Baud‐rate PD: (a) comparison with the Alexander PD and (b) conc...

Figure 11.16 Simplified MMPD with sign bits: (a) timing diagram and (b) circ...

Figure 11.17 Frequency detection with quadrature mixers.

Figure 11.18 Quadricorrelator with symmetric configuration.

Figure 11.19 Frequency detection with double‐edge DFFs.

Figure 11.20 Bang‐bang frequency detector.

Figure 11.21 Frequency acquisition using the FD.

Figure 11.22 Frequency acquisition with an external reference clock.

Figure 11.23 D/PLL‐based CDR: (a) block diagram and (b) open‐loop gain.

Figure 11.24 (a) Linear model of the D/PLL and (b) jitter transfer function....

Figure 11.25 JTRAN and JTRACK comparison: (a) type 2 PLL and (b) type 2 D/PL...

Figure 11.26 P/DLL‐based CDR.

Figure 11.27 P/DLL CDR with a clock delay for JTOL and JGEN only.

Figure 11.28 Frequency‐tracking DLL.

Figure 11.29 DLL‐based CDR for multiple serial links.

Figure 11.30 Blind oversampling CDR.

Figure 11.31 Burst‐mode CDR.

Figure 11.32 Burst‐mode CDR circuits with improved control of the gated VCO:...

Guide

Cover

Table of Contents

Title Page

Copyright

Dedication

Preface

About Authors

Begin Reading

Index

End User License Agreement

Pages

ii

iii

iv

v

xiii

xiv

xv

1

2

3

4

5

6

7

8

9

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

135

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

237

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

IEEE Press

445 Hoes Lane Piscataway, NJ 08854

IEEE Press Editorial Board

Sarah Spurgeon,

Editor in Chief

Jón Atli Benediktsson

Anjan Bose

James Duncan

Amin Moeness

Desineni Subbaram Naidu

Behzad Razavi

Jim Lyke

Hai Li

Brian Johnson

Jeffrey Reed

Diomidis Spinellis

Adam Drobot

Tom Robertazzi

Ahmet Murat Tekalp

Phase-Locked Loops

System Perspectives and Circuit Design Aspects

Woogeun Rhee and Zhiping Yu

Tsinghua UniversityBeijing, China

Copyright © 2024 by The Institute of Electrical and Electronics Engineers, Inc.All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.Published simultaneously in Canada.

No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per‐copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750‐8400, fax (978) 750‐4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748‐6011, fax (201) 748‐6008, or online at http://www.wiley.com/go/permission.

Trademarks: Wiley and the Wiley logo are trademarks or registered trademarks of John Wiley & Sons, Inc. and/or its affiliates in the United States and other countries and may not be used without written permission. All other trademarks are the property of their respective owners. John Wiley & Sons, Inc. is not associated with any product or vendor mentioned in this book.

Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. Further, readers should be aware that websites listed in this work may have changed or disappeared between when this work was written and when it is read. Neither the publisher nor authors shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages.

For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762‐2974, outside the United States at (317) 572‐3993 or fax (317) 572‐4002.

Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com.

Library of Congress Cataloging‐in‐Publication Data Applied for:

Hardback: 9781119909040

Cover Design: WileyCover Image: © Tuomas A. Lehtinen/Getty Images

To my parents and my wife, Soojung, and

To my acacemic adviser Prof. Bang‐Sup Song

Woogeun Rhee

To my academic advisers Prof. Zhijian Li of Tsinghua University, and

Prof. Robert W. Dutton of Stanford University

Zhiping Yu

Preface

Over 15 years of giving a phase‐locked loop (PLL) course to graduate students, the authors felt a strong need for one textbook that covers PLL basics, system perspectives, practical design aspects for integrated circuits, and PLL architecture for both wireless and wireline communication systems. Without such a book, the PLL lecture had to be given based on several textbooks. Even though there are many PLL books available for circuit designers, most of them can be classified into three types. The first one is a theory‐oriented book that describes the PLL based on control and communication theories but lacks circuit details. The second type of book deals with more circuits but is mostly based on discrete circuits, not covering practical design issues over on‐chip variability or modern PLL architectures such as fractional‐N PLLs. The last one is a circuit‐oriented book but does not describe a PLL from system basics to circuit design aspects for diverse applications with an integrated step‐by‐step format.

This book combines bottom‐to‐top and top‐to‐bottom approaches to address the system and circuit design aspects of the PLL, covering essential materials for circuit designers, from fundamentals to practical design aspects. Compared with circuit‐oriented PLL books, this book has substantial material on system design considerations in addition to circuit design aspects for wireless and wireline applications. Unlike other PLL books from the area of communication systems, this book mainly focuses on the linear behaviors of the PLL and describes them in an intuitive way without deriving mathematical analyses and equations in detail, while touching system analyses tailored for circuit designers. Below are some examples.

Is the critical damping ratio of loop dynamics ever used for on‐chip PLL design?

Is the natural frequency

ω

n

from control theory as meaningful as the loop gain to circuit designers?

Is the type 2 PLL with other phase detectors as well as the

phase‐frequency detector

(

PFD

) able to provide the infinite range of frequency acquisition if not limited by circuits? Does the PFD behave like other phase detectors after frequency acquisition?

Do we implement the second‐order type 2 charge‐pump PLL in practice? Why should we consider third‐order or fourth‐order type 2 charge‐pump PLLs in most cases?

How to consider a peak‐to‐peak jitter budget from random jitter if the random jitter is unbounded in theory?

How to analyze clock jitter in the frequency domain? How to relate phase noise and sidebands to the time‐domain jitter?

Do we care about frequency‐domain sidebands for clock generation if their level is lower than the carrier power by 40 dB?

Is the

digital‐intensive phase‐locked loop

(

DPLL

) totally a new PLL architecture that requires

z

‐domain analysis?

The first half of the book covers system basics, while the second half deals with hardware implementation. In the first half, PLL basics and system design considerations are discussed. In addition to the linear and transient behaviors of the PLL, analyzing clock jitter in the frequency domain is deeply explained. In addition, the book addresses system design trade‐offs for three key applications: frequency synthesis, clock‐and‐data recovery, and clock generation/synchronization. In the second half, building circuits and PLL architectures for the three applications are discussed by considering system and circuit design aspects. Also, frequency generation and modulation circuits based on analog, digital‐intensive, and hybrid PLL architectures are described. Learning system architectures and circuit design trade‐offs in wireless and wireline systems, readers will gain the knowledge of where and how to design the PLL for a broad range of applications.

The authors would like to thank Su Han, Xuansheng Ji, Luhua Lin, Longhao Kuang, Qianxian Liao, and Liqun Feng in the School of Integrated Circuits at Tsinghua University for a lot of help drawing figures. Special thanks to Liqun Feng who not only reviewed technical details with valuable comments but also provided many simulation plots.

Beijing, China

Woogeun RheeZhiping Yu

About Authors

Woogeun Rhee, Ph.D., is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He has over 25 years of professional career in integrated circuit design with nearly 10 years in industry and 17 years in academia. Dr. Rhee has worked on PLL architectures and circuits not only with different careers (academia and industry) but also over different fields (wireless and wireline systems). He is an IEEE Fellow.

Zhiping Yu, Ph.D., is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He is an IEEE Life Fellow with over 400 published papers on subjects related to ICCAD, nanoelectronics, and RF circuit design.

1Introduction

1.1 Phase‐Lock Technique

A basic concept of a phase‐locked feedback system for frequency generation was proposed in the early 1930s, but the use of a phase‐locked loop (PLL) circuit for mass production began with analog television systems in the 1940s. Since then, the PLL has been one of the most critical building blocks in modern communication IC systems, covering both wireless and wireline applications.

What is the main function of the PLL? From the name and a block diagram shown in Fig. 1.1, it can be deduced that it is the loop that performs a phase lock between a reference clock and an output clock. In the coherent communication systems that use the amplitude and phase information of a signal for modulation and demodulation, interestingly, the phase‐lock has not been the primary goal of the PLL in most cases. Let us look at some descriptions of the PLL in other books.

A circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as in phase [Best].

A circuit that synchronizes the signal from an oscillator with a second input signal, so that they operate at the same frequency [Egan].

When the loop is (phase) locked, the control voltage sets the average frequency of the oscillator exactly equal to the average frequency of the input signal [Gardner].

Basically, an oscillator whose frequency is locked onto some frequency component of an input signal, which is done with a feedback control loop [Wolaver].

The first description addresses the basic function of the PLL both in phase and frequency domains. In the second or the third description, the goal of the PLL is to achieve the same frequency as the input frequency by using a phase‐lock technique. In the last description, the phase lock was not even mentioned, and the PLL was simply defined as an oscillator whose frequency is locked to the input frequency. As implied by those descriptions, we can see that the primary goal of the PLL is not the phase‐lock but the frequency‐lock. This is because the frequency offset between an input signal and a local oscillator in the coherent receiver system is much more serious than the phase offset problem.

Figure 1.1 Accurate frequency control by a phase‐lock technique.

If the main goal of the PLL is to achieve the frequency‐lock, we may wonder if a frequency‐locked loop (FLL) should be used instead of the PLL. The reason is that the FLL still generates a static frequency error if there exist circuit mismatches, a limited loop gain at DC, or a limited resolution in a frequency detector. To the contrary, the PLL generates a static phase error rather than the frequency error in the presence of a limited loop gain at DC or imperfect matching in a phase detector circuit. Since the frequency error fe is the derivative of the phase error θe, the PLL always achieves a zero‐frequency error even with the presence of a static phase error illustrated in Fig. 1.1. In other words, the PLL guarantees that the accuracy of an output frequency is the same as that of a source frequency based on the phase‐lock technique. From that point of view, the PLL can be referred as a phase‐locking loop rather than the phase‐locked loop since the phase‐lock is not the goal but an active method to achieve the frequency‐lock. This explains why the PLL has been dominantly employed in the coherent communication system where the frequency offset between a carrier and a local oscillator is critical. When the PLL is used for frequency generation, we may regard the PLL as the oscillator circuit that generates an adaptive DC control voltage Vctr to an internal voltage‐controlled oscillator (VCO) so that a stable output frequency is maintained over process‐voltage‐temperature (PVT) variations as depicted in Fig. 1.1.

1.2 Key Properties and Applications

In addition to the zero‐frequency error, there is another important property. The PLL is the only device that performs auto‐tracking band‐pass filtering with high‐quality factor Q and wide tunability. The high‐Q band‐pass filtering with wide tunability is possible since the bandwidth of a PLL can be independently set without limitation to an output frequency, while the tunability is determined by the tuning range of a VCO regardless of the PLL bandwidth. This feature is well utilized for clock‐and‐data recovery (CDR) systems to extract a clean clock from a noisy input data. In the CDR system, the phase‐lock property is also used to define an optimum edge‐of‐clock position for data retiming. Besides those two properties, the inherent property of the PLL, phase‐lock, makes the PLL play an important role in modern wireline communication systems. As data rate or clock frequency increases, clock de‐skewing or phase synchronization has become critical to enhance the data throughput of serial I/O interfaces since the advent of the monolithic PLL implemented with complementary metal‐oxide semiconductor (CMOS) technology in the late 1980s. Below is the summary of three fundamental properties of the PLL:

Zero‐frequency error

High‐

Q

auto‐tracking BPF

Phase synchronization

With those three features, the PLL has been employed for diverse communication systems. We briefly introduce several applications of the PLL, and some key applications will be discussed in detail in later chapters.

1.2.1 Frequency Synthesis

Since the PLL enables the zero‐frequency offset between a reference clock and a feedback clock, this feature can be used to generate multiple output frequencies by adding counters in the reference clock path and the feedback clock path of the PLL. As depicted in Fig. 1.2(a), with a fixed reference frequency fref, the output frequency fout can be set by simply changing the counting values of the digital counters, that is, M and N in the reference‐path and the feedback‐path counters, respectively. Then, we obtain fout given by N × (fref/M) since the feedback frequency (= fout/N) must be equal to the phase‐detector frequency fPD (= fref/M) after the phase‐lock. Therefore, the frequency accuracy of the PLL is as good as that of the stable reference source which is typically a crystal oscillator.

1.2.2 Clock‐and‐Data Recovery

There are three main roles of the PLL for CDR systems. Firstly, a phase detector of the PLL directly extracts a clock information from a non‐return‐to‐zero (NRZ) data without requiring other nonlinear circuits such as a differentiator followed by a squarer as done in traditional CDR systems. Secondly, the PLL acts as a high‐Q auto‐tracking band‐pass filter to recover a clean clock from noisy incoming data by rejecting high‐frequency jitter. Thirdly, the PLL recovers the data by re‐timing the data with the extracted clean clock. The data retiming is normally performed with a D‐type flip‐flop (DFF). The phase‐lock feature is also utilized for the data re‐timing. For example, the falling edge of a recovered clock is used to trigger the DFF when the transition edge of the NRZ data is synchronized to the rising edge of the recovered clock, which gives an optimum clock position for bit slicing, i.e. data retiming as illustrated in Fig. 1.2(b).

Figure 1.2 Three key applications of the PLL: (a) frequency synthesis; (b) CDR; and (c) synchronization.

1.2.3 Synchronization

Clock jitter has become more important than ever for input/output (I/O) links in recent chip‐to‐chip communications as clock speed increases. In addition to the clock jitter, a clock skew between an internal clock and an external clock is a concern with high clock frequency. The delay variation due to a big clock tree in a chip significantly increases a worst‐case clock skew, making available phase margin much less than expected. By having the clock tree as the part of a PLL, the clock skew variation between the external clock CKext and the internal clock CKint due to the clock tree can be minimized as illustrated in Fig. 1.2(c). Since the frequency offset is negligible in the chip‐to‐chip communication, a delay‐locked loop (DLL) having a voltage‐controlled delay line can also be used to achieve better power supply rejection and more flexible clock control than the PLL.

1.2.4 Modulation and Demodulation

In modern transceiver systems, the PLL plays an important role not only as a local oscillator but also as a frequency/phase modulator. These days, digital frequency/phase modulation based on a fractional‐N PLL, as shown in Fig. 1.3(a), greatly simplifies the transmitter architecture. We will discuss how a direct‐digital modulation is achieved by the PLL in Chapter 9. Figure 1.3(b) also shows two cases of an FM demodulator and a PM demodulator. For the modulations and the frequency demodulation, the bandwidth of the PLL needs to be wide enough to track the frequency/phase variation. To the contrary, a very narrow bandwidth of the PLL is required to provide an averaged reference phase over a frequency drift for the phase demodulation. The narrow‐bandwidth PLL is not desirable for an on‐chip design as the phase noise contribution of a VCO becomes too high, which will be learned later.

Figure 1.3 Other applications: (a) modulation; (b) demodulation; (c) carrier recovery and (d) frequency translation.

1.2.5 Carrier Recovery

A good example of a PLL‐based carrier recovery system can be found in analog television systems. Figure 1.3(c) shows the simplified block diagram of a color‐signal demodulator. A color‐burst signal is embedded as a sub‐carrier and used as a reference phase for the color‐signal demodulation. The PLL generates a reference clock whose phase is synchronized to that of the color‐burst signal. The phase difference between each color signal and the reference clock is used to provide different color information. Therefore, a narrow‐bandwidth PLL using a highly stable VCO such as a voltage‐controlled crystal oscillator (VCXO) is designed. In addition to the carrier recovery, additional PLLs are used for horizontal synchronization (H‐sync) and vertical synchronization (V‐sync) in the analog television system. Since the PLL was a versatile building block in the television system for mass production, many practical architectures and circuit techniques were developed, including a phase‐frequency detector (PFD), a charge‐pump PLL, an all‐digital PLL with a numerically controlled oscillator (NCO), and so on.

1.2.6 Frequency Translation

A frequency‐translation circuit offers a flexible frequency planning for frequency generation systems. As shown in Fig. 1.3(d), instead of having a large‐value frequency divider, a mixer is put in a feedback path with another local oscillator (LO), making a phase‐detector frequency fPD become an intermediate frequency fIF. Therefore, an LO frequency (fLO) is effectively translated to a desired output frequency. With a high fPD and the absence of a frequency divider, a wide‐bandwidth PLL can be designed with low phase noise contribution from the LO and the reference source. Figure 1.3(d) shows an example of how a low‐noise frequency synthesizer is implemented with the frequency‐translation loop where fine frequency resolution is achieved by having another PLL or a direct‐digital frequency synthesizer as the LO.

1.3 Organization and Scope of the Book

This book consists of four major parts, covering basic theories, system and application perspectives, circuit design aspects, and PLL architectures. In the first part, the essential basics of the PLL for circuit designers are described. The linear and transient behaviors of the PLL are discussed in Chapters 2 and 3, respectively. In the second part, Chapter 4 describes system design parameters by discussing the relationship between clock and frequency in the time and frequency domains. Based on the system knowledge gained from previous chapters, Chapter 5 discusses system perspectives for three key applications; frequency synthesis, clock‐and‐data recovery, and synchronization. The content of Chapter 5 is rather advanced and can be considered a reference for Chapters 9 and 11. Chapters 6–8 of the third part describe building blocks, putting emphasis on basic operation principles and practical design aspects for integrated circuit design. In the last part, various PLL architectures for different applications are discussed. We begin with fractional‐N PLL architectures in Chapter 9, move to digital‐intensive PLL architectures in Chapter 10, and discuss CDR PLL architectures in Chapter 11. This book puts more weight on the traditional PLL architectures and their analyses for frequency generation and expands the discussion of circuits and design trade‐offs for other PLL architectures. This is not the thick PLL book that contains all details of system theories and circuit details but could be one of the PLL books that cover essential materials with balanced system perspectives and circuit design aspects for circuit and system designers. Other valuable resources are listed below.

Bibliography

1

R. E. Best,

Phase‐Locked Loops: Design, Simulation, and Applications

, 5th ed., McGraw‐Hill, New York, 2003.

2

W. Egan,

Frequency Synthesis by Phase Lock

, 2nd ed., Wiley, New York, 2000.

3

W. Egan,

Phase‐Locked Basics

, 2nd ed., Wiley, Hoboken, NJ, 2008.

4

K. Feher,

Telecommunications Measurements, Analysis, and Instrumentation

, Prentice‐Hall, Englewood Cliffs, NJ, 1987.

5

F. M. Gardner,

Phaselock Techniques

, 3rd ed., Wiley, Hoboken, NJ, 2005.

6

V. F. Kroupa,

Frequency Synthesis: Theory, Design et Applications

, Wiley, New York, 1973.

7

V. F. Kroupa,

Phase Lock Loops and Frequency Synthesis

, Wiley, Hoboken, NJ, 2007.

8

T. Lee,

The Design of CMOS Radio‐Frequency Integrated Circuits

, Cambridge University Press, United Kingdom, 1997.

9

W. C. Lindsey and C. M. Chie (eds),

Phase‐Locked Loops

, IEEE Press, New York, 1986.

10

V. Manassewitsch,

Frequency Synthesizers, Theory and Design

, 3rd ed., Wiley, New York, NY, 1987.

11

H. Meyr and G. Ascheid,

Synchronization in Digital Communications, Phase‐, Frequency‐Locked Loops, and Amplitude Control

, Wiley, New York, 1990.

12

B. Razavi (ed.),

Monolithic Phase‐Locked Loops and Clock Recovery Circuits

, IEEE Press, New York, 1996.

13

B. Razavi (ed.),

Phase‐Locking in High‐Performance Systems

, IEEE Press, New York, and Hoboken, NJ: Wiley, 2003.

14

B. Razavi,

RF Microelectornics

, 2nd ed., Prentice Hall, Upper Saddle River, NJ, 2012.

15

B. Razavi,

Design of Integrated Circuits for Optical Communications

, Wiley, New York, 2012.

16

B. Razavi,

Design of CMOS Phase‐Locked Loops: From Circuit Level to Architecture Level

, Cambridge University Press, United Kingdom, 2020.

17

W. Rhee (ed.),

Phase‐Locked Frequency Generation and Clocking: Architectures and Circuits for Modern Wireless and Wireline Systems

, The Institution of Engineering and Technology, United Kingdom, 2020.

18

U. L. Rohde,

Microwave and Wireless Frequency Synthesizers: Theory and Design

, Wiley, New York, 1997.

19

K. Shu and E. Sanchez‐Sinencio,

CMOS PLL Synthesizers; Analysis and Design

, Springer, New York, 2005.

20

R. B. Staszewski and P. T. Balsara,

All‐Digital Frequency Synthesizer in Deep‐Submicron CMOS

, Wiley, Hoboken, NJ, 2006.

21

D. H. Wolaver,

Phase‐Locked Loop Circuit Design

, Prentice Hall, Englewood Cliffs, NJ, 1991.

Part IPhase‐Lock Basics

2Linear Model and Loop Dynamics

For circuit designers, it would be more meaningful to consider the practical design aspects of a PLL for various applications than understanding complete mathematical descriptions originated from communication systems (knowing those would be useful though). It is because desired loop parameters for the on‐chip PLL design over process, temperature, and voltage (PVT) variations could be different from what we would have obtained based on theoretical analyses. Indeed, designing a robust PLL with optimum system parameters is valuable in integrated‐circuit systems rather than designing a best PLL under ideal conditions. Experienced PLL circuit designers seldom design a critically damped loop but consider either an overdamped or underdamped loop in practice.

2.1 Linear Model of the PLL

A feedback system is basically a nonlinear system. Then, why are we interested in the linear model of a PLL? It is because most system performances in which we are interested are determined when the PLL operates within a lock‐in range, that is, the PLL maintains a small phase error and does not exceed the linear range of a phase detector. Good examples are phase noise and static phase error performances. In the design of a PLL circuit, nonlinear analyses are used mainly to describe the transient response of the PLL before fully settled. In other words, we are mostly interested in the small‐signal behavior of a PLL after a large‐signal transient response is fully settled.

Figure 2.1 shows the basic linear model of a PLL. A phase detector (PD) compares the phases of an input signal and a VCO signal, and it generates the voltage that is proportional to the phase difference. The PD gain Kd is measured in units of volts per radian, that is V/rad. Depending on the PD type, a free‐running voltage Vdo, that is, a fixed DC voltage generated with a zero‐phase error appears in the PD transfer function as depicted in Fig. 2.1. In the linear model of the PLL, only the slope and the linear range of the PD transfer function are considered. A loop filter is the low‐pass filter (LPF) that rejects high‐frequency noise in the loop. Ultimately, we need a very narrow bandwidth to tune the output frequency of a VCO with a DC‐like voltage, but the 3‐dB corner frequency of the loop filter cannot be too low because of other noise considerations. The transfer function of the loop filter F(s) determines the type and order of a PLL. A VCO is the oscillator that modulates the frequency in response to a control voltage. The VCO gain Kv is defined by a frequency change to an input‐voltage change, measured in units of radians per second per volt, that is rad/s/V, or hertz per volt, that is Hz/V. A free‐running frequency ωc is the output frequency of the VCO with a floating control voltage but often refers to the center frequency of the VCO tuning range.

Figure 2.1 Linear model of the PLL.

In the linear model, we note that there is an integrator, 1/s, in the VCO model. It is not because the VCO performs integration during voltage‐to‐frequency conversion but because the phase is used as an error estimate in the loop. Figure 2.2 shows an equivalent liner model of the PLL and explains how the integrator is embedded in the VCO. For example, let us consider a frequency‐locked loop (FLL) where a frequency detector generates a frequency error to control the VCO. In the linear model of the FLL shown in Fig. 2.3, the integrator is not put in the VCO even if the same VCO circuit is used. Accordingly, the FLL is more stable than the PLL for a given loop bandwidth. However, the FLL suffers from the frequency error problem as discussed in Chapter 1.

Figure 2.2 Understanding 1/s in the linear model of the PLL.

Figure 2.3 Linear model of the FLL.

2.2 Feedback System

Feedback is essential in analog circuit design. One of the reasons is the variation of analog parameters. Therefore, desensitizing the analog parameters is important, which can be done by a feedback topology with a stable reference. In the voltage domain, a bandgap reference voltage is a good reference, while a crystal oscillator is the one in the frequency domain.

2.2.1 Basics of Feedback Loop

An open‐loop gain (or open‐loop transfer function) is highly useful to analyze the loop dynamics of a feedback system. In Fig. 2.1, the open‐loop gain G(s) is

(2.1)

The order of a loop is defined by the number of poles in G(s). The number of integrators, that is, the number of poles at the origin (s = 0) determines the type of the loop. Since the VCO inherently contains 1/s, the loop type of a PLL is at least one. If the loop filter contains another integrator, we call it a type 2 PLL. A closed‐loop transfer function (also called a system transfer function) H(s) from an input phase to an output phase is given by

(2.2)

For the first‐order PLL, the 3‐dB corner frequency of H(s) is the same as the unity‐gain frequency of G(s). Similarly, an error transfer function He(s) from an input phase to a phase error is expressed as

(2.3)

Note that He(s) exhibits a high‐pass filter (HPF) transfer function with the same 3‐dB corner frequency of H(s). It means that the PLL tracks the low‐frequency components of an input phase, while untracked high‐frequency components of the input phase are shown as phase errors.

For the frequency synthesizer that generates multiple frequencies from a low reference frequency, a feedback factor needs to be considered in the linear model of the PLL because a frequency divider is used in the feedback path. For a division ratio N, a feedback factor of N−1 is to be used. Figure 2.4 shows the linear model that includes a feedback factor. Since N is constant over frequency, it only plays as a scaling factor in the open‐loop gain. Now, we consider a feedforward gain Gf(s) given by (2.1). Then, the system transfer function is expressed as

(2.4)

Figure 2.4 Linear model of the PLL including a frequency divider.

The 3‐dB frequency is reduced by N, while the DC gain is increased by 20logN. Note that the division ratio N not only multiplies the input frequency but also amplifies the input phase variation. For the sake of simplicity, we will exclude the feedback factor to analyze the loop dynamics of the PLL in the rest of this chapter.

2.2.2 Stability

In the negative feedback system, stability is one of the most important things to be considered. For stability analysis, graphical methods are commonly used, including Nyquist diagrams, Evans (root locus) plots, Nicholas charts, and Bode plots. Among them, the Bode plot is well adopted for the stability analysis of a PLL because it gives a straightforward interpretation of the loop dynamics with the distinctive locations of poles and zeros. In addition, circuit designers who know how to design a stable operational amplifier should be familiar with the Bode plot.

For the quantitative analysis of stability, a phase margin or gain margin obtained from the open‐loop gain is used. To understand the physical meaning of the phase margin and gain margin, let us consider how a negative feedback system becomes unstable. A negative feedback system becomes a positive feedback system when there is a 180° phase‐shift in the negative feedback loop with an open‐loop gain equal to or higher than unity as illustrated in Fig. 2.5. Because of the 1/s term in the VCO, a phase shift of 90o is already made in the loop. Therefore, the maximum allowable phase margin is 90° with a first‐order PLL. If a second‐order PLL is designed, additional phase delay occurs due to the pole of a loop filter. The phase margin is defined by an excess phase available from the 180° phase shift when the open‐loop gain is unity. For example, a phase margin of 30° means that there is a total phase delay of 150° in the loop at the unity‐gain frequency. The less the phase margin is, the less stable is the feedback system. Similarly, the gain margin is an excess gain available from the unity gain when the total phase shift of the loop is 180°. The phase margin is more often used in practice than the gain margin since the gain margin cannot be evaluated if the phase delay in the loop does not reach 180°, for example the first‐order PLL. Even though the Nyquist plot or root locus plot shows the detailed information of how a system becomes unstable, the Bode plot is good enough as a starting point for the loop analysis.

Figure 2.5 Phase margin and gain margin.

Figure 2.6 Type 2 system with a system zero.

Figure 2.6 illustrates why the type 2 feedback system must have a zero in the loop dynamics. Each integrator lags the phase by 90° in the loop, causing a total phase delay of 180°. Accordingly, the type 2 system cannot be stable since the phase margin is 0°, oscillating at a frequency so‐called as natural frequency ωn. By providing a fast path in the system, that is, bypassing the integrator, a system zero is formed, and a non‐zero phase margin is obtained. Depending on the gain (or strength) of the fast path, the phase margin of the loop is determined.

2.3 Loop Dynamics of the PLL

Depending on the LPF configuration, a PLL has different types and orders. Despite various types and orders, having a good knowledge of the second‐order type 2 PLL is enough in the design of PLL circuits for most commercial applications, the grounds of which will be discussed in this chapter.

2.3.1 First‐Order Type 1 PLL

The simplest PLL would be a first‐order type 1 PLL with a constant LPF gain. Assuming F(s) = Kf, the open‐loop gain becomes

(2.5)

Figure 2.7 Open‐loop gain of the first‐order PLL with F(s) = 1.

In the first‐order PLL, a loop gain K is defined by

(2.6)

Then, the closed‐loop transfer function is given by

(2.7)

In the first‐order feedback system, the unity‐gain frequency of G(s) is the same as the 3‐dB corner frequency of H(s). The first‐order type 1 PLL is unconditionally stable with a constant phase margin of 90° as illustrated in Fig. 2.7. The unity‐gain frequency ωu in G(s) is given by

(2.8)

We can see that the unity‐gain frequency and the loop gain are related with each other. That is, to have a wide bandwidth, a high loop gain is required. With a finite loop gain, transient behaviors such as a lock‐in or pull‐in range exhibit worse performance than those of higher‐order PLLs. More importantly, the type 1 PLL has the problem of a static phase error for the change of an input frequency. Therefore, the use of the first‐order PLL by itself is limited in many applications. Those problems will be discussed in the next chapter.

2.3.2 Second‐Order Type 1 PLL

An easy way of implementing a second‐order PLL is to add an RC LPF in the loop. When the 3‐dB corner frequency of the RC filter is put outside the bandwidth of the PLL, the overall behavior of the second‐order PLL is similar to that of the first‐order type 1 PLL except second‐order filtering outside the bandwidth. In other words, the unity‐gain frequency and loop gain are still related with each other.

Figure 2.8 Second‐order type 1 PLL with a lead‐lag filter.

Now let us consider the case of putting the 3‐dB corner frequency of the RC filter within the bandwidth of the PLL. To compensate for the degraded phase margin due to a pole within the bandwidth, a zero should be added. A lead‐lag RC filter shown in Fig. 2.8