Polymeric Materials for Electronic Packaging E-Book

Shozo Nakamura

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 214

Veröffentlichungsjahr: 2023

Beschreibung

POLYMERIC MATERIALS FOR ELECTRONIC PACKAGING Create and deploy reliable polymeric materials for use in electronic products with this comprehensive guide Modern electronic products are manufactured at a finer scale and with more precision than ever before. This places increasing demand on the proper use and management of high-performance polymers to create reliable, rapidly-operating semiconductor products. Understanding the physical properties and viscoelasticity analysis of resins is essential for engineers and researchers to perfect and deploy these polymers in electronics contexts. Polymeric Materials for Electronic Packaging is designed to meet this specific need with a thorough introduction to these materials and their production. It provides the tools engineers need to reduce processing times and increase durability in their semiconductor packages and products. Translated from the Japanese original and offering in-depth analysis from a global-leading expert, this promises to be an indispensable volume. Polymeric Materials for Electronic Packaging readers will also find: * Detailed treatment of subjects including viscoelastic theory, design issues of LSI packages, and more * Analysis uniquely suited to the dimensions of cutting-edge semiconductor technology * Incorporation of cutting-edge viscoelasticity analysis software, available separately from the author Polymeric Materials for Electronic Packaging is critical for electrical and electronics engineers working with semiconductors, as well as advanced postgraduate students and researchers in this or numerous related areas.

Leseprobe

IEEE Press445 Hoes LanePiscataway, NJ 08854

IEEE Press Editorial BoardSarah Spurgeon, Editor in Chief

Jón Atli Benediktsson

Behzad Razavi

 Jeffrey Reed

Anjan Bose

Jim Lyke

 Diomidis Spinellis

James Duncan

Hai Li

 Adam Drobot

Amin Moeness

Brian Johnson

Tom Robertazzi

Desineni Subbaram Naidu

Ahmet Murat Tekalp

Polymeric Materials for Electronic Packaging

Shozo Nakamura

Doctor of Engineering, Professor EmeritusHiroshima Institute of Technology, and Corporate TechnicalAdviser, Japan

Copyright © 2023 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.Published simultaneously in Canada.

No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per‐copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750‐8400, fax (978) 750‐4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748‐6011, fax (201) 748‐6008, or online at http://www.wiley.com/go/permission.

Trademarks: Wiley and the Wiley logo are trademarks or registered trademarks of John Wiley & Sons, Inc. and/or its affiliates in the United States and other countries and may not be used without written permission. All other trademarks are the property of their respective owners. John Wiley & Sons, Inc. is not associated with any product or vendor mentioned in this book.

Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Further, readers should be aware that websites listed in this work may have changed or disappeared between when this work was written and when it is read. Neither the publisher nor authors shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages.

For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762‐2974, outside the United States at (317) 572‐3993 or fax (317) 572‐4002.

Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com.

Library of Congress Cataloging-in-Publication DataNames: Nakamura, Shozo (Professor Emeritus), author.Title: Polymeric materials for electronic packaging / Shozo Nakamura.Description: Hoboken, New Jersey : Wiley, [2023] | Includes bibliographical references and index.Identifiers: LCCN 2023013757 (print) | LCCN 2023013758 (ebook) | ISBN 9781394188796 (hardback) | ISBN 9781394188802 (adobe pdf) | ISBN 9781394188819 (epub)Subjects: LCSH: Conducting polymers. | Electronic packaging.Classification: LCC QD382.C66 N35 2024 (print) | LCC QD382.C66 (ebook) | DDC 620.1/9204297--dc23/eng20230708LC record available at https://lccn.loc.gov/2023013757LC ebook record available at https://lccn.loc.gov/2023013758

Cover Design: WileyCover Image: © Nikola Ilic/Getty Images

About the Author

Shozo Nakamura, Professor Emeritus, Hiroshima Institute of Technology, and Corporate Technical Adviser, Japan. Professor Nakamura graduated from the Department of Mechanical Engineering, Hiroshima Institute of Technology in 1971 after which he joined Hitachi Limited. He became a Doctor of Engineering in 1989, and a Professor in 2000 at the Department of Intelligent Mechanical Engineering, Hiroshima Institute of Technology. He established the Nakamura Technical Research Institute in 2019. He was given the title of Professor Emeritus in 2018. He has written numerous publications on viscoelasticity.

Preface

After graduating from university, I joined Hitachi, Ltd. and engaged in research on the viscoelastic analysis of the strength of general‐purpose resins, stress, and deformation of semiconductor encapsulation resins at the Yokohama Research Institute (later, Production Technology Research Institute). After that, moving from Hitachi to university, I was involved in research on viscoelasticity analysis for half a century throughout Hitachi and college.

Currently, smartphones, iPads, notebook PCs, etc., are widespread. Many semiconductor packages are frequently used in these electronic products, and resins are used in these semiconductor packages without exception.

The viscoelastic properties of this resin greatly affect the strength and deformation reliability of semiconductor packages, and optimal design technology based on resin viscoelastic analysis is indispensable for improving the quality of electronic products that make heavy use of semiconductor packages.

I was troubled by the viscoelastic properties of the resin when evaluating the reliability of semiconductor packages in the past. That is, as described in detail in the text, the semiconductor package is composed of many different materials such as LSI chips, resins, metals, solders, and substrates, and in particular, resins play various roles such as sealing LSI chips and buffering thermal stress.

In the development of semiconductor packages that are becoming lighter, thinner, shorter, and smaller, it is a major technical issue to prevent minute cracks and peeling at the resin and it adhesive interface, and to prevent warpage deformation due to the heat load during manufacturing. The optimal design of the materials, structures, and thermal processes that make up the semiconductor package was indispensable.

However, the stress simulation analysis half a century ago is based on the elastic theory, and it is a fatal problem that the viscoelastic behavior in which the elastic modulus and linear expansion coefficient of the resin are greatly affected by time and temperature is not taken into consideration.

As an episode under development at Hitachi, the warp direction of the actual product was the exact opposite of the analysis result, and I clarified that the cause of the defect is largely related to the viscoelastic property of the resin.

From this bitter experience, I strongly felt the need to develop a viscoelastic analysis and persuaded my boss to start the development. As a result, after 10 years, I developed viscoelastic analysis software and named it VESAP (Visco Elastic Stress Analysis Program). This VESAP is useful for the rapid and optimized design of materials, structures, and thermal processes to prevent defects in strength and deformation of electronic components including all resins such as semiconductor packages.

My aim in VESAP development was to focus on analysis software that can be easily and quickly utilized by nonspecialized researchers and engineers, and that contributes to shortening the product development period as an immediate force. Of course, the basis of the idea of analysis software is supported by the theory of viscoelasticity.

After that, I received technical consultations from many major companies in the electronics field such as semiconductor packages, electronic components, and resin substrates. The contents are concrete, such as

what kind of physical properties are optimal for preventing cracks and warp deformation at the joint interface, and

what physical properties are involved in strength and warp deformation. It was a quantitative requirement.

By the way, the connection between viscoelasticity and me is the encounter with Professor Yasushi Miyano, who was transferred from Hitachi, Ltd. to a professor at Kanazawa Institute of Technology, and Professor Takeshi Kunio, an emeritus professor at Keio University.

While working at Hitachi from early morning to late night, I desperately wrote research papers and presented at academic conferences without returning home, and obtained a doctorate in engineering. This is also a result of the guidance of both professors. Both the professors were strict but passionate guides to research and warm personalities, full of humanity. I would like to express my deep gratitude to both professors.

On the other hand, my relationship with semiconductor packages was the encounter with Dr. Gen Murakami, who was the development leader at the Musashi Work of Hitachi, Ltd. As described in Chapter 1, the semiconductor package has changed from a pin insertion type to a surface mount type represented by LOC (Lead On Chip) and QFP (Quad Flat Package), and is a smaller and thinner CSP (Chip Scale Package). It has greatly developed and changed into a type of BGA (Ball Grid Array)‐CSP. Dr. Murakami is a pioneer of this semiconductor package.

I thank Dr. Murakami for his guidance owing to which I was able to contribute to the development and application of VESAP, and I would like to express my sincere gratitude to him.

In addition, although VESAP was developed during the Hitachi era, many issues such as its application limits could be clarified through basic research with university students. Thanks to these students.

Furthermore, I would like to express my sincere gratitude to Sandra Grayson – Senior Commissioning Editor, Becky Cowan – Senior Editorial Assistant, and Jayashree S – Managing Editor, and Mustaq Ahamed – Content Refinement Specialist, for their kind and courteous guidance and advice on the series of tasks from application to contract in publishing this book, and Wiley for their guidance in publishing this book.