Practical ESD Protection Design E-Book

Albert Wang

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 721

Veröffentlichungsjahr: 2021

Beschreibung

An authoritative single-volume reference on the design and analysis of ESD protection for ICs Electrostatic discharge (ESD) is a major reliability challenge to semiconductors, integrated circuits (ICs), and microelectronic systems. On-chip ESD protection is a vital to any electronic products, such as smartphones, laptops, tablets, and other electronic devices. Practical ESD Protection Design provides comprehensive and systematic guidance on all major aspects of designs of on-chip ESD protection for integrated circuits (ICs). Written for students and practicing engineers alike, this one-stop resource covers essential theories, hands-on design skills, computer-aided design (CAD) methods, characterization and analysis techniques, and more on ESD protection designs. Detailed chapters examine an array of topics ranging from fundamental to advanced, including ESD phenomena, ESD failure analysis, ESD testing models, ESD protection devices and circuits, ESD design layout and technology effects, ESD design flows and co-design methods, ESD modelling and CAD techniques, and future ESD protection concepts. Based on the author's decades of design, research and teaching experiences, Practical ESD Protection Design: * Features numerous real-world ESD protection design examples * Emphasizes on ESD protection design techniques and procedures * Describes ESD-IC co-design methodology for high-performance mixed-signal ICs and broadband radio-frequency (RF) ICs * Discusses CAD-based ESD protection design optimization and prediction using both Technology and Electrical Computer-Aided Design (TCAD/ECAD) simulation * Addresses new ESD CAD algorithms and tools for full-chip ESD physical design verification * Explores the disruptive future outlook of ESD protection Practical ESD Protection Design is a valuable reference for industrial engineers and academic researchers in the field, and an excellent textbook for electronic engineering courses in semiconductor microelectronics and integrated circuit designs.

Leseprobe

Table of Contents

Cover

Title Page

Copyright

Author Biography

Preface

1 Why ESD?

1.1 A Historical Perspective

1.2 ESD and the Dangers

1.3 ESD Protection: The Principles

1.4 ESD Protection: More or Less?

1.5 ESD Protection: Evolution to Revolution

References

2 ESD Failure Analysis

2.1 ESD Failure Analysis

2.2 ESD FA Techniques

2.3 ESD Failure Signatures

2.4 ESD Soft Failures

2.5 ESD Failure Correlation

2.6 ESD Failure Models

References

3 ESD Test Models and Standards

3.1 ESD Origins

3.2 HBM Model

3.3 MM Model

3.4 CDM Model

3.5 IEC Model

3.6 TLP Model

3.7 Summary

References

4 ESD Protection Devices

4.1 On-Chip ESD Protection Mechanisms

4.2 Diode for ESD Protection

4.3 BJT for ESD Protection

4.4 MOSFET for ESD Protection

4.5 SCR for ESD Protection

4.6 Summary

References

5 ESD Protection Circuits

5.1 I/O ESD Protection

5.2 ESD Self-Protection

5.3 Low-Triggering ESD Protection Circuits

5.4 ESD Power Clamps

5.5 Summary

References

6 Full-Chip ESD Protection

6.1 Full-Chip ESD Protection Principles

6.2 ESD Protection Design Window

6.3 Advanced ESD Protection: More at Less

6.4 Full-Chip ESD Protection Schemes

6.5 No Universal ESD Protection Solution

References

7 Mixed-Signal and HV ESD Protection

7.1 ESD Protection for Mixed-Signal ICs

7.2 ESD Protection for Multiple-Voltages ICs

7.3 ESD Protection for High-Voltage ICs

7.4 Summary

References

8 TCAD-Based Mixed-Mode ESD Protection Designs

8.1 ESD Design Optimization and Prediction

8.2 TCAD-Based Mixed-Mode ESD Simulation-Design Methodology

8.3 Mixed-Mode ESD Simulation-Design Examples

8.4 Summary

References

9 RF ESD Protection

9.1 What Is Special for RF ESD Protection?

9.2 RF ESD Protection Characterization

9.3 Low-Parasitic ESD Protection Solutions

9.4 RF ESD Protection Design Example

9.5 Summary

References

10 ESD-RFIC Co-Design

10.1 ESD-IC Interactions

10.2 ESD-RFIC Co-Design

10.3 Summary

References

11 ESD Layout Designs

11.1 Layout is Critical to ESD Protection

11.2 Basic ESD Protection Layout

11.3 Advanced ESD Protection Layout

11.4 3D TCAD for ESD Layout Designs

11.5 Summary

References

12 ESD versus IC Technologies

12.1 IC Technologies and ESD Protection

12.2 Technology Affects ESD Design Window

12.3 Lowering ESD Protection for Advanced ICs?

12.4 Summary

References

13 ESD Circuit Simulation by SPICE

13.1 ESD Device Behavior Modeling

13.2 Full‐Chip ESD Circuit Simulation by SPICE

13.3 Summary

References

14 Emerging ESD Protection

14.1 Emerging ESD Protection Challenges

14.2 Dispensable ESD Protection

14.3 Field‐Programmable ESD Protection

14.4 Interposer/TSV‐Based ESD Protection

14.5 Summary

References

15 ESD CAD for Full‐Chip Design Verification

15.1 Full‐Chip ESD Design Verification

15.2 CAD Algorithms for ESD Design Verification

15.3 Full‐Chip ESD Design Verification Examples

15.4 Summary

References

16 New CDM ESD Protection

16.1 Misconception in CDM ESD Protection

16.2 Analyzing Pad‐Based CDM ESD Protection

16.3 Internally Distributed CDM ESD Protection

16.4 Summary

References

17 Future ESD Protection Outlook

17.1 The Fundamental ESD Protection Problem

17.2 Above‐IC Nano‐Crossbar Array ESD Switch

17.3 Graphene ESD Protection Switch

17.4 Graphene ESD Protection Interconnects

17.5 Future ESD Protection Outlook

17.6 Summary

References

Index

End User License Agreement

List of Tables

Chapter 1

Table 1.1 Triboelectric series.

Table 1.2 Common triboelectric generation at varying humidity related to ICs...

Chapter 3

Table 3.1 Triboelectricity generation in workplace.

Table 3.2 Method 3015.7 equivalent circuit Specs.

Table 3.3 Method 3015.7 waveform Specs.

Table 3.4 Method 3015.7 HBM ESDV classification.

Table 3.5 Waveform Specs by ANSI/ESDA/JEDEC JS‐001‐2017.

Table 3.6 ESD classification by ANSI/ESDA/JEDEC JS‐001‐2017.

Table 3.7 MM waveform Specs (Short/400 V) [12].

Table 3.8 Short‐circuit CDM ESD waveform specs per JESD22‐C101‐A (short‐wir...

Table 3.9 Short‐circuit CDM ESD waveform specs per ANSI/ESDA/JEDEC JS‐002‐2...

Table 3.10 ANSI/ESDA/JEDEC JS‐002‐2018 CDM ESDV classification.

Table 3.11 IEC discharge waveform specs (IEC 61000‐4‐2).

Table 3.12 Typical equivalent circuit parameters for different ESD test mod...

Chapter 8

Table 8.1 Comparison of key ESD Specs of ggNMOS and gcNMOS ESD Protection st...

Chapter 10

Table 10.1 Op Amp IC specs.

Table 10.2 Impacts of ESD protection on Op Amp Specs.

Table 10.3 Comparison of ESD-induced NF degradation of LNA.

Table 10.4 Measured NF for LNA design splits.

Chapter 11

Table 11.1 A summary for poly‐Si SCR ESD design splits.

Chapter 12

Table 12.1 Summary of technology scaling impact on P

+

/Nwell ESD diodes ...

Chapter 15

Table 15.1 Extracted ESD devices and ESD‐critical parameters.

Table 15.2 CMOS core BV.

List of Illustrations

Chapter 1

Figure 1.1 Elektron in Greek word means Amber that is beautiful both aesthet...

Figure 1.2 Benjamin Franklin's thought about electricity: (1) the lightning ...

Figure 1.3 J. J. Thomson discovered the electron in experiment to study “cat...

Figure 1.4 Thomas Edison debuted the first incandescent lightbulb on 21 Octo...

Figure 1.5 Hertz's first spark-gap radio transmitter, which can be called an...

Figure 1.6 The quantified triboelectric series. The error bar indicates the ...

Figure 1.7 Illustration of a typical ESD workstation providing an EPA area....

Figure 1.8 Commonly used ESD awareness symbols: (a) ESD common point ground ...

Figure 1.9 ESD protection in real life: (a) a house has a lightning rod syst...

Chapter 2

Figure 2.1 ESD failure analysis for a classic two-stage ESD protection circu...

Figure 2.2 Images for ESD damages under ESD zapping for the primary–secondar...

Figure 2.3 Improved layout design for the two-stage ESD protection circuit s...

Figure 2.4 Example for ESD damage in internal IC core circuit: D–S Si filame...

Figure 2.5 D/S contact (type ➀) and D–S Si filament (type ➁) CDM ESD damages...

Figure 2.6 Typical terminal-to-terminal Si filament ESD damages in a ggNMOS-...

Figure 2.7 A contact spiking ESD failure signature in a CMOS gate array circ...

Figure 2.8 Similar ESD failure signatures were observed in gate oxide of a d...

Figure 2.9 Different ESD zapping tests resulted in different ESD failure sig...

Figure 2.10 Evenly-distributed ESD-induced hot spots appear in the drain con...

Figure 2.11 ESD-induced metal extrusion defects in Al interconnects under HB...

Figure 2.12 ESD-induced various defects in Cu interconnects shows ESD failur...

Figure 2.13 HBM ESD-induced metal vaporization and electro-thermal migration...

Figure 2.14 Real-time EMMI imaging under DC stressing for (a) non-LDD ggNMOS...

Figure 2.15 FA analysis for 300-fin ggNFET ESD protection structures (a/b) m...

Figure 2.16 Optical microscopy and AFM images reveal the soft to hard ESD fa...

Figure 2.17 AFM images reveal ESD-induced soft defect in oxide sidewall in a...

Figure 2.18 SEM shows under-surface ESD defect in a P+/n-Well ESD protection...

Figure 2.19 ESD damages are observed for the 800-pin mixed-signal SoC in 45 ...

Figure 2.20 FA example for AlGaN/GaN HEMT devices by TLP stressing: (a) devi...

Figure 2.21 FA for HEMT-ii by on-the-fly monitoring reveals failure evolutio...

Figure 2.22 ESD FA analysis example for a SiC

n

MESFET with MESA isolation by...

Figure 2.23 ESD FA example for multiple-wall carbon nanotubes (MWCNTs) were ...

Figure 2.24 ESD FA analysis example for GaN-based LED by ESD zapping tests: ...

Figure 2.25 ESD FA example for poly-SiGe beam based RF MEMS structures by HB...

Figure 2.26 Soft failures were studied by measuring TDDB lifetime ...

Figure 2.27 ESD soft failure in ultrathin CMOS gate oxide films was studied ...

Figure 2.28 Failure signatures in an automotive IC (Device-1) by different E...

Figure 2.29 Same contact spiking defects observed in NMOS devices in 0.5 and...

Figure 2.30 Different ESD failure signatures are observed in a 0....

Figure 2.31 A parallelepiped-shaped heat source model assumed for an NMOS de...

Figure 2.32 Illustration for a four-segment ESD failure model.

Chapter 3

Figure 3.1 Original HBM test model per Method 3015.7: (a) equivalent circuit...

Figure 3.2 Illustration for HBM ESD waveforms: (a) HBM waveform variation pe...

Figure 3.3 A second‐order HBM ESD model equivalent circuit includes a parasi...

Figure 3.4 A fourth‐order HBM model equivalent circuit includes more parasit...

Figure 3.5 Illustration for HBM ESD waveforms per ANSI/ESDA/JEDEC JS‐001‐201...

Figure 3.6 A general equivalent circuit for MM ESD model.

Figure 3.7 A standard MM discharge waveform, under 400 V zapping at Short Wi...

Figure 3.8 Equivalent circuit component values can significantly affect the ...

Figure 3.9 CDM charging has two formats: (a) direct charging, e.g., contacti...

Figure 3.10 Illustration of a CDM ESD tester set‐up and its standard CDM dis...

Figure 3.11 A second‐order CDM ESD discharge model circuit where the ESDS DU...

Figure 3.12 ESD discharge waveforms produced by a CDM zapping tester (

C

ESD

 =...

Figure 3.13 A tester schematic for field‐induced CDM (FICDM) per ANSI/ESDA/J...

Figure 3.14 A typical CDM tester discharge waveform per ANSI/ESDA/JEDEC JS‐0...

Figure 3.15 Illustration of single CDM discharge procedures per ANSI/ESDA/JE...

Figure 3.16 Illustration of dual CDM discharge procedures per ANSI/ESDA/JEDE...

Figure 3.17 A simplified IEC ESD test model equivalent circuit. The parasiti...

Figure 3.18 Standard IEC ESD discharge waveform per IEC 61000‐4‐2.

Figure 3.19 Illustration of IEC testing set‐up for desk‐top EUT in laborator...

Figure 3.20 Illustration of IEC testing set‐up for floor‐standing EUT in lab...

Figure 3.21 A simplified circuit schematic for (a) a TLP testing set‐up, and...

Figure 3.22 A comparison of TLP and HBM pulse waveforms for ESD discharge eq...

Figure 3.23 Illustration of TLP pulse waveforms across a DUT stressed by a T...

Figure 3.24 Example of measured TLP‐produced square waveform (Green) that is...

Figure 3.25 Example for TLP‐measured transient ESD discharging

I

–

V

and

I

leak

Chapter 4

Figure 4.1 Concept of a shunt ESD switch method for on-chip ESD production: ...

Figure 4.2 Concept of a shunt-series ESD switch method for on-chip ESD produ...

Figure 4.3 Concept of a series ESD switch method for on-chip ESD production:...

Figure 4.4 Illustration of full-chip ESD protection scheme: multiple ESD pro...

Figure 4.5 Illustration of two typical

I

–

V

characteristics facilitating ESD ...

Figure 4.6 Concept of using filters or resonators for ESD protection: high-p...

Figure 4.7 Frequency spectrum comparison: ESD protection versus common wirel...

Figure 4.8 Concept of using single inductor filter for ESD protection.

Figure 4.9 Concept of using LC resonator for ESD protection.

Figure 4.10 Typical

I

–

V

characteristics for a diode can be described by piec...

Figure 4.11 Conceptual schematics for exemplar diode-based ESD protection sc...

Figure 4.12 Diode equivalent circuit models for ESD-induced parasitic capaci...

Figure 4.13 Operation of an intrinsic NPN BJT transistor.

Figure 4.14 Typical common-emitter (CE) BJT

I

–

V

characteristics in normal op...

Figure 4.15 Ebers–Moll model equivalent circuit for an NPN BJT.

Figure 4.16 Illustration for BJT-based ESD protection schemes with four simp...

Figure 4.17 Illustration of schematic and cross-section of NPN BJT for I/O-t...

Figure 4.18 Typical snapback ESD discharge

I

–

V

characteristic for a BJT ESD ...

Figure 4.19 BJT gain depends on biasing conditions and reduces at high curre...

Figure 4.20 An equivalent circuit models ESD-induced parasitic

C

ESD

for a BJ...

Figure 4.21 An equivalent circuit models ESD-induced noises for a BJT-based ...

Figure 4.22 Biasing condition and cross-section for an enhancement mode NMOS...

Figure 4.23 Typical common-source (CS) NMOSFET

I

–

V

characteristics in normal...

Figure 4.24 A large-signal equivalent circuit model for NMOS transistor.

Figure 4.25 Various I/O ESD protection schemes using ggNMOS and ggPMOS ESD p...

Figure 4.26 Illustration of ggNMOS ESD protection mechanism under PS ESD str...

Figure 4.27 Illustration of ggPMOS ESD protection mechanism under ND ESD str...

Figure 4.28 Illustration of an

incorrect

way of using ggNMOS ESD protection ...

Figure 4.29 A FOX-MOS ESD structure uses thick oxide as gate.

Figure 4.30 Simplified parasitic

C

ESD

equivalent circuit model for a ggNMOS ...

Figure 4.31 ESD-induced noise equivalent circuit model for a ggNMOS ESD prot...

Figure 4.32 A cross-section for a classic CMOS inverter shows a parasitic SC...

Figure 4.33 A generic SCR device and its equivalent circuit depict SCR opera...

Figure 4.34 Classic SCR

I

–

V

characteristics under positive and negative bias...

Figure 4.35 A simplified SCR ESD protection structure is a two-terminal SCR ...

Figure 4.36 Equivalent circuit models for a SCR ESD protection structure inc...

Figure 4.37 A simplified ESD-induced parasitic capacitance model for an SCR ...

Figure 4.38 A simplified noise equivalent circuit model for an SCR ESD prote...

Chapter 5

Figure 5.1 A two-stage primary-secondary ESD protection scheme uses a second...

Figure 5.2 A multiple-finger ggNMOS ESD protection structure is equivalent t...

Figure 5.3 ESD discharge

I

–

V

characteristics are critical to multiple-finger...

Figure 5.4 A conceptual schematic illustration for gcNMOS ESD protection str...

Figure 5.5 A cross-section view of gcNMOS ESD protection structure shows var...

Figure 5.6 Typical bell-shaped

I

sub

 ∼ 

V

G

characteristics of MOSFETs reported...

Figure 5.7 A conceptual BJT-based ESD protection sub-circuit for Input-to-GN...

Figure 5.8 Exemplar modified BJT-based ESD protection circuits feature varyi...

Figure 5.9 A complex BJT-based ESD protection circuit example utilizes a dio...

Figure 5.10 A cross-section view for an MVSCR ESD protection structure utili...

Figure 5.11 A primary-secondary output ESD protection scheme, where the pull...

Figure 5.12 A complete output ESD protection scheme uses various pull-up and...

Figure 5.13 A TGNMOS ESD protection scheme for output ESD protection using d...

Figure 5.14 A BJT ESD protection scheme for output pad requires careful desi...

Figure 5.15 ESD self-protection property of output buffer transistors may be...

Figure 5.16 A ggNMOS-triggered SCR (LVSCR) ESD protection structure reduces ...

Figure 5.17 A complementary gcMOS-triggered SCR ESD protection circuit, in n...

Figure 5.18 A low-triggering DTSCR ESD protection structure: (a) concept of ...

Figure 5.19 An exemplar DTSCR ESD protection structure uses a diode-string i...

Figure 5.20 Exemplar cross-section view for a forward diode-string triggered...

Figure 5.21 An alternative DTSCR ESD protection structure uses a diode-strin...

Figure 5.22 Exemplar cross-section view for a forward diode-string triggered...

Figure 5.23 Measured ESD discharging

I

–

V

curves for exemplar DTSCR ESD prote...

Figure 5.24 Schematic and equivalent circuit for a six-diode diode-string ES...

Figure 5.25 Cross-sectional view of a six-diode diode-string ESD power clamp...

Figure 5.26 A simplified equivalent circuit for deriving total ESD discharge...

Figure 5.27 Exemplar ESD power clamps using (a) ggNMOS and (b) two-stage ggN...

Figure 5.28 A exemplar ESD power clamp uses an NMOS-triggered SCR ESD protec...

Figure 5.29 (a) A non-snapback NMOS switch serves as an ESD power clamp for ...

Chapter 6

Figure 6.1 Concept of ESD Design Window suggests that ESD-critical parameter...

Figure 6.2 Complete on-chip ESD protection requires multiple single-polarity...

Figure 6.3 Conceptual ESD discharge

I

–

V

characteristics for ESD protection s...

Figure 6.4 A full-chip ESD protection example uses four ggMOS-SCR ESD protec...

Figure 6.5 A cross-sectional and schematic view for the novel dual-polarity ...

Figure 6.6 Illustration of the intrinsic N

1

P

2

N

3

P

4

N

5

unit of the novel dual-p...

Figure 6.7 A conceptual schematic for full-chip ESD protection scheme using ...

Figure 6.8 A cross-section view of the novel three-terminal multiple-polarit...

Figure 6.9 A conceptual full-chip ESD protection scheme using the multiple-p...

Figure 6.10 Equivalent circuit for the novel multiple-polarity ESD protectio...

Figure 6.11 An equivalent circuit schematic for an exemplar low-

V

t

1

multiple...

Figure 6.12 Illustration of a pad-clamp whole-chip ESD protection scheme usi...

Figure 6.13 Illustration for a whole-chip ESD protection scheme using a glob...

Chapter 7

Figure 7.1 Meeting the dynamic ESD Design Window requirement becomes challen...

Figure 7.2 Exemplar mixed-signal SoC – a 5G smartphone chipset contains digi...

Figure 7.3 A exemplar mixed-signal multiple-domain SoC architecture includes...

Figure 7.4 Exemplar ESD-protected LED-based VLC optical wireless communicati...

Figure 7.5 Full-chip ESD protection scheme contains power clamp between all ...

Figure 7.6 Different functional and power domains on a complex mixed-signal ...

Figure 7.7 Inter-domain rail-to-rail ESD clamps are often inserted between d...

Figure 7.8 It is understood that using inter-domain rail-to-rail ESD clamps ...

Figure 7.9 In Case-2, the

V

SS1

pad is grounded during CDM zapping test, and ...

Figure 7.10 In Case-3, the Out-2 pad is grounded during CDM zapping test, an...

Figure 7.11 Exemplar solution to the internal CDM ESD failure problem utiliz...

Figure 7.12 A exemplar schematic for a multiple-function/power-domain HV AMX...

Figure 7.13 A conceptual ESD discharge

I

–

V

curve for the anti-parallel diode...

Figure 7.14 A conceptual ESD discharge

I

–

V

characteristic for the asymmetric...

Figure 7.15 A conceptual ESD discharge

I

–

V

curve for the Zener diode used to...

Figure 7.16 A conceptual ESD discharge

I

–

V

curve for the symmetric dual-dire...

Figure 7.17 In concept, ESD protection utilizes a controlled low-

R

ESD switc...

Chapter 8

Figure 8.1 Traditional trial-&-error ESD protection design flows are experie...

Figure 8.2 Illustration of an over-simplified ESD heating source of an NMOSF...

Figure 8.3 A framework for TCAD-based mixed-mode ESD protection simulation-d...

Figure 8.4 A detailed TCAD-based mixed-mode ESD simulation-design flow.

Figure 8.5 An exemplar TCAD-based mixed-mode ESD simulation schematic for HB...

Figure 8.6 A typical ESD simulation calibration framework.

Figure 8.7 Examplar ESD test pattern for TCAD ESD simulation calibration: (a...

Figure 8.8 A cross-section for a TCAD-created ggNMOS ESD protection device i...

Figure 8.9 DC sweeping ESD discharge

I

–

V

curve by TCAD ESD simulation shows ...

Figure 8.10 Transient ESD discharging

I

–

V

curve of a ggNMOS ESD protection d...

Figure 8.11 Transient ESD discharging

V

–

t

curve of a ggNMOS ESD protection d...

Figure 8.12 Transient ESD discharge

T

max

–

I

characteristics of a ggNMOS ESD p...

Figure 8.13 Transient ESD discharge

T

max

–

t

curve of a ggNMOS ESD protection ...

Figure 8.14 Transient ESD simulation for a ggNMOS ESD protection structure s...

Figure 8.15 Transient

T

max

 ∼ 

I

characteristics for an under-sized ggNMOS ESD...

Figure 8.16 Maximum lattice temperature map by transient TCAD ESD simulation...

Figure 8.17 An alternative view of transient

T

max

contour of an under-design...

Figure 8.18 Transient ESD discharge

I

–

V

curve for a ggNMOS device by TCAD ES...

Figure 8.19 Transient ESD discharge

V

–

t

curve for a ggNMOS device by TCAD ES...

Figure 8.20 Transient ESD discharging

I

–

V

curve for a gcNMOS device by TCAD ...

Figure 8.21 Transient ESD discharging

V

–

t

curve for a gcNMOS device by TCAD ...

Figure 8.22 Transient ESD discharge

V

G

–

t

curve for a gcNMOS device by TCAD E...

Figure 8.23 Schematic for a gcNMOS power clamp to protect an output block (a...

Figure 8.24 Simulated transient ESD discharge

V

D

3

–

t

characteristics for gcNM...

Figure 8.25 Transient ESD simulation reveals lattice temperature for all dev...

Figure 8.26 A 30 V BCD process establishes the HV ESD Design Window of (35, ...

Figure 8.27 A cross-section view of HVggNMOS ESD protection structure in a B...

Figure 8.28 Evolutional ESD discharge flows of a HVggNMOS ESD protection str...

Figure 8.29 Measured ESD discharging

I

–

V

characteristics for the initial HVg...

Figure 8.30 Simulated ESD discharging

I

–

V

curve for the initial HVggNMOS ESD...

Figure 8.31 Evolution in electric field density of the HVggNMOS by TCAD ESD ...

Figure 8.32 Simulated ESD discharging

I

–

V

curve for HVggNMOS ESD protection ...

Figure 8.33 Simulated ESD discharging

I

–

V

curve for HVggNMOS ESD protection ...

Figure 8.34 Simulated ESD discharging

I

–

V

curve for HVggNMOS ESD protection ...

Figure 8.35 TCAD ESD simulation assists to tune the ESD discharging

I

–

V

curv...

Figure 8.36 A cross-section (

X

–

Y

) view of P

+

/Nwell ESD protection diode ...

Figure 8.37 A P

+

/Nwell ESD protection diode created by true 3D TCAD proc...

Figure 8.38 Comparison of transient ESD discharging

I

–

V

and

T

max

–

t

character...

Figure 8.39 Temperature map for the PPNW ESD diode by 2D TCAD simulation: (a...

Figure 8.40 Temperature map of the PPNW ESD diode by 3D TCAD simulation: (a)...

Figure 8.41 Four layout design splits of 3D PPNW ESD diodes by 3D TCAD simul...

Figure 8.42 Split-1 and Split-2 comparison of PPNW ESD didoes by 3D TCAD und...

Figure 8.43 Split-1 versus Split-3 ESD discharge comparison by 3D TCAD under...

Figure 8.44 Split-1 versus Split-4 ESD discharge comparison by 3D TCAD under...

Figure 8.45 Top view temperature contour comparison for PPNW ESD diodes by 3...

Figure 8.46 Original HBM ESD pulse waveform per

Method 3015.7, MIL-STD-883E

...

Figure 8.47 Correlating TLP and HBM waveforms in ESD testing for equivalent ...

Figure 8.48 TLP ESD testing applies a TLP pulse train across a DUT: (a) the ...

Figure 8.49 Cross-section for a STI ESD diode made in a 28 nm CMOS by TCAD s...

Figure 8.50 A TCAD mixed-mode ESD simulation set-up uses multiple different ...

Figure 8.51 Transient ESD discharging

I

–

V

curves for a STI ESD diode fabrica...

Figure 8.52 Transient incident ESD

I

–

t

curve (blue) and ESD-induced

T

max

–

t

c...

Chapter 9

Figure 9.1 Sample TLP-measured triggering voltage

V

t

1

data for commonly used...

Figure 9.2 A ggNMOS ESD protection device relies on the ESD-induced Drain av...

Figure 9.3 An SCR ESD protection device relies on the ESD-induced Pwell/N-su...

Figure 9.4 Measured data show that the

-induced displacement current plays ...

Figure 9.5 Illustration of ESD-induced IC noise degradation in two possible ...

Figure 9.6 Cross-section view for de-embedded ESD test pattern pair for accu...

Figure 9.7 Equivalent two-port network models for de-embedded ESD

C

ESD

test ...

Figure 9.8 Measured

C

ESD

across a 9 GHz bandwidth for various 2 kV ESD prote...

Figure 9.9 Measured

C

ESD

across a 9 GHz bandwidth for various 2 kV ESD prote...

Figure 9.10 Measured

C

ESD

at 2.4 GHz for various 2 kV ESD protection structu...

Figure 9.11 Layout sizes are different for various 2 kV ESD protection struc...

Figure 9.12 F-factors extracted for various 2 kV ESD protection structures i...

Figure 9.13 Measured

C

ESD

for STI P

+

ESD protection diodes in the I/O pr...

Figure 9.14 Measured

C

ESD

for single-diode-triggered DTSCR ESD protection st...

Figure 9.15 A comparison illustration for various on-chip ESD protection sch...

Figure 9.16 A cross-section view for a dSCR ESD protection structure impleme...

Figure 9.17 DC ESD discharging

I

–

V

curve for the dSCR ESD protection structu...

Figure 9.18 Transient ESD discharging

I

–

V

curve in one direction for the dua...

Figure 9.19 Measured symmetric ESD discharge

I

–

V

curve by a Curve Tracer mat...

Figure 9.20 Measured transient ESD discharge

I

–

V

curve (blue), in one direct...

Chapter 10

Figure 10.1 The complementary ggNMOS and ggPMOS ESD protection transistors c...

Figure 10.2 This design uses a CMOS power clamp for supply bus ESD protectio...

Figure 10.3 This example uses a gcNMOS power clamp for supply bus ESD protec...

Figure 10.4 TCAD ESD simulation for the circuit in Figure 10.3 shows that, u...

Figure 10.5 TCAD ESD simulation for the circuit in Figure 10.3 shows that, u...

Figure 10.6 General principle in reducing ESD impacts on RF ICs: (a) & (d) u...

Figure 10.7 A schematic for a low-power Op Amp designed in a 180 nm BiCMOS t...

Figure 10.8 The phase Bode plot for the Op Amp ICs with no ESD protection, a...

Figure 10.9 The settling time for the Op Amp ICs with no ESD protection, and...

Figure 10.10 The slew rate for the Op Amp ICs with no ESD protection, and gg...

Figure 10.11 Schematic for a 2.4 GHz LNA circuit with ESD protection at the ...

Figure 10.12 Simulation for the ESD-protected 2.4 GHz LNA shows strong noise...

Figure 10.13 A 2KV ESD protected dual-band 2.4 5.5GHz LNA circuit implement...

Figure 10.14 Measured NF behaviors for the LNA circuits without and with ESD...

Figure 10.15 Illustration of the ESD-RFIC co-design flow: (a) normal RF IC d...

Figure 10.16 Schematic (a) and die photo (b) of a 5 GHz LNA implemented in a...

Figure 10.17 Simulation using foundry-provided ESD device model incorrectly ...

Figure 10.18 Simulation using foundry-provided ESD device model incorrectly ...

Figure 10.19 Measured gain curves show significant degradation for LNA with ...

Figure 10.20 Measured NF curves show significant degradation for LNA with a ...

Figure 10.21 ESD-induced impacts on gain of LNA with various ESD protection ...

Figure 10.22 ESD-induced impacts on NF of LNA with various ESD protection st...

Figure 10.23 ESD-induced impacts on input reflection loss of LNA with variou...

Figure 10.24 Design of a SP10T T/R switch in 180 nm SOI CMOS: (a) quad-band ...

Figure 10.25 Evaluation of voltage distribution across MOSFETs in one 8-FET ...

Figure 10.26 Measured IL for the ESD-protected SP10T switch in GSM

R

x

mode u...

Chapter 11

Figure 11.1 A classic vertical (bottom discharging) N

+

/PW diode ESD prot...

Figure 11.2 A classic lateral (sidewall discharging) NW/PW sidewall diode ES...

Figure 11.3 A gated ESD diode versus a STI ESD diode made in a 28 nm CMOS: (...

Figure 11.4 A classic vertical NPN ESD protection device: (a) cross‐section,...

Figure 11.5 A classic ggNMOS ESD protection device: (a) cross‐section, and (...

Figure 11.6 A classic SCR ESD protection device has high

V

t

1

due to high Pwe...

Figure 11.7 A MVSCR ESD protection device has a N

+

plug and relies on N

+

...

Figure 11.8 An LVSCR ESD protection device relies on an embedded NMOS to ach...

Figure 11.9 An example of LV SCR device fabricated in a 28 nm CMOS shows imp...

Figure 11.10 A low‐capacitance Poly‐Si SCR ESD protection structure implemen...

Figure 11.11 A comparison for measured ESD discharging

I–V

curves for ...

Figure 11.12 A comparison for measured ESD discharge

I

–

V

curves for Poly‐Si ...

Figure 11.13 A comparison for measured parasitic ESD‐induced

C

ESD

for Poly‐S...

Figure 11.14 A classic ggNMOS ESD protection requires minimum SGCS and large...

Figure 11.15 Transient TCAD ESD simulation shows an ESD‐induced hot spot at ...

Figure 11.16 Transient TCAD ESD simulation, using a combined Si‐metal ESD si...

Figure 11.17 Illustration for a preferred BSGD‐DGSBSGD‐DGSB layout pattern f...

Figure 11.18 Two different ESD metal routing scenarios for a ggNMOS ESD prot...

Figure 11.19 An ideal straight ggNMOS ESD metal routhing ensures smooth ESD ...

Figure 11.20 Poor contact placement in combination of an anti‐parallel metal...

Figure 11.21 Careless contact and via placement introduces unwanted vertical...

Figure 11.22 A waffle layout design of NMOS ESD protection structure contain...

Figure 11.23 A dSCR cell array ESD proteciton structure in BiCMOS: (a) one‐c...

Figure 11.24 A square‐pad based three‐terminal mutiple‐polarity SCR ESD prot...

Figure 11.25 A circular‐pad based three‐terminal multiple‐polarity SCR ESD p...

Figure 11.26 Illustration of a pad‐oriented complementary ggNMOS/ggPMOS ESD ...

Figure 11.27 Illustration of a pad‐oriented ggNMOS‐triggered SCR (LVSCR) ESD...

Figure 11.28 A 3 × 3 Sudoku‐SCR ESD array by 3D TCAD wher...

Figure 11.29 3D transient ESD simulation for the 3 × 3 Sudoku...

Figure 11.30 A 3 × 3 Sudoku‐DTSCR ESD array by 3D TCAD ...

Figure 11.31 3D transient ESD simulation for the 3 × 3 Sudoku...

Figure 11.32 TLP‐measured ESD discharging

I

–

V

curves for Sudoku and finger E...

Figure 11.33 VFTLP‐measured ESD discharging

I

–

V

curves for Sudoku ESD arrays...

Figure 11.34 Layout of

N × N

scalable Sudoku ESD arrays con...

Figure 11.35 Normalized ESD area efficiency for large Sudoku DTSCR ESD array...

Chapter 12

Figure 12.1 Comparison for maximum sustainable current density (

J

C

) for Al a...

Figure 12.2 An LDD‐blocking mask is commonly used to block LDD implant in th...

Figure 12.3 Illustration of silicidation impact on MOSFET ESD protection dev...

Figure 12.4 A ggNMOS ESD protection device made in SOI CMOS removes the unde...

Figure 12.5 Illustration of a ggNMOE ESD protection device made in SOI CMOS:...

Figure 12.6 Various diode ESD protection devices in SOI CMOS: (a) a double‐d...

Figure 12.7 A low‐capacitance Poly‐Si SCR ESD protection structure implement...

Figure 12.8 A SiGe‐based ggNMOS ESD protection structure features a thin bur...

Figure 12.9 An ESD Design Window can change as per technologies and ICs, whi...

Chapter 13

Figure 13.1 A flowchart for the scalable ESD device behavior modeling method...

Figure 13.2 Exemplar N

+

/Pwell ESD protection diodes in forward conductio...

Figure 13.3 A two‐diode‐triggered DTSCR ESD protection structure in CMOS: (a...

Figure 13.4 Measured

I

t

2

(a) and

R

ON

(b) for a sample gated N

+

/Pwell ESD...

Figure 13.5 The TLP‐measured ESD discharging

I

–

V

curve for an exemplar N

+

...

Figure 13.6 The TLP‐measured snapback ESD discharging

I

–

V

curve for an exemp...

Figure 13.7 A flowchart of full‐chip ESD protection circuit design simulatio...

Figure 13.8 A simplified functional diagram for the input buffer IC core wit...

Figure 13.9 Layout of the IC core from which the ESD metal interconnects res...

Figure 13.10 Measured ESD discharge

I

–

V

curves by TLP for sample ESD metal i...

Figure 13.11 Simulated transient node voltages for the ESD‐protected input b...

Figure 13.12 Simulated branch currents (Left axis) and core circuit transist...

Figure 13.13 EMMI image under HBM ESD zapping shows a hot spot at the PU‐ESD...

Figure 13.14 A functional schematic for the PRBS IC core using anti‐parallel...

Figure 13.15 Two exemplar whole‐chip ESD zapping simulation cases: (a) posit...

Figure 13.16 Simulated transient ESD discharging behaviors for two ESD zappi...

Chapter 14

Figure 14.1 A functional diagram for ultrahigh‐speed IC using fuse‐based fie...

Figure 14.2 Simplified schematics for the input and output circuit blocks of...

Figure 14.3 Layout of the high‐speed transceiver link IC using fuse‐based di...

Figure 14.4 BEOL metal wires fabricated in a 28 nm 1P10M CMOS are measured b...

Figure 14.5 Measured output return loss for the high‐speed IC fabricated in ...

Figure 14.6 A Smartphone multiple‐chip platform contains ESD‐protected IC di...

Figure 14.7 Concept of programmable NC‐QD ESD protection structure uses a tu...

Figure 14.8 NC‐QD ESD triggering programming and on‐chip ESD protection sche...

Figure 14.9 TLP‐measured ESD discharge

I

–

V

curves for sample NC‐QD ESD prote...

Figure 14.10 Conceptual SONOS ESD protection device shows

V

t

1

programming me...

Figure 14.11 TLP‐measured ESD discharge

I

–

V

curves for a sample SONOS ESD pr...

Figure 14.12 Traditional in‐die/in‐plane on‐chip ESD protection integrates v...

Figure 14.13 Illustration of interposer‐based ESD protection scheme where th...

Figure 14.14 Illustration of TSV‐based ESD protection scheme that places var...

Figure 14.15 TCAD ESD simulation confirms ESD discharging function of a prot...

Figure 14.16 In a traditional in‐plane STI ESD protection diode, though the ...

Figure 14.17 A prototype in‐TSV poly‐Si/Si ESD protection diode fabricated i...

Figure 14.18 TLP‐measured ESD discharging

I

–

V

curves for the prototype in‐TS...

Chapter 15

Figure 15.1 Comparing common IC design flow with typical ESD protection desi...

Figure 15.2 A diagram for ESD‐function‐based smart parametric ESD checking m...

Figure 15.3 MG description for an intentional ggNMOS ESD protection device....

Figure 15.4 MG description for an intentional SCR ESD protection structure: ...

Figure 15.5 A conceptual on‐chip ESD protection circuit shows multiple ESD d...

Figure 15.6 A exemplar on‐chip ESD protection scheme uses a complementary gg...

Figure 15.7 Illustration of a weighted graph for the ESD protection circuit ...

Figure 15.8 An IC circuit designed in a 0.35 μm BiCMOS conta...

Figure 15.9 Layout view of ESD extraction outcomes for the IC shown in Figur...

Figure 15.10 SmartESD allows full‐chip ESD protection circuit design physica...

Figure 15.11 (a) Shown in an ESD Design Window, an ESD protection device may...

Figure 15.12 Schematic for an IC chip example designed in 28 nm CMOS feature...

Figure 15.13 Example of extracting any ESD‐like devices and their ESD‐critic...

Figure 15.14 Case‐1 ESD zapping scenario: in a positive IO2‐to‐IO1 ESD stres...

Figure 15.15 Case‐2 ESD zapping scenario: in a positive IO1‐to‐IO2 ESD stres...

Figure 15.16 Case‐1 ESD zapping scenario: in a positive IO2‐to‐IO1 ESD stres...

Chapter 16

Figure 16.1 Standard ESD pulse waveforms: (a) HBM ESD model, and (b) CDM ESD...

Figure 16.2 Classic pad‐based ESD protection method relies on discharging th...

Figure 16.3 The industrial standard FICDM ESD testing set‐up starts with an ...

Figure 16.4 CDM ESD failure can occur at both die and package levels: (a) a ...

Figure 16.5 Classic pad‐based CDM ESD protection method relies on the global...

Figure 16.6 Certain high‐speed and high‐frequency RF signal I/O pads do not ...

Figure 16.7 Illustration of a mixed‐signal IC chip may have large amount of ...

Figure 16.8 Induced electrostatic charges may be stored locally within a lar...

Figure 16.9 A three‐stage oscillator IC designed in 45 nm SOI CMOS: (a) cont...

Figure 16.10 Lumped circuit model for standard FICDM tester where CDM‐induce...

Figure 16.11 Improved pseudo‐distributed charge distribution model for FICDM...

Figure 16.12 Scenario‐1: Illustration of “from‐External‐to‐Internal” dischar...

Figure 16.13 Scenario‐1:

V

DD

‐to‐

V

SS

CDM ESD zapping case with a CDM ESD puls...

Figure 16.14 Scenario‐1: Transient

V

GS

and

V

GD

behaviors for PM1 under

V

DD

‐t...

Figure 16.15 Scenario‐1: transient CDM ESD discharging behaviors under 50 V

Figure 16.16 Scenario‐2: The CDM ESD protection simulation deck using the ps...

Figure 16.17 Scenario‐2:

V

DD

‐pad CDM ESD zapping case for a “from‐Internal‐t...

Figure 16.18 Scenario‐2: Transient

V

GS

and

V

GD

behaviors for PM1 when zappin...

Figure 16.19 Scenario‐2: Transient CDM ESD discharge behaviors under 50 V CD...

Figure 16.20 Scenario‐3: true “Internal‐oriented” CDM ESD zapping is a “from...

Figure 16.21 Scenario‐3: Transient

V

GS

behaviors for (a) PM1 and (b) NM9 whe...

Figure 16.22 Conceptual illustration of the nonpad‐based internally distribu...

Figure 16.23 The internally distributed CDM ESD protection can be realized u...

Figure 16.24 Split‐1: Functional diagram for a three‐stage oscillator IC cor...

Figure 16.25 Split‐2: The same three‐stage oscillator IC core is protected b...

Figure 16.26 Transient

V

GS

and

V

GD

behaviors for PM1 comparison: (a) Split‐1...

Figure 16.27 The same three‐stage oscillator IC core with internally distrib...

Figure 16.28 VFTLP testing for the internal CDM ESD protection didoes inside...

Chapter 17

Figure 17.1 Commonly used in‐Si PN‐based ESD protection structures include (...

Figure 17.2 Classic pad‐based full‐chip ESD protection method requires large...

Figure 17.3 An ideal ESD switch of any kinds may serve as a good ESD protect...

Figure 17.4 Illustration of the phase‐changing nano‐crossbar array ESD prote...

Figure 17.5 A

dispersed local ESD tunneling model

explains the ultrafast ESD...

Figure 17.6 TLP‐measured ESD discharging

I

–

V

curve for a sample single‐node ...

Figure 17.7 VFTLP‐measured ESD discharging

I

–

V

curve for a sample single‐nod...

Figure 17.8 TLP‐measured ESD discharging

I

–

V

curve for a sample single‐node ...

Figure 17.9 TLP‐measured ESD discharging

I

–

V

...

Figure 17.10 Measurement shows ultralow leakage currents of the nano‐crossba...

Figure 17.11 Measurement shows that the critical ESD triggering voltage can ...

Figure 17.12 TLP testing shows different

V

t

1

and

V

h

for prototype single‐nod...

Figure 17.13 Illustration for using the symmetric dual‐polarity nano‐crossba...

Figure 17.14 The concept of above‐IC graphene gNEMS ESD switch structure, it...

Figure 17.15 DC‐sweeping test shows switching effect of the prototype gNEMS ...

Figure 17.16 TLP measurement of a sample gNEMS device (

d

 ...

Figure 17.17 TLP measurement shows adjustable ESD

V

t1

values for prototype g...

Figure 17.18 Illustration of using graphene wires as ESD interconnects on a ...

Figure 17.19 Measured ESD discharging

I

–

V

curve for a sample GR wire (

L

 = 12...

Figure 17.20 Measured ESD discharging

I

–

V

curve for a sample GR wire (

L

 = 12...

Figure 17.21 Measured ESD failure threshold voltage and current density for ...

Figure 17.22 Measured ESD failure threshold current for GR wire samples of v...

Figure 17.23 Measured ESD failure threshold current density for GR wire samp...

Figure 17.24 Measured ESD failure threshold current for GR wire samples of v...

Figure 17.25 An outlook for future on‐chip ESD protection: ideal ESD switche...

Guide

Cover

Table of Contents

Title Page

Copyright

Author Biography

Preface

Begin Reading

Index

End User License Agreement

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IEEE Press

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Editor in Chief

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Ahmet Murat Tekalp

Practical ESD Protection Design

Albert Wang

University of California

Copyright © 2022 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.Published simultaneously in Canada.

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Library of Congress Cataloging-in-Publication Data is applied forHardback: 9781119850403

Cover Design: WileyCover Image: © Albert Wang

Author Biography

Professor Albert Wang

Dept. of Electrical and Computer Engineering

University of California, Riverside, USA

After working in the Silicon Valley as an IC design engineer, Wang joined the academia and, currently, is a professor of Electrical and Computer Engineering at the University of California, Riverside, California, USA. His research covers electron devices, analog/mixed-signal (AMX) and RF ICs, design-for-reliability, 3D heterogeneous integration, emerging nanodevices and circuits, and visible light communication systems. His research records include two books, about 300+ peer-reviewed papers, and 16 US patents. His editorial board services include IEEE Journal of Electron Devices Society, IEEE Transactions on Circuits and Systems I, IEEE Electron Device Letters, IEEE Transactions on Circuits and Systems II, IEEE Transactions on Electron Devices, IEEE Journal of Solid-State Circuits, IEEE Transactions on Device and Materials Reliability, and Journal of Engineering. He has been IEEE Distinguished Lecturer for IEEE Electron Devices Society, IEEE Circuits and Systems Society, and IEEE Solid-State Circuits Society. He was president of IEEE Electron Devices Society. He served as a Program Director at the National Science Foundation, USA. He is a Fellow of National Academy of Inventors, USA, and an IEEE Fellow.

Preface

The birth of Germanium (Ge) transistor in 1947, followed by the inventions of integrated circuits (ICs) in Ge and Silicon (Si) in 1958 and 1959, respectively, and particularly the advent of Si complementary metal-oxide-semiconductor (CMOS) IC technology in 1963, led to the prosperity of semiconductor microelectronics, which have forever changed the human society. Semiconductors and ICs laid the foundation of the information technology (IT) era where everything relies on ICs, from internet to internet of everything (IoET), from smartphones to tablets, and from autonomous driving to artificial intelligence (AI). ICs are truly everyday commodity now. Like other products, Performance and Reliability are the two cornerstone attributes of ICs. Electrostatic discharge (ESD) is a daily phenomenon that can cause damages to ICs. ESD failure is a major IC reliability problem ever since IC was born. On-chip ESD protection is therefore required for all ICs, as well as all electronics products. For the microelectronics industry, ICs are sold for monies due to the performance, however, ICs could not be sold without adequate on-chip ESD protection. For consumers, IC performance makes your smartphone powerful and enjoyable, however, one would kill a touch phone instantly if no ESD protection provided for IC chips. Generally, as IC technologies continue to advance into the nanometer domain, while IC performance and complexity increase rapidly, on-chip ESD protection design is becoming extremely more challenging today. How to conduct practical ESD protection designs for ICs is the scope of this book. Developed as a professional reference for IC design engineers and a textbook for upper-level students majoring in microelectronics, this book teaches both fundamentals and practical skills of on-chip ESD protection designs. All design examples discussed in this book are outcomes of our research. The author is therefore very grateful to his graduate students who contributed to the relevant research.

University of California

June 2021

Albert Wang

1Why ESD?

1.1 A Historical Perspective

Sure, this book means to discuss about electrostatic discharge (ESD) protection designs for integrated circuits (ICs). Yet nothing would prohibit our free minds from wandering around a bit before the show starts.

Imagine a world without electricity? The answer is no-brainer – impossible and scary!

To solve any problem, it is important to know where does it come from. Human curiosity in electricity dates back to our ancient ancestor era. Let us take a flash cyber-trip traveling through the time tunnel back to the ancient past. Around 600 BC, the Greek scientific philosopher, Thales of Miletus, discovered that a piece of amber rubbed with fur can magically attract light things, such as leaves, ash, or dust, because the amber was considered to have gained static charges, or, electrostatic charge as we call it these days. This amber effect is what is called static electricity today. Indeed, the loveliness of amber goes well beyond its natural beauty as shown in Figure 1.1. In fact, the English word electron came from the Greek word ēlektron for amber. Later, William Gilbert conducted serious studies on the attraction associated with rubbing materials, such as amber, and named it electric attraction, which led to the publication of DeMagnete in 1600 [1]. The word electricity was derived subsequently. The two types of electricity, i.e., vitreous (glass) and resinous (amber) was documented by Charles François de Cisternay DuFay in 1733 [2]. In 1751, Benjamin Franklin gave the terms of “positive” and “negative” for the two types of electrostatic charges in his publication of “Experiments and Observations on Electricity” [3], albeit a reverse definition might have made the life of college freshman students a little easier in understanding the current flowing direction versus the electron flowing direction. Obviously, when Franklin enjoyed his leisure time flying a kite, as shown in Figure 1.2, his brain never stopped roaming in the scientific wonderland. During 1800s, it became evident that electric charge may not be further divided, and Johnstone Stoney gave it the name “electron.” Later, Joseph John Thomson's experiments led to the conclusion of the existence of light particles carrying negative charge, and the word “electron” was used for it in 1897. The hard-working Thomson (Figure 1.3) was rewarded with the Nobel Prize in Physics in 1906 “in recognition of the great merits of his theoretical and experimental investigations on the conduction of electricity by gases.”

The magic charges have brought in unlimited amount of amazing applications, which have dramatically changed our life today. In a conductor, electric charges can move freely to form the electric current, which fire up an electric lightbulb and light up our life, mostly thanks to Humphry Davy who invented the first electric light in 1809 and Thomas Edison who demonstrated the first carbon filament bulb in 1897, as shown in Figure 1.4. Equally amazing and important are the electric charges at rest, i.e., static charges or electrostatic charges, which when discharge through an air gap, being one version of the ESD phenomena, will produce electromagnetic waves that eventually led to radio-frequency (RF) wireless communications. The ESD-based radio waves were first observed by Heinrich Rudolf Hertz in experiments conducted during 1886–1889 using amazingly simple spark-gap radio transmitter as shown in Figure 1.5[4]. At the time, Hertz did not realize the importance of his spark-gap radio wave experiments. In his own words, Hertz said it's of no use whatsoever and describes his work was just an experiment that proves Maestro Maxwell was right. As Hertz stated, we just have these mysterious electromagnetic waves that we cannot see with the naked eye, but they are there, his experiments proved that the airborne electromagnetic waves, initially called Hertzian waves and later named radio waves, exist as predicted by Maxwell.

Figure 1.1 Elektron in Greek word means Amber that is beautiful both aesthetically and scientifically.

(Courtesy of Custom Crystal.)

Figure 1.2 Benjamin Franklin's thought about electricity: (1) the lightning is electricity; (2) the two types of electrical charge are positive (vitreous) and negative (resinous).

(Courtesy of Chris Wang.)

Figure 1.3 J. J. Thomson discovered the electron in experiment to study “cathode rays” in 1897. He found that cathode rays consist of charged particles (electrons) that can conduct electricity.

(Courtesy of Cavendish Laboratory, University of Cambridge.)

Figure 1.4 Thomas Edison debuted the first incandescent lightbulb on 21 October 1897, which burned for about 13 hours.

(Courtesy of ThoughtCo.)

Figure 1.5 Hertz's first spark-gap radio transmitter, which can be called an ESD discharging device, is a capacitor-type dipole resonator comprising a pair of 1-m copper wires separated by a spark gap of about 7.5 mm. When a high voltage is applied through an inductor coil, the spark gap fires up the air and generates standing waves of roughly 50 MHz.

(Heinrich Rudolf Hertz/Wikipedia Commons/Public domain.)

1.2 ESD and the Dangers

While Hertz's spark-gap transmitter may be regarded as an original ESD discharging device that is useful, the ESD phenomena that we are concerned about today are more harmful than useful, which is the topic of this book.

Electric charge is a fundamental physical property of a matter, which makes it feel a force in an electromagnetic field. There are two types of electric charges. Per Franklin's convention, the electric charges gained by a glass rod rubbing a silk cloth are positive charges (vitreous), while the electric charges obtained by a piece of amber rubbed by a piece of fur are negative charges (resinous). Charge is quantized, meaning a charge carrier can only contain integer number of elementary charges. The SI unit for charge is Coulomb. An elementary charge (denoted as e) is indivisible. Elementary charge is a fundamental physical constant given as e = 1.602 176 634 × 10−19 C exactly [5]. One electron has one charge of –e.

Electric charge experiences a force through an electrostatic field. In modern physics, there exist four fundamental forces: weak force, strong force, electromagnetic force, and gravitational force. Weak force and strong force apply in “short” distance (microscale), while electromagnetic and gravitational forces act in “long” distance (macroscale). These fundamental forces, also referred to as fundamental interactions, can be mathematically described as a field. Electromagnetic force has two components: the electrostatic force that applies to electrically charged particles at rest, and the combined electric and magnetic forces that act on charged particles in motion. Due to the electrostatic force, like charges repel each other, while unlike charges attract each other. The electrostatic force acting on charges follows the Coulomb's Law as depicted below

(1.1)

where F is the Coulomb's Force, Q1 and Q2 are the amount of electrostatic charges contained by the two charge-carrying objects involved, r is the distance in between, and κ is a constant. Therefore, it requires certain amount of energy, defined as work, to move a charge in an electric field, which is characterized by the electrostatic potential at related points in the electric field.

Electrostatic charges are created when two objects, at least one of them has to be an electrical insulator or of high electrical resistivity in nature, are brought into contact and then separate from each other. Static electricity reflects an imbalance of electric charges (net positive or negative) inside a charged object. In physics, an isolated system follows the Law of Conservation of Charge, which states that the net charges, the difference of positive and negative charges, are preserved in the universe. Charge conservation does not prohibit static charges from being generated or destroyed. But any gain in charges somewhere at a time will accompany with the loss of the same amount of charges somewhere else. Static charges are associated with electric charging and discharging for an object. Electric charging puts static charges into an object, while electric discharging removes static charges from an object. Electric charging and discharging are two opposite phenomena associated with static charges, which involve separation and neutralization of positive and negative charges of materials. Electric charging leads to static electricity. Static charge generation requires separation of positive and negative charges through electric charging procedure. Normally, materials are electrically neutral because the atoms have same number of positive and negative charges. When two objects are in contact, electrons may move in between, which causes imbalance of positive or negative charges within each object. Then, when the two objects are separated thereafter, they may retain the charge imbalance, i.e., containing net positive or negative charges. This completes a charging procedure. Therefore, the static electricity phenomena involve contact and separation of materials. There are many electric charging mechanisms. The most common electrostatic charging phenomena observed in our daily life is the triboelectricity phenomena, which follow a contact-induced charge separation mechanism. When two objects with different electrical resistivity are in contact, electrons will exchange in between due to different binding force. Upon separation of the two objects, each object will be electrically charged containing either net positive or negative charges. Many magic and fun static electricity phenomena observed in our life follow the contact-induced charge separation procedure. For example, amber rubbed by fur can attract leaves; a plastic comb combing through hair can attract paper scraps; or you feel your hair raising when taking off a hat in a dry day. The triboelectric effect is considered to be related to the materials adhesion phenomenon and dominated by the atomic-scale electron transfer mechanism [6]. Triboelectric effect is generally unpredictable and depends heavily on many factors, such as materials, surfaces, temperature, pressure, and humidity. The Triboelectric series, as given in Table 1.1, is a reference for the tendency of contact-induced electrostatic charge generation based upon the materials properties. Different materials are friendly to either positive or negative charges at varying levels. The farther apart the two involved materials in the Triboelectric series table, the stronger the triboelectric effect, i.e., the easier the two materials will exchange charges. Materials very close to each other may not exchange charges, i.e., triboelectrification may not occur. Figure 1.6 presents a quantified Triboelectric series [7].

Charge-induced charge separation is another electrostatic charging phenomenon commonly observed also referred to as electrostatic induction