Silicon Technologies E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 477

Veröffentlichungsjahr: 2013

Beschreibung

This book has been written to provide newly arrived engineers in a silicon foundry environment with a comprehensive background in the fundamental physical and chemical basis for major front-end silicon treatments, such as oxidation, epitaxy, ion implantation and impurities diffusion, as well as giving a survey of the major types of equipment used in integrated circuit (IC) chip foundries.

Techniques include various forms of chemical vapor deposition (CVD), epitaxy, thin film technologies, lithography, masking, and other nanotechnologies.

As well as the target audience, the book will also be of great interest to engineers and advanced students in all these and related fields of electrical engineering, materials science, and manufacturing.

Leseprobe

Table of Contents

Preface

Chapter 1. Silicon and Silicon Carbide Oxidation

1.1. Introduction

1.2. Overview of the various oxidation techniques

1.3. Some physical properties of silica

1.4. Equations of atomic transport during oxidation

1.5. Is it possible to identify the transport mechanisms taking place during oxidation?

1.6. Transport equations in the case of thermal oxidation

1.7. Deal and Grove theory of thermal oxidation

1.8. Theory of thermal oxidation under water vapor of silicon

1.9. Kinetics of growth in O2 for oxide films < 30 nm

1.10. Fluctuations of the oxidation constants under experimental conditions

1.11. Conclusion

1.12. Bibliography

Chapter 2. Ion Implantation

2.1. Introduction

2.2. Ion implanters

2.3. Ion range

2.4. Creation and healing of the defects

2.5. Applications in traditional technologies and new tendencies

2.6. Conclusion

2.7. Bibliography

Chapter 3. Dopant Diffusion: Modeling and Technological Challenges

3.1. Introduction

3.2. Diffusion in solids

3.3. Dopant diffusion in single-crystal silicon

3.4. Examples of associated engineering problems

3.5. Dopant diffusion in germanium

3.6. Conclusion

3.7. Bibliography

Chapter 4. Epitaxy of Strained Si/Si1-x Gex Heterostructures

4.1. Introduction

4.2. Engineering of the pMOSFET transistor channel using pseudomorphic SiGe layers

4.3. Engineering of the nMOSFET transistor channel using pseudomorphic Si1-yCy layers; SiGeC diffusion barriers

4.4. Epitaxy of Si raised sources and drains on ultra-thin SOI substrates

4.5. Epitaxy of recessed and raised SiGe:B sources and drains on ultra-thin SOI and SON substrates

4.6. Virtual SiGe substrates: fabrication of sSOI substrates and of dual c-Ge / t-Si channels

4.7. Thin or thick layers of pure Ge on Si for nano and opto-electronics

4.8. Devices based on sacrificial layers of SiGe

4.9. Conclusions and prospects

4.10. Bibliography

List of Authors

Index

First published 2011 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.

Apart from any fair dealing for the purposes of research or private study, or criticism or review, aspermitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced,stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers,or in the case of reprographic reproduction in accordance with the terms and licenses issued by theCLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at theundermentioned address:

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The rights of Annie Baudrant to be identified as the author of this work have been asserted by her inaccordance with the Copyright, Designs and Patents Act 1988.

Library of Congress Cataloging-in-Publication Data

Silicon technologies : ion implantation and thermal treatment / edited by Annie Baudrant.

p. cm.

Includes bibliographical references and index.ISBN 978-1-84821-231-21. Semiconductor doping. 2. Ion implantation. 3. Semiconductors--Heat treatment. I. Baudrant, Annie.TK7871.85.S5485 2011621.3815'2--dc22

2011008131

British Library Cataloguing-in-Publication Data

A CIP record for this book is available from the British Library

ISBN 978-1-84821-231-2

Text not available in this digital edition.

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Preface

Electronic components based on semiconductors are at the core of all electrical and electronic equipment. They are stakeholders of an increasing share of the objects surrounding and accompanying us. They give to these objects various functions: capture, storage, transmission or information restoration (cameras, phones, TV, etc.), control-command, aid to decision-making, safety, etc.

Nowadays, the components aggregate more than 20% of the value of electrical or electronic equipment, against 7% in 1985. Therefore, there is a global market of the “semiconductor” sector of 270 billion dollars.

These components are indeed at the heart of all applications, for the “digital society”, of which they ensure both the engine and the memory, or for the improvements expected in the fields of transport, aeronautics, health, safety, and electrical energy management close to the user or within distribution systems.

Broadband available to all, the intelligent and efficient management of energy in buildings, telehealth, the intelligent road and zero emission cars or even the replacement of the electrical infrastructure, go inevitably through an increasing use of electronic components with more complex and powerful semiconductors.

The number of delivered components amounts to billions of parts per week (3.25 billion of units/week, at the end of December 2009).

This increasing and continuous penetration of electronic components in equipment was made possible by two other key features of the sector, which have been permanent over the last four decades:

— the monolithic and collective fulfillment or the increasing integration, of complex electronic functions (combination of elementary components) on hardware support, which constitutes an integrated silicon circuit, with a fast renewal of products and technologies;

— the continuous reduction of manufacturing costs and unit prices.

For the driving markets of the memories, of the specific processors and digital circuits, the production is primarily based on CMOS technologies. They are characterized by the most critical dimension of the transistors constituting them. Thus, the “40 nm node” corresponds to the technology, where this lower limit measures 40 nm.

Nowadays, the most aggressive generation of production is the 40 nm node, but the 28 nm node will be proposed in production from the next half-year.

The dimensions' reduction, for which the transistors (elementary components of the integrated circuits) are produced, is at the heart of two important product evolutions:

— the rise in performance (transistor speed, related to the minimal size of these elementary components);

— the integration of a growing number of transistors, today exceeding a billion per circuit.

The evolution of technologies leading to this increasing integration is fast. It follows an empirical prediction made by Gordon Moore (cofounder of Intel), of an integration doubled every 18 months. Unequalled fact in any industrial sector, this technical evolution of the products has lasted for four decades (see Figure 1).

The manufacturing technologies of electronic components have evolved a lot since the invention of the first transistor: we went from an element the size of a 1€ coin to submicron dimensions (45 nm previewed at IBM in spring 2006, while in December 2007, the TSMC group sampled SRAMs in 32 nm technology. Nowadays, we are heading for 22 nm and below).

Nevertheless, some principles have been preserved, and of course the technology is subjected to constraints, resulting from the fundamental properties of the semiconductors, such as they appear in the chapters on the components' physics. Let us note however that 32 nm noticeably represents the thickness of a hundred atomic lines, and that we imperceptibly come near a limit below which we will no longer be able to go, except by completely changing the principles.

Figure 1.Moore's law

Surprisingly, there are no works written in the French language describing these 30 years of history and evolution of technological methods. We can remember:

— that the evolution of CMOS technologies is made up of incremental and radical evolutions;

— that the control of these radical evolutions gives place to the highest costs and are the object of strategic decisions.

We often find a good number of precise publications on each topic, but little or no scientific summaries outlining the “why and how” of the various technical choices.

Among these key points, we have often quoted, over the last ten years:

— around the year 2000, for 130 to 90 nm nodes:

- introduction of 193 nm optical lithography;

- introduction of the Copper technology: with this method, we can accelerate the interconnections between the transistors and reduce the losses;

— around the year 2005, for 65 to 45 nm nodes:

- dipping lithography: with this, we can go down below 65 nm. Its unit piece of equipment exceeds 50 million dollars;

- the process-induced strain, introduced in 2003 by Intel, and taken over since then by almost all of the other microprocessor manufacturers (i.e. the strain induced in a localized way into the channel of the transistors;

— around 2010, for 32 to 22 nm nodes:

- introduction of the technology of metal gate and of high permittivity dielectric, which reduces the leak of transistors during their miniaturization;

- transition to substrates of thin silicon films (SOI), to improve the performances of transistors of the smallest sizes;

— around 2014, for the 18-12 nm node:

- EUV (extreme ultraviolet) lithography.

All these stages use new techniques and thus new investments. We forget to name the advances made in the course of time by elementary methods, with the constant objective to decrease all dimensions (width, length, thickness) and to increase all the electrical performances (current, speed, low consumption, etc.).

This book thus proposes to the reader a timeline, of the development of active zones, modifying the surface structure of the massive silicon substrate, the basic principles, the implementations according to the technological fields, the limits and constraints, with a focus on the recent advances.

Its objective is not to go through the issue exhaustively for all the elementary processes of a technological assembly, but to point out the essential and fundamental pieces of data, only for the methods aiming to use and to improve the properties of the material or of the silicon semiconductor, for the electronic components, as well as for the microsystems (integrated sensors for example).

Below, a few paragraphs introduce each of the four matters evoked, but leave to the authors (J.J. Ganem, I. Trimaille, J.J. Grob, D. Mathiot and J.M. Hartmann, the best French-speaking specialists on the topic), the pleasure of elaborating on the manufacturing methods and scientific materials (physical and chemical laws),which consolidate or predict the outcomes.

Silicon oxidation

Oxidation is a very important stage in the achievement of integrated silicon circuits, because it is thanks to this specific property that the silicon, which is not a priori a very good semiconductor, has become the most frequently used material in microelectronics. This operation is necessary throughout the modern manufacturing methods of integrated circuits. It is thus essential to know how to carry out an oxide of good quality.

The oxide can be used as:

— an implantation and diffusion mask of dopants;

— a passivating layer on the silicon surface;

— insulation zones between various components of an integrated structure;

— an active zone in MOS (gate oxide) transistors;

— electrical insulation between the adjacent layers to improve the integration and the reduction of dimensions (“spacer” for example, see further);

— electrical insulation between the various levels of metallization or of conducting layers in strongly doped polycrystalline silicon;

— sacrificial layers that can improve the circuit performances and integration. These sacrificial layers can also be used to manufacture microstructures containing polycrystalline silicon and to intervene in integrated microsystems (MEMS: micro electro-mechanical systems).

Ion implantation

Ion implantation is a low-temperature process. The implantation process takes the ions of the chosen species, accelerates them with an electrical field, and then makes them scan the surface of the slice, to carry out a uniform pre-deposition.

This method of introducing doping atoms into silicon was developed in the 1960s: it is ion implantation (an ion is a loaded atom). Very briefly, the ion implantation consists of projecting the ions of the adequate doping species towards the slice, through the openings of an oxide mask or of hardened resin.

The ions used for the doping, such as boron, phosphorus or arsenic, are generally produced from a gas source, guaranteeing a great purity of the source. These gases have a tendency to be very dangerous. When they are implanted in a semiconductor, each doping atom creates a charge carrier (hole or electron according to whether it is a type p or n dopant), thus locally altering the conductivity of the semiconductor.

The ion implantation is also a method used for the preparation of SOI (silicon-on-insulator) substrates from conventional silicon substrates.

Diffusion

Diffusion is the term used to describe the movement of atoms, molecules or particles from a high concentration zone towards a lower concentration zone.

Diffusion is a phenomenon, depending on time and temperature. The diffusion velocity of an atom, molecule or compound from an area of high concentration towards a low concentration zone is a function of time and temperature. The parameter connecting the diffusion velocity to the temperature at a given time, is known as the diffusion or diffusivity coefficient.

The atoms of the dopant must move the silicon atoms of the crystalline structure and take their place to become electrically active. The diffusion process is used in the manufacture of integrated circuits, in order to introduce a controlled quantity of a specific dopant into a specific area of the semiconductor crystal. The diffusion process used to achieve this substitution is divided into distinct stages.

Epitaxy of strained Si/Si1-xGex hetero-structures

The term epitaxy is of Greek origin and means “to build above”. Deposition by epitaxy is in general the construction of a single-crystal silicon layer on a slice (also a single-crystal). The layer deposited is a crystallographic extension of the substrate, from the point of view of the atomic arrangement (i.e. identical crystalline structure). The substrate can thus be regarded as the “seed” essential to generate a single-crystal growth.

Deposition by epitaxy is a process of CVD. The first use of CVD was the single-crystal silicon deposition at the end of the 1950s. This technique then played a crucial role in this industry, but this chapter will not develop the aspect “material -growth and crystallography of silicon substrates”, instead focusing on the use of the epitaxy technique for the manufacture of active SiGe zones in nano-CMOS new technologies.

We hope that by introducing a comprehensive overview of these techniques to readers, this book will answer the expectations of those students, professors, technicians, engineers or researchers, closely interested in the manufacture of silicon micro nanostructures.

This preface would not be complete without extending to the authors, J.J. Ganem, I. Trimaille, J.J. Grob, D. Mathiot and J.M. Hartmann, my warmest thanks for their rich contributions to this book.

Annie BAUDRANTMay 2011

Chapter 1

Silicon and Silicon Carbide Oxidation1

This chapter is devoted to the physics of silicon and silicon carbide oxidation. We will find in this chapter, an examination of the main techniques of deposition and growth of thin films. The reader will then discover how the laws governing oxidation are established, in particular those concerning silicon oxidation. This remains nowadays the most widespread method in the manufacture of integrated circuits and of MEMS in the broad sense. This chapter has a double purpose. First, it is written to expose in detail the theoretical principles that are particularly interesting for researchers, and secondly, to review a certain number of experimental results, useful in the practice of any process engineer.

1.1. Introduction

The substantial improvement of the electrical and physical characteristics of the SiO2/Si interface leads to an impressive development of integrated circuits. That was made possible by a better understanding, over time, of the way in which silica is manufactured by deposition or growth on silicon.

Although thermal growth is nowadays one of the most frequently used methods, other techniques have also been developed. In section 1.2, we review the main passivation techniques employed today in industry as well as in research laboratories.

In the semiconductor industry, silica can be manufactured by thermal growth from silicon substrates placed at atmospheric pressure in a flux of water vapor, oxygen or a mix of oxidizing gases. Chemical vapor deposition is also usually used to obtain thick passivation films.

In laboratories, more often aiming at the study of physical phenomena governing the production of layers, the techniques used will be based on the physics of the methods (anodic oxidation in an electrolytic environment or by oxygen plasma) or on specific conditions of thermal oxidation (low or high pressure, etc.).

In section 1.3, we detail the silica properties useful for understanding the growth phenomena. We pay particular attention to showing the properties of atomic transport and the solubility of gases in silica. For a more complete review of the physical characteristics of silica, we refer the reader to the works of Bruckner [BRU 70]. For self-scattering and chemical diffusion in glasses, we recommend the works of Frischat [FRI 75].

In section 1.4, we develop the general equations of transport taking place during oxide growth, and the borderline cases arising from various approximate assumptions that can be made on the flux of mobile species in the case of oxidation. Thus, we also could deduct the expressions of the flux of the transported ion species, in the case of anodic oxidation.

In section 1.5, we show how it is possible to give a satisfactory answer to the two following questions: Which are the mobile species in silicon and in silicon carbide oxidation? How do they move? For this purpose, isotopic labeling techniques are also presented, as well as the experimental results.

In section 1.6, we state the transport equations after the simplifying hypotheses. Two cases are considered, where the transported species are either neutral or charged. When they are charged, two cases still emerge. For the films with a thickness lower than 3 nm, where the tunneling currents are established, the Cabrera and Mott theory predicts the growth laws. For the larger thicknesses, equations become very complex.