SiP System-in-Package Design and Simulation E-Book

Suny Li (Li Yang)

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch

Seitenzahl: 517

Veröffentlichungsjahr: 2017

Beschreibung

An advanced reference documenting, in detail, every step of a real System-in-Package (SiP) design flow Written by an engineer at the leading edge of SiP design and implementation, this book demonstrates how to design SiPs using Mentor EE Flow. Key topics covered include wire bonding, die stacks, cavity, flip chip and RDL (redistribution layer), Embedded Passive, RF design, concurrent design, Xtreme design, 3D real-time DRC (design rule checking), and SiP manufacture. Extensively illustrated throughout, System in Package Design and Simulation covers an array of issues of vital concern for SiP design and fabrication electronics engineers, as well as SiP users, including: * Cavity and sacked dies design * FlipChip and RDL design * Routing and coppering * 3D Real-Time DRC check * SiP simulation technology * Mentor SiP Design and Simulation Platform Designed to function equally well as a reference, tutorial, and self-study, System in Package Design and Simulation is an indispensable working resource for every SiP designer, especially those who use Mentor design tools.

Leseprobe

Table of Contents

Cover

Title Page

Copyright

About the Author

Preface

Chapter 1: SiP Design and Simulation Platform

1.1 From package to SiP

1.2 The development of mentor SiP design technology

1.3 The mentor SiP design and simulation platform

1.4 The introduction of the finished project

Chapter 2: Introduction to Package

2.1 Definition and function of package

2.2 Development of packaging technology

2.3 SiP and Related Technologies

2.4 The development of the package market

2.5 Package manufacturers

2.6 Bare chip suppliers

SiP System-in-Package Design and Simulation

Mentor EE Flow Advanced Design Guide

Suny Li (Li Yang)

SiP/PCB Technical Specialist Beijing, China

This edition first published 2017 by John Wiley & Sons Singapore Pte. Ltd under exclusive license granted by Publishing House of Electronics Industry for all media and languages (excluding simplified and traditional Chinese) throughout the world (excluding Mainland China), and with non-exclusive license for electronic versions in Mainland China.

© 2017 Publishing House of Electronics Industry

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The right of Suny Li (Li Yang) to be identified as the author of this work has been asserted in accordance with law.

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Library of Congress Cataloging-in-Publication Data

Names: Li (Li Yang), Suny, 1974- author.

Title: SiP system-in-package design and simulation : Mentor EE Flow advanced design guide / Suny Li (Li Yang).

Description: Singapore ; Hoboken, NJ : John Wiley & Sons, 2017. | Includes bibliographical references and index.

Identifiers: LCCN 2017007232 (print) | LCCN 2017011202 (ebook) | ISBN 9781119045939 (cloth) | ISBN 9781119046011 (Adobe PDF) | ISBN 9781119046004 (ePub)

Subjects: LCSH: Integrated circuits--Design and construction. | Multichip modules (Microelectronics)-Design and construction.

Classification: LCC TK7874 .L437 2017 (print) | LCC TK7874 (ebook) | DDC 621.3815-dc23

LC record available at https://lccn.loc.gov/2017007232

John Wiley & Sons Limited is a private limited company registered in England with registered number 641132. Registered office address: The Atrium, Southern Gate, Chichester, West Sussex, United Kingdom. PO19 8SQ.

Cover design by Wiley

Cover Images: (Background) © KTSDESIGN/Gettyimages; (Gold Chip) Courtesy of the author

About the Author

Mr. Suny Li (Li Yang) is an SiP/PCB Technical Specialist in China; he now works in AcconSys Technology Co., Ltd, (a Mentor Authorized Distributor for China).

Suny has guided and consulted on dozens of SiP projects in China, accumulating plentiful experience in SiP design and simulation.

Suny has 10 years' experience in and knowledge of Application Engineer for Mentor especially in SiP/PCB design and simulation.

Before this, Suny worked in the Chinese Academy of Science and SIEMENS for several years. He has more than seven years' experience in hardware design (HW system design, PCB layout, high-speed signal integrity, power integrity, EMI, etc.).

In the course of his work, Suny has published papers and acquired four patents, and he continues with this work.

Suny is a senior member of the Chinese Institute of Electronics (CIE) and a member of the IEEE.

Suny graduated from Beijing University of Aeronautics & Astronautics (BUAA) in 2000, receiving Master's and Bachelor's degrees in Science and Technology of Aeronautics & Astronautics.

Preface

SiP – System in Package technology is becoming a hotspot of current electronic technology development, receiving attention from many sides, including from traditional package designers, traditional MCM designers and traditional PCB designers, and even SoC designers are beginning to pay close attention to SiP technology.

Comparing SiP to package, SiP is a system-level chip package, with independent system functionality.

In comparison with MCM, SiP is a three-dimensional chip package; its 3D aspect is mainly embodied in the chip stack and substrate cavity; at the same time, the functionality and volume of SiP are greater than those of MCM.

In comparison with PCB, SiP's advantage lies in the aspects of miniaturization, low power consumption and high performance. To achieve the same function as PCB, SiP only needs about 10–20% of PCB area and 40% of PCB power consumption, and system performance will be greatly improved over traditional PCB.

In comparison with SoC, the advantages of SiP technology lie mainly in its short cycle, low cost, ease of use and success rate. To achieve the same result, SiP needs just 10–20% the R&D time required by SoC, and costs in the region of 10–15% of the cost of SoC, and SiP is more likely to be successful.

In China and all over the world, more and more electronic design engineers are beginning to pay close attention to SiP and to study this technology, but since there is no SiP reference book available, designers often do not know how to start; this has to some extent hindered the rapid development of SiP technology.

The author of this book in recent years has been engaged in research into SiP technology and technical support of customers engaged in SiP design and simulation, and has participated in many SiP projects.

During these projects, I realized that there was a more and more pressing need for a comprehensive SiP reference book for users of SiP design and simulation technology. It is for this reason that I wrote this book.

The book is divided into 21 chapters, and systematically describes the whole process of SiP from design to simulation.

Because the SiP projects I have participated in are designed with Mentor SiP tools, the book's description of the SiP design and simulation methods is based on Mentor tools.

The following is a high-level description of the chapters of the book.

Chapter 1

focuses on the development of the Mentor SiP technology, as well as providing an introduction to the Mentor SiP design and simulation platform.

Chapter 2

provides a basic description of package and SiP, including details such as package manufacturers and chip suppliers.

Chapter 3

deals with BGA package, and describes the SiP packaging production process.

Chapter 4

introduces new packaging technologies and their application, including TSV, IPD, PoP, etc.

Chapter 5

describes the entire SiP design and simulation process.

Chapter 6

introduces the establishment and management of the SiP design central library.

Chapter 7

introduces SiP schematic design, various options and other functions.

Chapter 8

introduces multi-board project management, concurrent schematic design, and implementation methods.

Chapter 9

introduces SiP layout creation, setup and operation.

Chapter 10

describes constraint rules management in SiP design.

Chapter 11

introduces the bond wire model, parameter setting and design methods.

Chapter 12

introduces the cavity and chip stack, their definitions and design methods.

Chapter 13

introduces the concept and the design methods of flip chip and RDL.

Chapter 14

describes SiP substrate routing and plane shape processing methods.

Chapter 15

introduces embedded resistor and capacitor technology, materials and design methods.

Chapter 16

introduces design methods for RF circuits and RF schematic and layout design, as well as the link with simulation tools.

Chapter 17

describes Xtreme real-time concurrent design technology and operation methods.

Chapter 18

describes the 3D real-time DRC check, and use of 3D Viewer to simulate SiP production and processing.

Chapter 19

introduces DRC technology, including online DRC, batch DRC and hazard review.

Chapter 20

introduces the output of various kinds of production data.

Chapter 21

describes several SiP simulation technologies.

The chapters provide a complete description of SiP and the problems that may be met in design.

As regards technologies in SiP design that this book doesn't cover, I hope readers will bring these up, and I will deal with them in subsequent editions of the book.

In writing this book, I have striven to create a comprehensive book on SiP. Therefore, in addition to introducing various techniques and methods in SiP design, in the last chapter of this book I introduce SiP simulation technology.

To provide reassurance to beginners in SiP design, in addition to describing SiP design and simulation, the book also introduces SiP manufacturers and bare chip suppliers, and provides other relevant reference information.

Furthermore, the book has three chapters introducing the basics of package and SiP, the production process and emerging SiP technologies, so that engineers who know very little about SiP or package before touching this book can, with the guidance provided, accomplish high-speed, high-quality SiP design.

Of course, although I strove for perfection in writing this book, limitations in my knowledge may lead to faults and errors. I hope that experts and readers will kindly supply suggestions to allow any faults to be corrected in future editions.

I sincerely hope that the publication of this book can play a role in the development of SiP technology and related industries.

Author: Suny Li (Li Yang) Chinese version, March 2012, Beijing English version, July 2016, Beijing

Chapter 1SiP Design and Simulation Platform

1.1 From package to SiP

Package is the term commonly used to refer to the protective housing and related accessories of a single Integrated Circuit (IC) bare chip cut down from wafer; it is mainly used to protect the silicon chips. Because silicon chips are very fragile, even very fine dust or water droplets can destroy their functionality, so it is necessary to protect IC chips with package. Another feature of package is to amplify the scale; because the chip itself is usually very small, the scale is increased by package, making it easier to use in subsequent board-level PCB systems. The third function of package is electrical connection: via package, the chip exchanges information with the outside world.

Depending on the process or material, package product is usually divided into three types: plastic package, ceramic package and metal package. Plastic package is mainly used in commercial products and has the advantage of low cost, but the thermal dissipation, stability and air tightness are relatively poor. Ceramic package and metal package are suitable for industrial products as well as in the aerospace, military and other harsh fields, have excellent heat dissipation and air tightness, and high reliability. Meanwhile, ceramic and metal package have the advantage that they can be disassembled easily for fault finding and problem “zeroing”. Figure 1.1 shows the three different kinds of package.

Figure 1.1 Three different kinds of package.

IC package typically includes DIP, QFP, BGA, etc. With improvements in technology, packaging technology developed rapidly, along the DIP→QFP→BGA→CSP direction. Package density is becoming higher, scale is increasing quickly, and number of pins is growing fast. Single-chip package has not met the requirements of system design; packaging products are developing from small scale to large scale, from single-chip package to multi-chip package.

Multi-chip package has attracted more and more attention, with most directed to System in Package (SiP).

SiP, as the name suggests, refers to the integration of a system in a package body. Typically, this system requires encapsulating multiple chips able to complete a specific task, such as system-level package-integrated CPU, DRAM, Flash and other IC chips. At present, with the development of package technology, SiP has gradually developed to 3D stacked-chip package.

Multi-chip package is not a new concept; MCM (Multi-Chip Module) technology has been popular for many years, and has been widely used in specific areas such as the military, aerospace and aviation.

MCM is a kind of package; as opposed to SiP, small chips are usually used in MCM, which can accomplish relatively simple functions compared to SiP. In MCM the chips are usually in 2D layout.

The bare chips used in MCM usually have a single function, and are smaller and simple. MCM uses 2D flat package, which also means that it is not easy to increase the capability of MCM, it is difficult to shrink in size, and there are other disadvantages.

SiP combines the advantages of both MCM and large-scale IC package.

SiP package is specifically intended for large-scale, multi-chip, 3D packaging. Its stereoscopic 3D nature is mainly reflected in the two aspects of chip stacking and substrate cavity. Figure 1.2 shows the process of IC package and MCM evolving to SiP.

Figure 1.2 Evolution from IC package and MCM to SiP.

The new trend in SiP technology development is that traditional package design by IC chip manufacturers is being gradually transformed to a new arrangement whereby the system user is beginning to consider and design the package. In the past, chip manufacturers usually packaged chips and then delivered them to the user.

Now, with the development of SiP technology, miniaturization and low-power design requirements, more and more system users want to get the bare dies, and build their system based on bare dies and packaging.

It follows that market demand for bare chips will greatly increase, as more and more designers want to know how to get the bare chips.

As these demands continue to grow, traditional IC agents will continue to expand their bare chips business in order to meet the growing demands of the market.

If the demand does not reach a certain number, orders for bare chips from IC manufacturer are usually made via agents. There will be some delay for the customer. So, the SiP designer, in the early stages of project, should fully consider the order channels and order cycles. When the market demand for bare chips reaches a certain level, and when there is a continuing demand, bare chips agents would consider increasing their inventories to meet customer needs.

The bare chip market is developing, and is driven by the rapidly growing demand for SiP technology. In turn, developments in the bare chip market promote the application and popularity of SiP technology.

Because SiP or package design is gradually shifting from the IC chip manufacturer to the system user and system users are most concerned with system design, the collaboration of package design and system design will also become increasingly important. Package design itself will become a key link to system design, with designers required to realize the function of the entire system in a unified platform. Figure 1.3 shows the relationship between IC bare chips, SiP package and the PCB board-level system.

Figure 1.3 The relationship between IC bare chips, SiP package and the PCB board-level system.

SiP is getting much attention, not only from traditional package designers, but also from traditional MCM designers and PCB designers, and even SoC designers have begun to keep a watchful eye on SiP. Refer to Figure 1.4.

Figure 1.4 SiP is receiving attention from a wide range of areas.

As compared with traditional package, SiP is a system-level package, and can accomplish system functions independently.

Compared with MCM, SiP is a 3D multi-chip package, with the 3D embodied in chip stacks and substrate cavities, while the scale and function of SiP are also greatly increased compared to MCM.

Compared with PCB, the advantage of SiP technology is mainly in terms of miniaturization, low power consumption and high performance. To realize the same function as PCB, SiP only needs about 10–20% of the area and 40% of the power of a corresponding PCB, and also has a relatively large performance improvement over PCB.

Compared with SoC, the advantage of SiP is mainly embodied in short cycles, low cost and ease of success. To achieve the same function, only 10–20% of the development time required for SoC is needed for SiP, the cost of SiP development is typically about 10–15% that of SoC, and SiP is more likely to succeed. Therefore, SiP is often seen as a low-cost, short-term, alternative solution to SoC by many users.

Often, SiP is a forerunner at the start of an SoC project, used to make a rapid and low-cost SiP product. When SiP is successful, giving some initial results on the project, and receiving recognition and support from all, the project then shifts to SoC research and development.

With increasing demand for high-performance, high-speed and versatile design, designers are more concerned about signal integrity, power integrity, crosstalk, EMC/EMI, and functional simulation and verification. A common solution is to use simulation tools to assist in the design flow; HyperLynx SI/PI/Thermal, HyperLynx DRC, HyperLynx 3DEM solver and HyperLynx Analog are commonly used simulation tools.

For high-density, small-size and low-power-consumption design, designers require design rules such as trace width and clearance, smaller passive components, for example, resistors and capacitors, HDI (High Density Interconnection) technology, and buried and blind via technology.

Moreover, design software and product technics support the use of many passive components embedded in the substrate; this is called EP (Embedded Passive) technology, and consists of bare dies mounted directly on the circuit board; this is called COB (Chip On Board) technology.

With the application and maturity of these technologies, PCB system designers began to focus on a new technology, which is the integration of all these technologies: this is SiP technology.

In contrast with PCB, to realize the same function SiP requires only 10%~20% area and 40% power consumption of original PCB; refer to Figure 1.5.

Figure 1.5 Size and power consumption comparison between PCB and SiP.

1.2 The development of mentor SiP design technology

The Mentor company is the largest EDA software supplier of PCB board-level system design in the world. Mentor provides the most advanced solutions for electronics companies and research institutions worldwide.

Mentor has held the absolute leading position in the PCB design market for many years. Statistical data from the global PCB design market (third-party statistics) show that Mentor has more than 50% of the market share, dominating the market and far outstripping competitors.

In May 2009, based on version EE2007.5, Mentor launched the Expedition advanced packaging bundle (Expedition AdvPkg) to support SiP design. Before launching this module, Mentor had no tool for package or SiP design specifically; however, Mentor's related technology can be traced back a few decades.

First, let us recall the processes of the Mentor package and SiP technology accumulation and development.

BoardStation, also called EN (ENTERPRISE), is an excellent Mentor PCB board-level system design platform, mainly used by high-end PCB designers.

In BoardStation there is a module called Hybrid Station, mainly used in hybrid circuits and MCM design, which has a wide range of applications in MCM and mixed-signal circuit design. At present, there are still a number of companies and research institutes worldwide which use this design platform for their projects.

In the 1990s, Mentor acquired DDE's Supermax ECAD. Supermax ECAD is an excellent tool, used mainly for embedded passive, MCM, Hybrid IC package and RF design. As multi-functional layout software, the distinctive feature of Supermax ECAD is the ability to support RF, EP, package and MCM design.

Mentor developed these technologies, and gradually integrated and consolidated them into a new software product: Expedition Enterprise Flow, EE Flow for short.

With the development of technology and design needs, Mentor is gradually shifting its high-end PCB board-level design platform, focused on Expedition Enterprise Flow; the latest version is EE7.9.5.

At the same time, Expedition Enterprise also continues to absorb advanced technology and functionality from other products, covering new areas of design. The Expedition AdvPkg bundle is the new product, which incorporates many of Mentor's advantages in relation to MCM, hybrid circuits, RF, embedded passive components (EP) and other technologies.

Therefore, we can say that while the Expedition AdvPkg bundle is a relatively new product, the technology is very mature, and its technological development can be traced back to the 20th century.

In Figure 1.6, we can see the inheritance and development process of the Mentor SiP design platform and advanced packaging technology.

Figure 1.6 Development of the Mentor SiP platform.

1.3 The mentor SiP design and simulation platform

1.3.1 SiP platform introduction

Mentor provides a comprehensive SiP/MCM, advanced package and PCB design and simulation platform, as shown in Figure 1.7.

Figure 1.7 Mentor SiP/MCM/advanced package/PCB design and simulation platform.

For SiP design needs, the Expedition AdvPkg bundle comprises AdvPkg, 3D Check, EP, RF and AI (Advanced Interconnection), as well as FabLink XE Pro modules, specialized support for SiP/MCM, advanced packaging design, data output and validation.

Meanwhile, for SiP simulation, Mentor offers the mixed digital–analog simulation tool HyperLynx Analog, the thermal simulation tool HyperLynx Thermal, the signal integrity analysis tool HyperLynx SI, the power integrity analysis tool HyperLynx PI, the 3D electromagnetic simulation tool HyperLynx 3D EM and the EMI/EMC check tool HyperLynx DRC.

Mentor's design and simulation flow for SiP/MCM and advanced package is a Windows-based software platform, compatible with both Linux and Solaris. Mentor EE Flow supported platforms and processors are shown in Figure 1.8.

Figure 1.8 Mentor EE Flow supported platforms and processors.

1.3.2 Schematic input

DxDesigner is the schematic input tool in the SiP design platform.

In addition to conventional schematic, DxDesigner supports RF input, and its RF components library is synchronized with the Agilent ADS RF library.

In relation to the schematic design phase, DxDesigner is provided with a mixed-circuit simulation tool, to simulate the function of circuits, so as to ensure that “design is correct” from the outset.

Meanwhile, designers can also use the SI pre-simulation tool to do “what if” analysis of the signal integrity of the design, so as to determine the components selection, net topology planning, terminal-matching and substrate laminate structure parameters of the design.

Using the PI pre-simulation tool, designers can plan power plane partition, distribution of power nets, and the number and variety of decoupling capacitors in the schematic design phase, and reasonably control the power plane impedance.

In addition, DxDesigner supports concurrent schematic design for multiple people designing one schematic at the same time; it does not require any partitioning. This technology is especially important for large and complex projects.

1.3.3 Concurrent system design

Because SiP design and PCB design were eventually carried out by system designers, collaborative design between them became closer and closer. Mentor was sensitive to this new trend, and developed collaborative design capabilities, which also became a key feature of Mentor tools.

As shown in Figure 1.9, multiple designs are managed in one project, including two SiP designs and one PCB board design; each design can be completed independently. There is a mutual relationship between the three designs, because both SiPs are ultimately installed on the PCB board to work together.

Figure 1.9 One project manages multiple designs, and realizes SiP and PCB collaborative design.

This way of managing projects is more reasonable than having three separate designs, because in considering subsequent PCB system design, the pin assignment of SiP design can be optimized.

1.3.4 SiP board design

In the field of PCB board design, Mentor accounted for more than 50% of the global market share, far more than its competitors. Mentor extended its powerful advantages from PCB board design to the SiP design area; all the powerful features of PCB design are also used in SiP design.

Currently, layout is one of the core modules of SiP design. Mentor developed six core design features based on Expedition PCB, features which support the user with all kinds of needs in the SiP design procedure, as shown in Figure 1.10.

Figure 1.10 The six core design functions of Mentor SiP layout.

1.

AdvPkg core design function

AdvPkg(Advanced Packaging)core design function supports wire bonding and substrate cavity, with no level limit on IC chip stacks, and complex multi-step cavity design, as shown in Figure 1.11.

AdvPkg also supports both automatic bonding of complex bond wire and automatic generation of power ring.

Mentor bond wire models can be created using a variety of types of curve fitting, which are more accurate and closer to the actual bonding wire. These models can help designers improve design accuracy, thereby increasing product yield. The Mentor bond wire model is shown in Figure 1.12.

2.

3D check function

The 3D check function supports 3D viewing and checking. It supports interactive 3D real-time DRC check of layout design; it allows checks of the chips, including bond wire and cavity, routing, copper, through-hole vias, buried and blind vias, buried resistors and capacitors, etc. By using 3D real-time DRC check, designers can avoid errors at design time, and ensure design is correct. This interactive 3D real-time DRC is shown in Figure 1.13.

Differing from the traditional method, the Mentor tool is better in relation to understanding the 3D design and check, and realizing 3D real-time inspection during the design process, to ensure design is correct.

In traditional methods, 3D checking is usually executed after design finish, and the designer needs additional tools for 3D inspection. It is similar to checking routing results in a Gerber browser. Typically, design finish is too late for this kind of post-processing 3D inspection, which can seriously affect the accuracy and efficiency of SiP design.

3.

EP function

EP function supports embedded passive components, namely buried resistors and buried capacitors. This function supports the automatic integration of embedded resistors and capacitors.

Depending on the selected material and resistance or capacitance parameters, required resistors or capacitors can be automatically integrated. Laser adjustment is also supported. Expedition supports multiple types of resistor and capacitor, as shown in Figure 1.14; the designer can use resistors and capacitors in any of the substrate layers. Using EP technology, we can greatly save on surface space and reduce the solder joints, thereby increasing the reliability of the design.

4.

RF design function

The RF(Radio Frequency)design function can realize RF circuit design. It supports RF parameter transfer between schematic and layout, and supports RF circuits passing through a dynamic link tool to and from ADS/AWR, as shown in Figure 1.15.

The RF function can also meet some special design requirements in layout, such as gradient-width trace, stitched via and spiral inductor in power supply.

5.

AI function

The AI feature supports automatic routing of blind and buried vias in complex layer structures, and displays the layer numbers through which the buried or blind vias pass in layout, as shown in Figure 1.16.

Intelligent AI automatic routing algorithms can greatly improve the routing completion rate and routing efficiency of the design.

6.

Xtreme concurrent team design function

The Xtreme concurrent team design function is suitable for complex SiP projects, with multiple designers concurrently designing one substrate board. It does not require any design segmentation, and provides design data updates to each designer in real-time. It greatly reduces the difficulty of design and alleviates the pressure on designers. Based on statistical data from real projects, Xtreme can improve design efficiency by as much as 50%.

It is particularly important for complex SiP design, for which timeframes are very tight. Traditional methods generally do not have such a concurrent design function.

Figure 1.17 shows a diagrammatic sketch of Xtreme concurrent team design.

The SiP six core layout design functions are integrated into the design process of Expedition, belonging to the same environment as PCB design.

Therefore, all the advanced features of Expedition PCB can be used for SiP design, such as bus topology planning and bus routing, intelligent high-speed automatic routing, flexible routing, circuit copy, design reuse, and constraint management and other advanced features can be configured according to the design needs.

In addition to providing powerful layout features, Mentor provides a wide range of simulation and verification tools to support SiP design, including signal integrity, power integrity, thermal analysis, EMI/EMC, etc.

Figure 1.11 Chip stacks and multi-step cavity.

Figure 1.12 Mentor bond wire model.

Figure 1.13 Interactive 3D real-time DRC.

Figure 1.14 Expedition supports four kinds of EP resistor and three kinds of EP capacitor.

Figure 1.15 RF design data and RF parameter transfer.

Figure 1.16 Blind and buried via setup and application.

Figure 1.17 Sketch of Xtreme concurrent team design.

1.3.5 Signal integrity and power integrity simulation

The HyperLynx SI signal integrity analysis tool supports SI, crosstalk and EMC simulation, using oscilloscope and spectrum analyzer displays. HyperLynx SI is embedded with FCC, CISPR and VCCI, which are three international EMC standards, and supports users in defining their own standards.