System Level ESD Co-Design E-Book

• Herausgeber: John Wiley & Sons
• Kategorie: Wissenschaft und neue Technologien
• Serie: Wiley - IEEE
• Sprache: Englisch

Seitenzahl: 801

Veröffentlichungsjahr: 2015

Beschreibung

An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. This pioneering book presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from 'hard' to 'soft' types are considered to review simulation and tool applications that can be used.

The principal focus of System Level ESD Co-Design is defining and establishing the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers' system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance.

With contributions from Robert Ashton, Jeffrey Dunnihoo, Micheal Hopkins, Pratik Maheshwari, David Pomerenke, Wolfgang Reinprecht, and Matti Usumaki, readers benefit from hands-on experience and in-depth knowledge in topics ranging from ESD design and the physics of system ESD phenomena to tools and techniques to address soft failures and strategies to design ESD-robust systems that include mobile and automotive applications.

The first dedicated resource to system-level ESD co-design, this is an essential reference for industry ESD designers, system builders, IC suppliers and customers and also Original Equipment Manufacturers (OEMs).

Key features:

• Clarifies the concept of system level ESD protection.
• Introduces a co-design approach for ESD robust systems.
• Details soft and hard ESD fail mechanisms.
• Detailed protection strategies for both mobile and automotive applications.
• Explains simulation tools and methodology for system level ESD co-design and overviews available test methods and standards.
• Highlights economic benefits of system ESD co-design.

Leseprobe

Table of Contents

Cover

Title Page

Copyright

List of Contributors

Preface

Acronyms

About the Book

Chapter 1: Introduction

1.1 Definition of Co-Design

1.2 Overview of the Book

1.3 Challenges of System Level ESD Protection

1.4 Importance of System Level Protection

1.5 Industry-Wide Perception

1.6 Purpose and Motivation

1.7 Organization and Approach

1.8 Outcome for the Reader

Acknowledgments

References

Chapter 2: Component versus System Level ESD

2.1 ESD Threat in the Real World

2.2 Component ESD Qualification

2.3 System Level ESD Tests

2.4 ISO 10605

2.5 IEC 61000-4-5

2.6 Soft Failures Due to IEC Testing

Acknowledgments

References

Chapter 3: System Level Testing for ESD Susceptibility

3.1 Introduction

3.2 Objectives of System Level Testing

3.3 Compliance to ESD Standards

3.4 Testing for Product Reliability

3.5 Standards Requirements for System Level Testing

3.6 Using the IEC Simulator for Device Testing

3.7 Cable Discharge (CDE) Testing

3.8 Evaluation of Test Results

3.9 The Quick Fix vs Root Cause Determination

3.10 Determining Root Cause of System Level ESD

3.11 Reproducibility of System Level ESD Tests

Acknowledgments

References

Chapter 4: PCB/IC Co-Design Concepts for SEED

4.1 On-Chip System ESD Protection

4.2 Off-Chip ESD Protection

4.3 Concept of PCB/IC Co-Design

4.4 Introduction to System Efficient ESD Design

4.5 Characterization for Hard Failures

4.6 Simulation of System Level ESD Discharge Paths

4.7 Characterization of Soft Failures

4.8 Summary of SEED Characterization

Acknowledgments

References

Chapter 5: Hard Failures and PCB Protection Devices

5.1 Introduction

5.2 ESD Damage to ICs

5.3 Protection Methods

5.4 Characteristics of Protection Devices

5.5 Types of Protection Devices for ESD

5.6 Primary and Secondary Protection

5.7 Evaluating IC Pins

5.8 Choosing ESD Protection Devices

5.9 Summary

References

Chapter 6: Soft Failure Mechanisms and PCB Design Measures

6.1 Introduction

6.2 Are HBM, CDM, MM, and Latch-Up Results Meaningful Soft Failures?

6.3 Classification of Soft Failure Modes

6.4 Optimized System Level Testing

6.5 Soft Failure Characterization Methods

6.6 Soft Failure Examples

6.7 Countermeasure Examples

6.8 The Way Forward

Acknowledgment

References

Chapter 7: ESD in Mobile Devices

7.1 Introduction

7.2 ESD Energy Path in Mobile Device

7.3 ESD Generation Examples on a Large Scale

7.4 Relation between Electrostatic Discharge Immunity Test and Real-World Discharge Waveforms

7.5 Laboratory Test Methods

7.6 Fast ESD and Slow ESD Concepts

7.7 Fast-ESD and Slow-ESD in a Mobile Device

7.8 Isolating a Mobile Device

7.9 Shielding a Mobile Device

7.10 Orientation Effects on ESD Path

7.11 ESD Design in Practice

7.12 PCB Layout Considerations of Metal Shielding “Cans”

7.13 ESD Protection for Cable Interfaces

7.14 Common Mode Impedance Concerns for Layout

7.15 ESD and Software Considerations in Mobile Devices

7.16 Software Versions Utilized in Early ESD Immunity Testing

7.17 Conclusion

References

Chapter 8: ESD for Automotive Applications

8.1 Introduction and Historical Aspects

8.2 Automotive Components

8.3 Design Constraints, Operating Voltage, and Overvoltage Tolerance

8.4 On-Board ESD Protection and Internal ESD Protection

8.5 Verification and Qualification

8.6 Conclusion

References

Chapter 9: Future Applications of SEED Methodology

9.1 Refinement of Models

9.2 Limitations of Simulation and Beyond

9.3 Advances toward High-Speed Systems

9.4 Issues and Challenges of System Protection

9.5 Benefits for Next Generation Systems

Acknowledgments

References

Chapter 10: Co-Design Trade-Offs: Balancing Robustness, Performance, and Cost

10.1 Co-Designing across Functional and Corporate Boundaries

10.2 ESD Goals and Constraints

10.3 Costs of System and Component ESD Susceptibility

10.4 Costs of Improving System and Component ESD Robustness

10.5 Defining the Interaction and Trade-off Matrix

10.6 Assigning the Costs of Failure Criteria

10.7 System Development Triangle Co-Design Contributions

10.8 Product Planning Guidelines

10.9 Validating Co-Design Trade-off Decisions

10.10 Conclusions on Co-Design Economics

References

Glossary

Index

End User License Agreement

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Guide

Cover

Table of Contents

Preface

Begin Reading

List of Illustrations

Chapter 1: Introduction

Figure 1.1 Overview of the component and system level ESD event scenarios. With proper ESD controls as required, the IC devices do not see higher than 1 kV at the most, while in the external environments the ESD pulses can be much higher in magnitude and thus require a good system level ESD strategy

Figure 1.2 Comparison of different ESD events. HBM and CDM are component ESD pulses; cable discharge and EOS are other types of ESD events; and system level ESD is represented by the IEC standard. Note that the x-axis is not to scale

Figure 1.3 Failure levels for products characterized with both HBM and IEC pulses. Six case studies performed by the Industry Council on ESD Target Levels (WP3PI) are shown here. In all cases the failures were hard failures (Industry Council on ESD Target Levels, 2010)

Figure 1.4 Schematic of an effective system protection method involves two-stage protection to absorb the predominant energy at the TVS device and board components to protect the internal IC pin

Figure 1.5 The concept of “residual pulse” as described in Marum

et al

. (2009). A TVS device alone cannot protect the interfacing IC pin since the voltage build-up of this device at high currents can still damage the internal pin (S. Marum, J. Watson, C. Duvvury, “Effects of Low Level IEC 61000-4-2 Stress on Integrated Circuits,” International ESD Workshop, Lake Tahoe, CA, May 2007.)

Figure 1.6 Simulated waveforms from (Bertonnaud

et al

., 2012) showing the IEC pulse shape with and without the TVS device. Note that TVS alone still has a large peak that would not protect the internal IC pin. Adding the parasitics of the PCB will mitigate this pulse shape (S. Bertonaud, C. Duvvury, and A. Jahanzeb, “IEC System Level ESD Challenges and Effective Protection Strategy for USB Interface,” ESD Symposium Proceedings 2012.)

Chapter 2: Component versus System Level ESD

Figure 2.1 The TVS Zener diode provides positive transient overvoltage protection from supply to ground and the Schottky diode provides negative supply protection for reverse overshoots

Figure 2.2 ESD strategies from wafer to end-customer applications. In many cases the PCB assembly and test are aslo included in the ESD protected areas.

Figure 2.3 Comparison of measured current versus time waveforms for (a) HBM and (b) CDM

Figure 2.4 Impact of advanced technologies and improved ESD controls on HBM/CDM target levels

Figure 2.5 Various ESD control programs

Figure 2.6 Roadmap for HBM target levels

Figure 2.7 Roadmap for CDM target levels

Figure 2.8 HBM levels requiring ESD control programs (Industry Council on ESD Target Levels, 2007)

Figure 2.9 CDM levels requiring ESD control programs (Industry Council on ESD Target Levels, 2010a)