FPGA Programming for Beginners E-Book

Frank Bruno

• Herausgeber: Packt Publishing
• Kategorie: Wissenschaft und neue Technologien
• Sprache: Englisch
• Veröffentlichungsjahr: 2021

Seitenzahl: 328

Beschreibung

Field Programmable Gate Arrays (FPGAs) have now become a core part of most modern electronic and computer systems. However, to implement your ideas in the real world, you need to get your head around the FPGA architecture, its toolset, and critical design considerations. FPGA Programming for Beginners will help you bring your ideas to life by guiding you through the entire process of programming FPGAs and designing hardware circuits using SystemVerilog.
The book will introduce you to the FPGA and Xilinx architectures and show you how to work on your first project, which includes toggling an LED. You’ll then cover SystemVerilog RTL designs and their implementations. Next, you’ll get to grips with using the combinational Boolean logic design and work on several projects, such as creating a calculator and updating it using FPGA resources. Later, the book will take you through the advanced concepts of AXI and show you how to create a keyboard using PS/2. Finally, you’ll be able to consolidate all the projects in the book to create a unified output using a Video Graphics Array (VGA) controller that you’ll design.
By the end of this SystemVerilog FPGA book, you’ll have learned how to work with FPGA systems and be able to design hardware circuits and boards using SystemVerilog programming.

Leseprobe

FPGA Programming for Beginners

Bring your ideas to life by creating hardware designs and electronic circuits with SystemVerilog

Frank Bruno

BIRMINGHAM—MUMBAI

FPGA Programming for Beginners

Copyright © 2021 Packt Publishing

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First published: March 2021

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ISBN 978-1-78980-541-3

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Contributors

About the author

Frank Bruno is an experienced high-performance design engineer specializing in FPGAs with some ASIC experience. He has experience working for companies such as Cruise, SpaceX, Allston Trading, and Number Nine. He is currently working as an FPGA engineer for Cruise.

About the reviewer

George Kaldis has a bachelor's degree in electrical engineering from Northeastern University and has over 30 years of experience working with FPGAs. He is president of GK-Digital LLC, an FPGA design consulting company. He has implemented many FPGA designs for applications ranging from wireless/wired networking to high-frequency trading and test equipment.

Table of Contents

Preface

Section 1: Introduction to FPGAs and Xilinx Architectures

Chapter 1: Introduction to FPGA Architectures and Xilinx Vivado

Technical requirements

Hardware

Software

What is an ASIC?

Why an ASIC or FPGA?

How does a company create a programmable device using an ASIC process?

Fundamental logic gates

More complex operations

Introducing FPGAs

Exploring the Xilinx Artix-7 and 7 series devices

Combinational logic blocks

Storage

Clocking

I/Os

DSP48E1

ASMBL architecture

Introduction to the Vivado toolset and evaluation boards

Evaluation boards

Nexys A7 100T (or 50T)

Basys 3

Introducing Vivado

Vivado installation

Directory structure

Running the example

Summary

Questions

Challenge

Further reading

Section 2: Introduction to Verilog RTL Design, Simulation, and Implementation

Chapter 2: Combinational Logic

Technical requirements

Creating SystemVerilog modules

How to create reusable code – parameters

Introducing data types

Introducing built-in data types

Creating arrays

Handling multiple-driven nets

Handling signed and unsigned numbers

Adding bits to a signal by concatenating

Casting signed and unsigned numbers

Creating user-defined types

Accessing signals using values with enumerated types

Packaging up code using functions

Creating combinational logic

Using custom data types

Project 1 – creating combinational logic

Testbench

Implementing a leading-one detector using the case statement

Designing a reusable leading-one detector using a for loop

Counting the number of ones

Implementing an adder/subtractor

Multiplier

Bringing it all together

Summary

Questions

Challenge

Further reading

Chapter 3: Counting Button Presses

Technical requirements

What is a sequential element?

Clocking your design

Looking at a basic register

Registers in the Artix 7

Project 2 – Counting button presses

Introducing the seven-segment display

Detecting button presses

What about simulation?

Deep dive on synchronization

Why use multiple clocks?

Two-stage synchronizer

Synchronizing control signals

Passing data

Summary

Questions

Challenge

Further reading

Chapter 4: Let's Build a Calculator

Technical requirements

Implementing our first state machine

Writing a purely sequential state machine

Splitting combination and sequential logic in a state machine

Designing a calculator interface

Designing a Moore state machine

Implementing a Mealy state machine

Practical state machine design

Project 3 – Building a simple calculator

Packaging for reuse

Coding the top level

Investigating the divider

Project 4 – Keeping cars in line

Defining the state diagram

Displaying our traffic lights

Summary

Questions

Challenge

Extra challenge

Further reading

Chapter 5: FPGA Resources and How to Use Them

Technical requirements

Project 5 – Listening and learning

What is a PDM microphone?

Simulating the microphone

Introducing storage

Capturing audio data

Project 6 – Using the temperature sensor

Handling the data

Smoothing out the data

Summary

Questions

Further reading

Chapter 6: Math, Parallelism, and Pipelined Design

Technical requirements

Introduction to fixed-point numbers

Project 7 – Using fixed-point arithmetic in our temperature sensor

Using fixed-point arithmetic to clean up the bring-up time

Temperature conversion using fixed-point arithmetic

What about floating-point numbers?

A quick look at the AXI streaming interface

Project 8 – Updating the temperature sensor project to a pipelined floating-point implementation

Fix to floating point conversion

Floating-point math operations

Float to fixed point conversion

Simulation

Parallel designs

ML and AI and massive parallelism

Parallel design – a quick example

Summary

Questions

Challenge

Further reading

Section 3: Interfacing with External Components

Chapter 7: Introduction to AXI

Technical requirements

AXI streaming

Project 9 – creating IPs for Vivado using AXI streaming interfaces

Seven-segment display streaming interface

Developing the ADT7420 IP

Understanding the flt_temp core

IP integrator

AXI4 interfaces (full and AXI-Lite)

Developing IPs – AXI-Lite, full, and streaming

Adding an unpackaged IP to the IP integrator

Summary

Questions

Further reading

Chapter 8: Lots of Data? MIG and DDR2

Technical requirements

Project 10 – introducing external memory

Introduction to DDR2

Generating a DDR2 controller using the Xilinx MIG

Modifying the design for use on the board

Other external memory types

Quad Data Rate (QDR) SRAM

HyperRAM

SPI RAM

Summary

Questions

Challenge

Further reading

Chapter 9: A Better Way to Display – VGA

Technical requirements

Project 11 – Introducing the VGA

Defining registers

Generating timing for the VGA

Displaying text

Testing the VGA controller

Examining the constraints

Summary

Questions

Challenge

Further reading

Chapter 10: Bringing It All Together

Technical requirements

Investigating the keyboard interface

Project 12 – keyboard handling

Testing the PS/2

Project 13 – bringing it all together

Displaying PS/2 keycodes on the VGA screen

Displaying the temperature sensor data

Displaying audio data

Summary

Questions

Challenge

Further reading

Chapter 11: Advanced Topics

Technical requirements

Exploring more advanced SystemVerilog constructs

Interfacing components using the interface construct

Using structures

Block labels

Looping using for loops

Looping using do…while

Exiting a loop using disable

Skipping code using continue

Using constants

Exploring some more advanced verification constructs

Introducing SystemVerilog queues

Display enhancements

A quick introduction to assertions

Using $error or $fatal in synthesis

Other gotchas and how to avoid them

Inferring single bit wires

Bit width mismatches

Upgrading or downgrading Vivado messages

Handling timing closure

Summary

Questions

Further reading

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Section 1: Introduction to FPGAs and Xilinx Architectures

In this section, you will get an understanding of what a Field Programmable Gate Array (FPGA) is, what the underlying technology is, and an introduction to the Artix-7 architecture.

This part of the book comprises the following chapter:

Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado