Electronic Packaging Science and Technology E-Book

King-Ning Tu

• Herausgeber: John Wiley & Sons
• Kategorie: Fachliteratur
• Sprache: Englisch

Seitenzahl: 501

Veröffentlichungsjahr: 2021

Beschreibung

Must-have reference on electronic packaging technology! The electronics industry is shifting towards system packaging technology due to the need for higher chip circuit density without increasing production costs. Electronic packaging, or circuit integration, is seen as a necessary strategy to achieve a performance growth of electronic circuitry in next-generation electronics. With the implementation of novel materials with specific and tunable electrical and magnetic properties, electronic packaging is highly attractive as a solution to achieve denser levels of circuit integration. The first part of the book gives an overview of electronic packaging and provides the reader with the fundamentals of the most important packaging techniques such as wire bonding, tap automatic bonding, flip chip solder joint bonding, microbump bonding, and low temperature direct Cu-to-Cu bonding. Part two consists of concepts of electronic circuit design and its role in low power devices, biomedical devices, and circuit integration. The last part of the book contains topics based on the science of electronic packaging and the reliability of packaging technology.

Leseprobe

Table of Contents

Cover

Title Page

Copyright Page

Preface

1 Introduction

1.1 Introduction

1.2 Impact of Moore’s Law on Si Technology

1.3 5G Technology and AI Applications

1.4 3D IC Packaging Technology

1.5 Reliability Science and Engineering

1.6 The Future of Electronic Packaging Technology

1.7 Outline of the Book

References

Part I:

2 Cu‐to‐Cu and Other Bonding Technologies in Electronic Packaging

2.1 Introduction

2.2 Wire Bonding

2.3 Tape‐Automated Bonding

2.4 Flip‐Chip Solder Joint Bonding

2.5 Micro‐Bump Bonding

2.6 Cu‐to‐Cu Direct Bonding

2.7 Hybrid Bonding

2.8 Reliability – Electromigration and Temperature Cycling Tests

Problems

References

3 Randomly‐Oriented and (111) Uni‐directionally‐Oriented Nanotwin Copper

3.1 Introduction

3.2 Formation Mechanism of Nanotwin Cu

3.3 In Situ Measurement of Stress Evolution During Nanotwin Deposition

3.4 Electrodeposition of Randomly Oriented Nanotwinned Copper

3.5 Formation of Unidirectionally (111)‐oriented Nanotwin Copper

3.6 Grain Growth in [111]‐Oriented nt‐Cu

3.7 Uni‐directional Growth of η‐Cu

6

Sn

5

in Microbumps on (111) Oriented nt‐Cu

3.8 Low Thermal‐Budget Cu‐to‐Cu Bonding Using [111]‐Oriented nt‐Cu

3.9 Nanotwin Cu RDL for Fanout Package and 3D IC Integration

Problems

References

4 Solid–Liquid Interfacial Diffusion Reaction (SLID) Between Copper and Solder

4.1 Introduction

4.2 Kinetics of Scallop‐Type IMC Growth in SLID

4.3 A Simple Model for the Growth of Mono‐Size Hemispheres

4.4 Theory of Flux‐Driven Ripening

4.5 Measurement of the Nano‐channel Width Between Two Scallops

4.6 Extremely Rapid Grain Growth in Scallop‐Type Cu6Sn5 in SLID

Problems

References

5 Solid‐State Reactions Between Copper and Solder

5.1 Introduction

5.2 Layer‐Type Growth of IMC in Solid‐State Reactions

5.3 Wagner Diffusivity

5.4 Kirkendall Void Formation in Cu

3

Sn

5.5 Sidewall Reaction to Form Porous Cu

3

Sn in μ‐Bumps

5.6 Effect of Surface Diffusion on IMC Formation in Pillar‐Type μ‐Bumps

Problems

References

Part II:

6 Essence of Integrated Circuits and Packaging Design

6.1 Introduction

6.2 Transistor and Interconnect Scaling

6.3 Circuit Design and LSI

6.4 System‐on‐Chip (SoC) and Multicore Architectures

6.5 System‐in‐Package (SiP) and Package Technology Evolution

6.6 3D IC Integration and 3D Silicon Integration

6.7 Heterogeneous Integration: An Introduction

Problems

References

7 Performance, Power, Thermal, and Reliability

7.1 Introduction

7.2 Field‐Effect Transistor and Memory Basics

7.3 Performance: A Race in Early IC Design

7.4 Trend in Low Power

7.5 Trade‐off between Performance and Power

7.6 Power Delivery and Clock Distribution Networks

7.7 Low‐Power Design Architectures

7.8 Thermal Problems in IC and Package

7.9 Signal Integrity and Power Integrity (SI/PI)

7.10 Robustness: Reliability and Variability

Problems

References

8 2.5D/3D System‐in‐Packaging Integration

8.1 Introduction

8.2 2.5D IC: Redistribution Layer (RDL) and TSV‐Interposer

8.3 2.5D IC: Silicon, Glass, and Organic Substrates

8.4 2.5D IC: HBM on Silicon Interposer

8.5 3D IC: Memory Bandwidth Challenge for High‐Performance Computing

8.6 3D IC: Electrical and Thermal TSVs

8.7 3D IC: 3D‐Stacked Memory and Integrated Memory Controller

8.8 Innovative Packaging for Modern Chips/Chiplets

8.9 Power Distribution for 3D IC Integration

8.10 Challenge and Trend

Problems

References

Part III:

9 Irreversible Processes in Electronic Packaging Technology

9.1 Introduction

9.2 Flow in Open Systems

9.3 Entropy Production

9.4 Cross‐Effects in Irreversible Processes

9.5 Cross‐Effect Between Atomic Diffusion and Electrical Conduction

9.6 Irreversible Processes in Thermomigration

9.7 Cross‐Effect Between Heat Conduction and Electrical Conduction

Problems

References

10 Electromigration

10.1 Introduction

10.2 To Compare the Parameters in Atomic Diffusion and Electric Conduction

10.3 Basic of Electromigration

10.4 Current Crowding and Electromigration in 3‐Dimensional Circuits

10.5 Joule Heating and Heat Dissipation

Problems

References

11 Thermomigration

11.1 Introduction

11.2 Driving Force of Thermomigration

11.3 Analysis of Heat of Transport,

Q*

11.4 Thermomigration Due to Heat Transfer Between Neighboring Pairs of Powered and Unpowered Solder Joints

Problems

References

12 Stress‐Migration

12.1 Introduction

12.2 Chemical Potential in a Stressed Solid

12.3 Stoney’s Equation of Biaxial Stress in Thin Films

12.4 Diffusional Creep

12.5 Spontaneous Sn Whisker Growth at Room Temperature

12.6 Comparison of Driving Forces Among Electromigration, Thermomigration, and Stress‐Migration

Problems

References

13 Failure Analysis

13.1 Introduction

13.2 Microstructure Change with or Without Lattice Shift

13.3 Statistical Analysis of Failure

13.4 A Unified Model of MTTF for Electromigration, Thermomigration, and Stress‐Migration

13.5 Failure Analysis in Mobile Technology

Problems

References

14 Artificial Intelligence in Electronic Packaging Reliability

14.1 Introduction

14.2 To Change Time‐Dependent Event to Time‐Independent Event

14.3 To Deduce MTTF from Mean Microstructure Change to Failure

14.4 Summary

Index

End User License Agreement

List of Tables

Chapter 1

Table 1.1 5G technical requirements.

Chapter 2

Table 2.1 Cu surface diffusivity (cm

2

/sec).

Chapter 6

Table 6.1 Ideal scaling of MOS transistors.

Table 6.2 Scaling of local and global interconnections.

Table 6.3 Intel’s P856 Interconnect dimensions (0.25 um process).

Chapter 10

Table 10.1 Comparison between atomic flux and electron flux.

Table 10.2 Diffusivity at 100 °C.

List of Illustrations

Chapter 1

Figure 1.1 A sketch of the achievements of 2D IC of Si technology according ...

Figure 1.2 An image of part of the device structure of the mainframe compute...

Figure 1.3 The petals of flower, which shows the required functions in 4G an...

Figure 1.4 Scanning electron microscopy (SEM) image of the cross‐section of ...

Figure 1.5 (a) Synchrotron radiation tomographic images of a similar device ...

Figure 1.6 Schematic diagram of the cross‐section of a typical 3D IC device....

Figure 1.7 An example of electromigration electromigration‐induced failure o...

Chapter 2

Figure 2.1 General process of packaging procedure with lead‐frame.

Figure 2.2 Photo for lead‐frames.

Figure 2.3 First and second bonds in ultrasonic wire bonding.

Figure 2.4 General layout of tape circuit boards. Sprocket holes guide the t...

Figure 2.5 Tape‐automated bonding procedure. Inner lead bonds connect die to...

Figure 2.6 Schematic diagram of gang bonding. A press applies force to multi...

Figure 2.7 Schematic diagram of flipping chip to form bonds at multiple sold...

Figure 2.8 Schematic diagram of the cross‐section of a ceramic module joined...

Figure 2.9 Schematic diagram of the cross‐section of a C4 flip‐chip solder j...

Figure 2.10 Schematic diagram of the formation of a C‐4 solder joint of sold...

Figure 2.11 Schematic diagram of automatic self‐alignment process in the ref...

Figure 2.12 Schematic diagrams of the procedure in flip‐chip solder joint te...

Figure 2.13 Schematic diagram of the distribution of C‐4 solder joint on the...

Figure 2.14 Schematic diagram of the peripheral distribution I/O connections...

Figure 2.15 Schematic diagram and SEM image of Cu/solder/Cu micro‐bump.

Figure 2.16 SEM cross‐sectional image of side‐wall wetting and porous Cu

3

Sn ...

Figure 2.17 A plot of the I/O number per chip vs. various types of bonding t...

Figure 2.18 Effect of surface roughness on minimum bonding temperature.

Figure 2.19 Schematic diagram of the Cu‐to‐Cu interface. (a) The stress grad...

Figure 2.20 The surface morphology of a Cu surface analyzed by atomic force ...

Figure 2.21 (a) It shows the effect of surface roughness on the bonding time...

Figure 2.22 Cross‐sectional TEM images of voids in the Cu‐to‐Cu bonding inte...

Figure 2.23 (a) Plan‐view of TEM image of voids in the Cu‐to‐Cu bonding inte...

Figure 2.24 Kagawa et al. presented their void distribution for the Cu‐to‐Cu...

Figure 2.25 (a) A high‐resolution TEM image for a low‐angle grain boundary a...

Figure 2.26 Cross‐sectional focus ion beam (FIB) and electron back‐scatter d...

Figure 2.27 A plot of shear strength against bonding temperature of Cu pilla...

Figure 2.28 Schematic diagrams depict the effect of Cu dishing on hybrid bon...

Figure 2.29 Cross‐sectional SEM image of Cu interconnects with a pitch of ap...

Figure 2.30 It shows state‐of‐the‐art of hybrid Cu‐to‐Cu bonds using the SiC...

Figure 2.31 It shows the microstructures for a Cu‐to‐Cu joint after 1000 cyc...

Chapter 3

Figure 3.1 High resolution TEM images showing the atom migration under elect...

Figure 3.2 Schematic diagram of the periodic nanotwin structure by repetitio...

Figure 3.3 Biaxial stress in the model of calculation.

Figure 3.4 (a) Calculated curves showing the evolution of the total energies...

Figure 3.5 Schematic diagram depicts the in situ stress measurement system. ...

Figure 3.6 The evolution of the product of stress and film thickness as a fu...

Figure 3.7 Microstructures of pulsed electrodeposited randomly oriented nt‐C...

Figure 3.8 The schematic drawing for dislocation slip between two parallel t...

Figure 3.9 (a) FIB images of the both the top view and cross‐sectional view ...

Figure 3.10 Plan‐view EBSD showing the orientation of surface grains of the ...

Figure 3.11 Cross‐sectional FIB image of an electroplated [111]‐oriented nan...

Figure 3.12 Grain growth in [111] nt‐Cu film. Cross‐sectional FIB images for...

Figure 3.13

Transformation of the oriented (111) nt‐Cu to large grain (100) C

...

Figure 3.14 The growth of large (100) grains from the oriented (111) nt‐Cu. ...

Figure 3.15 (a) Cross‐sectional EBSD orientation image map for a SnAg micro‐...

Figure 3.16 Microstructures after solid‐state aging of nt‐Cu/solder/nt‐Cu at...

Figure 3.17 Cross‐sectional FIB image showing the microstructures of nt‐Cu f...

Figure 3.18 Schematic diagram of a void in the bonding interface. Under ther...

Figure 3.19 Microstructures analysis of the bonding interface for a [111] nt...

Figure 3.20 Schematic drawing for a fanout package. A chip is embedded in ep...

Figure 3.21 Tensile stress and strain curves for regular Cu and nt‐Cu films ...

Figure 3.22 Plot of yield strength against electrical and thermal conductivi...

Figure 3.23 Voids and oxidation formation in the nt‐Cu line after current st...

Chapter 4

Figure 4.1 (a) A circular solder mount or cap on a copper substrate. (b) The...

Figure 4.2 A schematic diagram of the cross‐section on an array of hemispher...

Figure 4.3 The physical meaning of C

b

and C

e

are, respectively, the equilibr...

Figure 4.4 A plot of φ(η) versus η.

Figure 4.5 In a sample having a very thin layer of Sn, when the Sn was compl...

Figure 4.6 SEM image of the opposite rows of IMC in a micro‐bump solder join...

Figure 4.7 (a) After reflow at 260 C for four minutes of the same SnAg solde...

Chapter 5

Figure 5.1 The growth of a single IMC phase, the “i” phase, between two term...

Figure 5.2 Free energy diagram of A (α‐phase) and B (β‐phase), and an IMC (i...

Figure 5.3 SEM image of the distribution of Kirkendall voids in the layer of...

Figure 5.4 A set of SEM cross‐sectional images of micro‐bumps after annealin...

Figure 5.5 A schematic diagram of cellular precipitation is shown. The cell ...

Figure 5.6 A schematic diagram of the growth of porous Cu

3

Sn is shown, where...

Figure 5.7 The pillar‐type samples are shown having various diameters, from ...

Figure 5.8 SEM images of 1 1 μm pillars after annealing at 195 °C for (a) 30...

Figure 5.9 (a and b) The change of IMC thickness with different diameters wh...

Figure 5.10 The mechanism of Cu interstitial diffusion into 1 μm pillar is d...

Chapter 6

Figure 6.1 IC design style: full‐custom.

Figure 6.2 IC design style: standard cell (row‐based).

Figure 6.3 IC design style: field programmable gate array (FPGA).

Figure 6.4 VLSI design process and flow.

Figure 6.5 Evolution of minimum feature sizes in semiconductor manufacturing...

Figure 6.6 Wire bonding in a BGA.

Figure 6.7 Flip chip bonding packages.

Figure 6.8 The package evolution: from MCM to HI.

Chapter 7

Figure 7.1 The trend of power density along the process advances.

Figure 7.2 (a) Cross section of an n‐type transistor. (b) Basic DRAM cell.

Figure 7.3 An n‐type transistor with channel length (L) and width (W) [3].

Figure 7.4 DRAM cell and block configurations [4]. (a) Schematic circuit for...

Figure 7.5 A typical 6T Static RAM cell.

Figure 7.6 Illustration of the performance/timing analysis in digital design...

Figure 7.7 Illustration of energy‐delay product (EDP) for the trade‐off.

Figure 7.8 A power network illustration.

Figure 7.9 A clock mesh/tree hybrid architecture for clock network.

Figure 7.10 An example of DVFS architecture chip.

Figure 7.11 Illustration of MSV designs.

Figure 7.12 In MSV designs, level shifters are needed for the signal traveli...

Figure 7.13 (a) Temperature distribution of a testcase using the thermal mod...

Chapter 8

Figure 8.1 Packaging hierarchy in interposer‐based 3D IC. CoWoS is one of th...

Figure 8.2 An illustration for high bandwidth memory (HBM) with interposer....

Figure 8.3 TSV fabrication options in 3D IC integration: via‐first, via‐midd...

Figure 8.4 Process flow of DRAM/logic die stacking module in [16]: (a) a thi...

Figure 8.5 Cross‐sectional view of single chip InFO_PoP with TIV (Through‐In...

Figure 8.6 3D power delivery model illustration.

Chapter 9

Figure 9.1 (a) It depicts a closed container keeping a fixed amount of water...

Figure 9.2 Two heat chambers at temperature of

T

1

and

T

2

, where the temperat...

Figure 9.3 Schematic diagram depicting electric conduction in a conductor of...

Figure 9.4 (a) Schematic diagram of flip chip technology, in which typically...

Figure 9.5 Schematic diagram depicting one‐dimensional heat conduction. Let ...

Figure 9.6 (a) SEM images of a set Al short stripes in electromigration. The...

Figure 9.7 Schematic diagram of a short Al strip patterned on a baseline of ...

Figure 9.8 Schematic diagram to depict a vacancy concentration gradient decr...

Figure 9.9 (a) Schematic diagram of a flip chip on a substrate, (b) the cros...

Figure 9.10 SEM cross‐sectional images of composite solder bump before and a...

Figure 9.11 (a) Schematic diagram depicts a row of 24 solder bumps from righ...

Figure 9.12 (a) Schematic diagram depicts a single metal wire of a given len...

Chapter 10

Figure 10.1 Schematic diagram depicting atomic diffusion in a face‐centered‐...

Figure 10.2 (a) SEM image of a straight Ni silicide line formed between two ...

Figure 10.3 (a) Schematic diagram of the cross‐section of an Al short stripe...

Figure 10.4 The lower schematic diagram (b), depicting a joint of an Al line...

Figure 10.5 (a) Schematic diagram of an in situ TEM samples, where the elect...

Figure 10.6 (a) Schematic diagram depicts a Cu interconnect conductor with a...

Figure 10.7 (a) The schematic diagram on the left side depicts a conductor w...

Figure 10.8 The upper row of SEM images shows a daisy chain of flip‐chip sol...

Chapter 11

Figure 11.1 We shall consider

J

in the equation between two points; point 1 ...

Figure 11.2 The temperature distribution on the cross‐section of a solder jo...

Figure 11.3 (a) Schematic diagram of a row of four composite solders, in whi...

Chapter 12

Figure 12.1 (a) The deposition of an Al thin film on a thick quartz substrat...

Figure 12.2 (a) It shows that the stresses act along the two principal axes ...

Figure 12.3 (a) We have enlarged one end of the substrate to show the neutra...

Figure 12.4 A hexagonal grain in a polycrystalline solid is under a shear st...

Figure 12.5 (a) SEM image of a Sn whisker between two Cu bumps having a top ...

Figure 12.6 (a) SEM image of Sn whiskers on a lead‐frame surface. (b) A shor...

Figure 12.7 Both (a) and (b) are electron diffraction pattern and cross‐sect...

Figure 12.8 A cross‐sectional view of a whisker on a bilayer of Sn/Cu. A cra...

Figure 12.9 SEM image of a Sn whisker on a leg of lead‐frame indicated by a ...

Figure 12.10 Synchrotron radiation micro‐diffraction was used to measure the...

Figure 12.11 The measured distribution of compressive stress in the surround...

Figure 12.12 To model the whisker growth, we assume an array of them, each h...

Figure 12.13 A set of four SEM images of the initiation and growth of a Sn w...

Chapter 13

Figure 13.1 Shows such an equipment for statistical analysis of failure of f...

Figure 13.2 Shows an optical image of such a test board having four chips on...

Figure 13.3 The layout of the solder joints between the chip and the board i...

Figure 13.4 Is a schematic diagram to illustrate the idea of lattice shift....

Figure 13.5 Shows the Weibull distribution plots of time to failure of a set...

Figure 13.6 All the failures showed a rather flat resistance change with tim...

Figure 13.7 (a) and (b) show the failure site images of the sample failed in...

Figure 13.8 (a) It shows that the location of RDL in the sample is near the ...

Figure 13.9 Simulation result in three different stressing conditions, from ...

Figure 13.10 (a) Cross‐sectional SEM image showing the test sample, (b) Top ...

Figure 13.11 In the test structure, there are two Si chips placed horizontal...

Guide

Cover Page

Title Page

Copyright Page

Preface

Table of Contents

Begin Reading

Index

Wiley End User License Agreement

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Electronic Packaging Science and Technology

King‐Ning Tu

National Chiao Tung University, Hsinchu, Taiwan, ROC

Chih Chen

Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, ROC

Hung‐Ming Chen

Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, ROC

This edition first published 2022© 2022 John Wiley & Sons, Inc.

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Library of Congress Cataloging‐in‐Publication Data

Names: Tu, K. N. (King‐Ning), 1937– author. | Chen, Chih, 1970– author. | Chen, Hung‐Ming, author.Title: Electronic packaging science and technology / King‐Ning Tu, University of California, Los Angeles, United States of America; Chih Chen, National Chiao Tung University, Hsinchu, Taiwain; Hung‐Ming Chen, National Chiao Tung University, Hsinchu, Taiwain.Description: 1st edition. | Hoboken, NJ : Wiley, 2022. | Includes bibliographical references and index.Identifiers: LCCN 2021039114 (print) | LCCN 2021039115 (ebook) | ISBN 9781119418313 (cloth) | ISBN 9781119418320 (adobe pdf) | ISBN 9781119418337 (epub)Classification: LCC TK7870.15 .T8 2022 (print) | LCC TK7870.15 (ebook) | DDC 621.381/046–dc23LC record available at https://lccn.loc.gov/2021039114LC ebook record available at https://lccn.loc.gov/2021039115

Cover image: © Andriy Onufriyenko/Getty ImagesCover design by Wiley

Preface

As we enter the big data era, mobile devices are ubiquitous. Internet of things (IoT) is everywhere, and we have man‐to‐man, man‐to‐machine, and machine‐to‐machine communications. Furthermore, in the Covid‐19 virus pandemic period, the trend of distance teaching, distance medicine, home office, and on‐line meeting has increased greatly the need of advanced consumer electronic products, demanding smaller form factor, larger memory, more functions, faster and larger data collection and transmission, cheaper cost, and superb reliability. At the same time, 5G advanced communication technology and 3D IC devices have begun their impact to our society, and many new artificial intelligence (AI) applications have been invented.

With the perceived slowing down of Moore’s law of miniaturization of Si chip technology, microelectronic industry is searching for alternative ways to sustain Moore’s law. 3D IC is most promising in achieving more‐than‐Moore, wherein the up‐scale of packaging technology is critical. Indeed, new advanced packaging factories are being built worldwide. We ask what will be the technical innovations in electronic packaging for 3D IC devices in order to enhance performance and reliability? Or, what are the challenging issues in electronic packaging technology that are essential in the near future development of semiconductor technology?

The goal of this book to present the science and engineering of advanced electronic packaging technology for a deeper understanding of the essence in development and manufacturing of the more‐than‐Moore technology. Especially, what is new in this book are the subjects of Cu‐to‐Cu direct bonding by using the (111) uni‐directionally oriented nanotwin Cu, innovative 3D IC systems in packaging integration for high performance of wide bandwidth and low power devices, and the analysis of mean‐time‐to‐failure equations based on entropy production.

After the introduction chapter, the following chapters will be divided into three parts. In Part I, the history of bonding technology will be covered in Chapter 2, starting from wire‐bonding, tab‐automated bonding, flip chip C‐4 solder joint bonding, micro‐bump bonding, Cu‐to‐Cu direct bonding, and hybrid bonding. The microstructure, properties, and applications of randomly oriented and (111) uni‐directionally oriented nano‐twin Cu will be covered in Chapter 3. Then, Chapter 4 and Chapter 5 will be dedicated to chemical reactions and kinetic processes in Cu‐Sn reactions for solder joint formation. Chapter 4 will review solid‐liquid interfacial diffusion (SLID) reactions between liquid solder and Cu. Chapter 5 will review solid‐solid reactions between solid solder and Cu. The kinetics of growth of intermetallic compound (IMC), which is a stoichiometric compound and has no composition gradient, has been an outstanding problem in solid‐solid reactions. We introduce Wagner’s diffusivity to overcome it.

Part II consists of chapters on electric circuit integration in packaging technology. The emphasis is on the design of low power devices and intelligent integration. The technical issues related to the need for faster rates and increased amounts of data transport in 2.5D/3D IC are discussed. It is explained how to increase the I/O density and the bandwidth in packaging technology.

Part III is a collection of chapters on reliability science. It begins with a chapter on irreversible processes of atomic flow, heat flow, and charge flow in open systems. The most important issue of Joule heating will be analyzed. The topics of electromigration, thermomigration, stress migration, and failure analysis will be covered. Equations of mean‐time‐to‐failure (MTTF) will be reanalyzed on the basis of entropy production.

Finally, in Chapter 14, a brief discussion on how to use artificial intelligence to accelerate reliability testing will be presented. We propose an x‐ray based graphic processing unit (X‐GPU) to analyze early reliability failure before it occurs in any newly developed 3D IC device for mass production. The goal of AI here is to change the time‐dependent and time‐consuming reliability tests to time‐independent tests. The basic idea of mean microstructure‐change to failure (MMTF) will be introduced, so that we can link MTTF to MMTF.

We appreciate the capable help of Mrs. Jody Lee and Mr. John Wu at NCTU in preparing the book.

Hsinchu, December 2020

King‐Ning TuChih ChenHung‐Ming Chen

Part I

2Cu‐to‐Cu and Other Bonding Technologies in Electronic Packaging

2.1 Introduction